CN116995068B - Chip integrated antenna packaging structure and packaging method - Google Patents

Abstract

The application provides a chip integrated antenna packaging structure and a packaging method. The chip integrated antenna packaging structure comprises a substrate, a rewiring layer, a filling layer, an antenna structure layer and packaging materials coated on the periphery. One side of the substrate far away from the rewiring layer is connected with the first functional chip and the substrate bonding pad. And one side of the filling layer, which is close to the substrate, is provided with a second functional chip and a third functional chip, the second functional chip and the third functional chip are electrically connected with the first functional chip and the substrate bonding pad, and the first functional chip is electrically connected with the substrate bonding pad. The antenna structure layer comprises a first antenna, a second antenna and signal ground, wherein the first antenna is electrically connected with the second functional chip, the second antenna is electrically connected with the third functional chip, and the signal ground is respectively electrically connected with the first antenna and the second antenna. The substrate bonding pad is used for leading out the electricity. The high-frequency signal transmission path can be shortened, the power consumption of the packaging antenna and the attenuation of electromagnetic waves can be reduced, and the performance of the chip integrated antenna packaging structure can be improved.

Description

Chip integrated antenna packaging structure and packaging method

Technical field

The present application relates to the field of semiconductor manufacturing technology, and specifically to a chip integrated antenna packaging structure and packaging method.

Background technique

The iteration speed of Moore's Law is slowing down. Starting from system applications, overall performance improvement relies on advanced packaging technology. In the technological evolution of silicon-based semiconductors, the number of transistors doubles every year every 18 to 24 months, doubling chip performance or reducing costs by half. This law is called "Moore's Law." The cost advantage and first-mover advantage brought by advanced processes have made semiconductor manufacturers have been committed to reducing feature sizes. Now, as the research and development threshold for new technologies required to continue Moore's Law has increased and the research and development cycle has lengthened, iterations of process technology require costs. It takes longer and the cost increases significantly. The industry believes that system heterogeneous integration is one of the key technologies to improve system performance and reduce costs, which requires relying on advanced packaging technology.

Advanced packaging is judged based on the advancement of the internal packaging process and is classified based on whether there is a substrate for internal connections. The division point of advanced packaging lies in the advancement of process and packaging technology. Advanced packaging can be divided into two parts based on whether there is a carrier (substrate) for internal connection: 1) With carrier (substrate type): Internal packaging needs to rely on substrate and lead frame Or interposer, the main internal interconnection adopts flip chip packaging method, which can be divided into single chip or multi-chip packaging. Multi-chip packaging will have multiple chips on the interposer (or substrate) Side by side or stacked to form a 2.5D/3D structure. External packages under the substrate include BGA (ball grid array, ball grid array package), LGA (landgrid array, plane grid array package), CSP (chip scale package, chip scale package), etc. The overall package consists of internal and external components It is a combination of packaging. Currently, the most representative and widely used combinations in the industry include FCBGA (flip-chip BGA), Embedded SiP (EmbeddedSystem In Package, embedded system-level packaging), and 2.5D/3D Integration (heterogeneous integration). . 2) Carrierless (wafer level): No substrate, lead frame or interposer is required, represented by wafer level packaging, using redistribution layers (RDL) and bumping (Bumping) as I/O wrappers Line means, and then use the inverted method to directly connect to the PCB board, and the package thickness becomes thinner than with a carrier. Advanced packaging focuses on reducing size, system integration, increasing the number of I/Os, and improving heat dissipation performance. It can include single-chip and multi-chip. Flip-chip packaging and wafer-level packaging are widely used, coupled with interconnection technology ( TSV, Bump, etc.) have improved their technical capabilities and promoted the advancement of packaging. Internal and external packaging can be combined to form different high-performance packaging products.

Advanced packaging technology is mainly developed for silicon-based processes. For GaAs (gallium arsenide)-based chips, due to the use of different process technologies, the compatibility of its packaging technology is lower than that of silicon-based CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) process. Flash technology chip. In future 5G/6G communication chips, in order to achieve long-distance high signal-to-noise ratio signal transmission requirements, it is necessary to combine the advantages of silicon-based chips and GaAs chips for heterogeneous integrated packaging, and to package the antenna within the chip as much as possible. However, existing packaging technology cannot meet the requirements for heterogeneous integrated packaging of millimeter wave communication chips.

Contents of the invention

In view of the shortcomings of related technologies, this application proposes a chip integrated antenna packaging structure and packaging method to solve the problem in related technologies that cannot meet the requirements of heterogeneous integrated packaging of millimeter wave communication chips.

The present application provides a chip integrated antenna packaging structure. The chip integrated antenna packaging structure includes: a substrate, a rewiring layer, a filling layer, an antenna structure layer and packaging materials. The substrate includes an opposite first surface and a second surface, and the first surface of the substrate is connected to the first functional chip and the substrate pad. The redistribution layer is located on the second surface of the substrate, and the redistribution layer is electrically connected to the first functional chip and the substrate pad through the substrate. The filling layer is located on a side of the rewiring layer away from the substrate. A second functional chip and a third functional chip are provided on the side of the filling layer close to the substrate. The second functional chip passes through the rewiring layer in sequence. The wiring layer and the substrate are electrically connected to the first functional chip and the substrate pad respectively. The third functional chip passes through the rewiring layer and the substrate in sequence and is connected to the first functional chip and the substrate pad respectively. The substrate pads are electrically connected, and the first functional chip is electrically connected to the substrate pads through the redistribution layer, the substrate, and the substrate pads. The antenna structure layer is located on the side of the filling layer away from the redistribution layer. The antenna structure layer includes a first antenna, a second antenna and a signal ground. The first antenna and the second antenna are respectively used for signals. For transmitting and receiving, the first antenna is electrically connected to the second functional chip, the second antenna is electrically connected to the third functional chip, and the signal ground is respectively connected to the first antenna and the third functional chip. The two antennas are electrically connected. The packaging material covers the outside of the substrate, the rewiring layer, the filling layer and the antenna structure layer that are stacked in sequence, and at least part of the packaging material exposes the substrate pad, and the substrate The pads are used to lead out electrical connections.

According to the above embodiments, in this application, functional chips are integrated on the upper and lower sides of the substrate in the chip integrated antenna packaging structure, and the antenna structure layer is introduced to form an antenna radio frequency circuit in the chip integrated antenna packaging structure. Compared with the structure in the related art in which the antenna is arranged outside the chip, the first functional chip in the three-dimensional packaging structure in this application is located below the substrate, and the second functional chip and the third functional chip are located above the substrate. Signals can be transmitted vertically between chips through the substrate and the rewiring layer, further shortening the signal transmission distance. And because the wiring in the rewiring layer is relatively precise, the transmission path of high-frequency signals can be significantly shortened, and the power consumption of the packaged antenna can be reduced. The attenuation of electromagnetic waves improves the performance of the chip integrated antenna packaging structure. In addition, due to the smaller size of the integrated antenna in the chip package space, the transmission distance of high-frequency signals is shorter, so the high-frequency signal transmission link loss is lower, the transmitting antenna can radiate more power, and the receiving antenna can receive more For weak signals, the dynamic range of the packaged chip is higher, providing support for higher efficiency, lower latency, and more portable communication technology.

In one embodiment, the substrate has an interconnection via connecting the first surface and the second surface, and an end of the interconnection via close to the first surface is soldered to the substrate. The disk and the first functional chip are connected, and one end of the interconnection via close to the second surface is electrically connected to the second functional chip and the third functional chip through the redistribution layer.

In one embodiment, the rewiring layer includes at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer.

In one embodiment, the first functional chip includes a frequency synthesizer chip, the second functional chip includes a power amplifier chip, and the third functional chip includes a low noise amplifier chip.

In one embodiment, the filling layer is provided with at least four metal support columns, and the metal support columns include a first metal support column, a second metal support column, a third metal support column and a fourth metal support column, so One end of the first metal support column is connected to the first antenna, and the other end is electrically connected to the second functional chip; one end of the second metal support column is connected to the signal ground, and the other end is connected to the third functional chip. The two functional chips are electrically connected; one end of the third metal support column is connected to the signal ground, the other end is electrically connected to the third functional chip, and one end of the fourth metal support column is connected to the second antenna , the other end is electrically connected to the third functional chip.

In one embodiment, the antenna structure layer includes a signal ground, a dielectric layer and an antenna stacked sequentially in a direction from the filling layer to the antenna structure layer, and the antenna includes the first antenna and the third antenna. Two antennas. The first antenna includes a plurality of first radiating units distributed along a straight line connected by a first feed line, and the second antenna includes a plurality of second radiating units distributed along a straight line connected by a second feed line.

This application also provides a packaging method for a chip integrated antenna packaging structure, including:

Forming a sequentially stacked substrate and a rewiring layer, the substrate includes an opposite first side and a second side, the rewiring layer is located on the second side of the substrate, and a plurality of rewiring layers are formed on the first side of the substrate. The substrate pad is used to lead out the electricity;

Fixedly connecting a first functional chip to the first surface of the substrate and coating the surface of the first functional chip with protective glue;

A second functional chip and a third functional chip are formed on the side of the rewiring layer away from the substrate. The second functional chip and the third functional chip pass through the rewiring layer, the substrate and the substrate in sequence respectively. The first functional chip is electrically connected;

At least four metal support pillars are formed on a side of the redistribution layer away from the substrate. The size of the metal support pillars in the direction from the first surface to the second surface of the substrate is larger than that of the second functional chip. , the size of the third functional chip in the direction from the first surface of the substrate to the second surface; the metal support pillar includes a first metal support pillar, a second metal support pillar, a third metal support pillar and a third metal support pillar. Four metal support pillars, the first metal support pillar and the second metal support pillar are electrically connected to the second functional chip respectively, the third metal support pillar and the fourth metal support pillar are respectively connected to the The third function chip is electrically connected;

An antenna structure layer is formed on the side of the metal support pillar away from the redistribution layer. The antenna structure layer includes a first antenna, a second antenna and a signal ground. The first antenna passes through the first metal support pillar. The second antenna is electrically connected to the third functional chip through the fourth metal support pillar, and the signal ground is electrically connected to the second functional chip through the second metal support pillar. The functional chip is electrically connected, and the signal ground is electrically connected to the third functional chip through the third metal support pillar;

Glue material is filled between the rewiring layer and the antenna structure layer, and the glue material at least partially covers the metal support pillar, the second functional chip and the third functional chip, and the glue material , the metal support pillar, the second functional chip and the third functional chip jointly form a filling layer;

Remove the protective glue on the surface of the first functional chip;

Encapsulating material is coated on the outside of the substrate, the rewiring layer, the filling layer and the antenna structure layer that are stacked in sequence;

Etching the packaging material to expose at least a partial area of the packaging material to expose the substrate pad and electroplating the substrate pad to be flush with the surface of the packaging material;

A metal solder ball is formed on a side of the substrate pad away from the substrate.

According to the above embodiments, it can be seen that this embodiment is based on the through silicon via (TSV) technology and rewiring technology in the semiconductor manufacturing process. The second function chip and the third function chip are fixed through metal support pillars and glue in the chip integrated antenna packaging structure. The chip also realizes the circuit connection within the packaging structure. The first functional chip is designed on the first side of the substrate, and the second functional chip and the third functional chip are designed on the rewiring layer, which can realize vertical signal transmission and can significantly shorten the high frequency signal transmission path, so the high-frequency signal transmission link loss is lower, the transmitting antenna can radiate greater power, the receiving antenna can receive weaker signals, and the dynamic range of the packaged chip is higher, which provides a higher efficiency ratio and more Low-latency, more portable communication technology provides support.

In one embodiment, the substrate and the redistribution layer are stacked in sequence, the substrate includes an opposite first side and a second side, the redistribution layer is located on the second side of the substrate, and the substrate A plurality of substrate pads are formed on the first side for electrical leads, including:

A wafer is provided, and a plurality of blind vias are formed on the front side of the wafer;

Fill the blind hole with conductive material;

A rewiring layer is formed on the front side of the wafer, the rewiring layer includes at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer;

Form a plurality of redistribution layer micro pads on the side of the redistribution layer away from the wafer;

Perform a thinning process on the back of the wafer to expose the conductive material in the blind hole to form interconnection vias on the back of the wafer to obtain the substrate;

A plurality of the substrate pads are formed on the back side of the substrate, and the substrate pads are electrically connected to the rewiring layer through the interconnection via holes.

In one embodiment, an antenna structure layer is formed on the side of the metal support pillar away from the redistribution layer. The antenna structure layer includes a first antenna, a second antenna and a signal ground. The first antenna The second antenna is electrically connected to the second functional chip through the first metal support pillar, the second antenna is electrically connected to the third functional chip through the fourth metal support pillar, and the signal ground is electrically connected to the second functional chip through the second metal support pillar. The metal support pillar is electrically connected to the second functional chip, and the signal ground is electrically connected to the third functional chip through the third metal support pillar, which specifically includes:

Provide organic substrates;

A first metal layer is formed on the front side of the organic substrate, and the first metal layer includes a first antenna and a second antenna;

Several metal vias are formed at the ports of the first antenna and the second antenna respectively;

A second metal layer is formed on the back side of the organic substrate, and several metal pads are formed on the second metal layer. The side of the metal pads away from the back side of the organic substrate is in contact with the side on the organic substrate. The metal via holes are connected correspondingly, and the side of the metal pad close to the back side of the organic substrate is connected correspondingly to the position of the metal support pillar on the filling layer.

In one embodiment, the first metal layer is formed on the front side of the organic substrate, and the first metal layer includes a first antenna and a second antenna. Specifically, the first metal layer includes:

A group of several first radiating units distributed along a straight line and connected by a first feed line are formed on the front side of the organic substrate, and a group of a plurality of second radiating units distributed along a straight line and connected by a second feeding line are formed on the front side of the organic substrate.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and will be obvious from the description, or may be learned by practice of the invention.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Figure 1 shows a schematic structural diagram of a chip integrated antenna packaging structure provided by an embodiment of the present application;

Figure 2 shows the working principle diagram of the chip integrated antenna packaging structure shown in Figure 1;

Figure 3 shows a top view of the antenna structure layer in the chip integrated antenna packaging structure shown in Figure 1;

Figure 4 shows a schematic cross-sectional view of the antenna structure layer along the dotted line AA’ in the chip integrated antenna packaging structure shown in Figure 3;

Figure 5 shows a top view of the antenna structure layer in the chip integrated antenna packaging structure shown in Figure 3;

Figure 6 shows a schematic flow chart of a packaging method for a chip integrated antenna packaging structure provided by an embodiment of the present application;

Figures 6a to 6k show a schematic structural diagram of each step in the packaging method shown in Figure 6;

Figure 7 shows a schematic flow chart of a method for preparing a substrate and a rewiring layer in a packaging method for a chip integrated antenna packaging structure provided by an embodiment of the present application;

Figures 7a to 7k show schematic structural diagrams of each step in the preparation method shown in Figure 7;

FIG. 8 is a schematic flow chart of the preparation method of the antenna structural layer shown in FIGS. 3 to 5 .

Among them: 100-substrate; 101-first side; 102-second side; 110-interconnection via hole; 111-power input interconnection via hole; 112-power output interconnection via hole; 113-reference positive voltage interconnection Through hole; 114 - reference negative voltage interconnection via hole; 103 - substrate micro pad; 200 - rewiring layer; 201 - rewiring layer micro pad; 210 - metal wiring layer; 211 - first metal wiring layer; 212 -Second metal wiring layer; 213-Third metal wiring layer; 220-Dielectric layer; 300-Filling layer; 310-Second functional chip; 320-Third functional chip; 330-Metal support pillar; 331-First metal Support pillar; 332-the second metal support pillar; 333-the third metal support pillar; 334-the fourth metal support pillar; 340-the second micro metal ball; 341-the second functional chip power input pin; 342-the second Functional chip power output pin; 343-Second function chip signal input pin; 344-Second function chip signal output pin; 350-Third micro metal ball; 351-Third function chip power input pin; 352- The power output pin of the third function chip; 353-the signal input pin of the third function chip; 354-the signal output pin of the third function chip; 400-antenna structural layer; 410-the first antenna; 411-the first feeder line; 412-first radiating unit; 420-second antenna; 421-second feed line; 422-second radiating unit; 430-signal ground; 440-metal via; 450-metal pad; 500-packaging material; 600 -The first functional chip; 601-amplifier; 602-filter; 603-mixer; 604-frequency multiplier; 605-analog-to-digital converter; 606-digital-to-analog converter; 607-baseband signal; 608-standard frequency Input terminal; 610-first micro metal ball; 611-first function chip power input pin; 612-first function chip power output pin; 613-first function chip signal input pin; 614-first function chip Signal output pin; 700-substrate pad; 710-first substrate pad; 720-second substrate pad; 730-third substrate pad; 740-fourth substrate pad; 800-metal solder ball; 900 -Protective glue, 001-wafer.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings refer to the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the appended claims.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "the" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

Research has found that the packaging technology in advanced packaging mainly focuses on the process development of silicon-based chips. For gallium arsenide chips, because GaAs-based chips use different process technologies, their packaging technology compatibility is lower than that of silicon-based chips. In future 5G/6G communication chips, in order to achieve long-distance high signal-to-noise ratio signal transmission requirements, it is necessary to combine the advantages of silicon-based chips and GaAs chips for heterogeneous integrated packaging, and to package the antenna within the chip as much as possible. However, related packaging technologies still cannot solve the problem of heterogeneous integrated packaging requirements for millimeter wave communication chips.

This application provides a chip integrated antenna packaging structure and packaging method, aiming to solve the above technical problems of related technologies.

The packaging structure and packaging method of the chip integrated antenna in the embodiment of the present application will be described in detail below with reference to the accompanying drawings. Features in the embodiments described below may complement each other or be combined with each other unless they conflict.

This application provides a chip integrated antenna packaging structure and packaging method. As shown in Figure 1, the chip integrated antenna packaging structure includes: a substrate 100, a rewiring layer 200, a filling layer 300, an antenna structure layer 400 and a packaging material 500. The substrate 100 includes an opposite first surface 101 and a second surface 102. The first surface 101 of the substrate 100 is connected to the first functional chip 600 and the substrate pad 700. The redistribution layer 200 is located on the second surface 102 of the substrate 100, and the redistribution layer 200 is electrically connected to the first functional chip 600 and the substrate pad 700 through the substrate 100. The filling layer 300 is located on the side of the rewiring layer 200 away from the substrate 100. The filling layer 300 is provided with a second functional chip 310 and a third functional chip 320 on the side close to the substrate 100. The second functional chip 310 passes through the rewiring layer 200, The substrate 100 is electrically connected to the first functional chip 600 and the substrate pad 700 respectively. The third functional chip 320 is electrically connected to the first functional chip 600 and the substrate pad 700 respectively through the rewiring layer 200 and the substrate 100. The first functional chip 600 is electrically connected to the substrate pad 700 through the redistribution layer 200, the substrate 100, and the substrate pad 700. The antenna structure layer 400 is located on the side of the filling layer 300 away from the redistribution layer 200. The antenna structure layer 400 includes a first antenna 410, a second antenna 420 and a signal ground 430. The first antenna 410 and the second antenna 420 are respectively used for signal grounding. For transmitting and receiving, the first antenna 410 is electrically connected to the second functional chip 310, the second antenna 420 is electrically connected to the third functional chip 320, and the signal ground 430 is electrically connected to the first antenna 410 and the second antenna 420 respectively. The packaging material 500 covers the outside of the substrate 100, the rewiring layer 200, the filling layer 300 and the antenna structure layer 400 that are stacked in sequence. At least part of the packaging material 500 exposes the substrate pad 700. The substrate pad 700 is used to connect the electrical circuit to the substrate. Sexual elicitation.

According to the above embodiments, in this application, functional chips are integrated on the upper and lower sides of the substrate 100 in the chip integrated antenna packaging structure, and the antenna structure layer 400 is introduced to form an antenna radio frequency circuit in the chip integrated antenna packaging structure. Compared with the structure in the related art in which the antenna is arranged outside the chip, the first functional chip 600 in the three-dimensional packaging structure in this application is located below the substrate 100, and the second functional chip 310 and the third functional chip 320 are located on the substrate. Above 100, vertical signal transmission can be realized between functional chips through the substrate 100 and the rewiring layer 200, further shortening the signal transmission distance, and due to the relatively precise wiring in the rewiring layer 200, the transmission path of high-frequency signals can be significantly shortened. , reduce the power consumption of the packaged antenna and the attenuation of electromagnetic waves, and improve the performance of the chip integrated antenna packaging structure. In addition, due to the smaller size of the integrated antenna in the chip package space, the transmission distance of high-frequency signals is shorter, so the high-frequency signal transmission link loss is lower, the transmitting antenna can radiate more power, and the receiving antenna can receive more For weak signals, the dynamic range of the packaged chip is higher, providing support for higher efficiency, lower latency, and more portable communication technology.

In some embodiments, as shown in FIG. 1 , the substrate 100 has an interconnection through hole 110 inside that connects the first surface 101 and the second surface 102 . An end of the interconnection through hole 110 close to the first surface 101 is soldered to the substrate. The disk 700 and the first functional chip 600 are connected, and one end of the interconnection via 110 close to the second surface 102 is electrically connected to the second functional chip 310 and the third functional chip 320 through the redistribution layer 200 .

In this embodiment, interconnection vias 110 are provided inside the substrate 100 to electrically connect the first functional chip 600, the second functional chip 310, the third functional chip 320 and the substrate pad 700 to realize circuit transmission. Improve the connection accuracy of the circuit transmission structure and avoid chip failure caused by interruptions between circuits.

In one example, as shown in FIG. 1 , the interconnection vias 110 include a power input interconnection via 111 (VCC interconnection via), a power output interconnection via 112 (GND interconnection via), a reference positive voltage interconnection via 113 (Ref+interconnection via) and reference negative voltage interconnection via 114 (Ref-interconnection via). The substrate pad 700 includes a first substrate pad 710 , a second substrate pad 720 , a third substrate pad 730 and a fourth substrate pad 740 . The power input interconnection through hole 111 is close to one end of the first surface 101 and the second substrate pad 700 . The substrate pad 720 is connected, and one end of the power input interconnection via hole 111 close to the second surface 102 is electrically connected to the second functional chip 310 and the third functional chip 320 through the rewiring layer 200. At the same time, the power input interconnection via hole 111 is close to the second functional chip 310 and the third functional chip 320. One end of the two surfaces 102 is electrically connected to the first functional chip 600 through the redistribution layer 200 and the substrate 100 . One end of the power output interconnection via hole 112 close to the first surface 101 is connected to the first substrate pad 710 , and one end of the power output interconnection via hole 112 close to the second surface 102 is electrically connected to the second functional chip 310 and the third functional chip 320 . connect. At the same time, one end of the power output interconnection via 112 close to the second surface 102 is electrically connected to the first functional chip 600 through the redistribution layer 200 and the substrate 100 . The reference positive voltage interconnection via 113 is electrically connected to the first functional chip 600 through the redistribution layer 200 and the substrate 100 . The reference negative voltage interconnection via 114 is electrically connected to the first functional chip 600 through the redistribution layer 200 and the substrate 100 . It should be noted that this example only provides one possible circuit connection method, which can be flexibly set by those skilled in the art and is not limited to this.

In some embodiments, the redistribution layer 200 includes at least one metal wiring layer 210 and a dielectric layer 220 wrapping the metal wiring layer 210 .

In one example, as shown in FIG. 1 , the rewiring layer 200 includes a first metal wiring layer 211 , a second metal wiring layer 212 , and a third metal wiring layer 213 that are sequentially stacked in the direction of the substrate 100 toward the rewiring layer 200 . , the first metal wiring layer 211 includes a metal line connected to the power input interconnection via 111 and a metal line connected to the reference positive voltage interconnection via 113, and the second metal wiring layer 212 includes a power output interconnection via 112 The connected metal lines, the metal lines connected to the reference negative voltage interconnection via 114 and the radio frequency metal lines electrically connected to the second functional chip 310 and the third functional chip 320, the third metal wiring layer 213 includes a plurality of rewiring layers Micro pads 201 and metal lines connected to the micro pads 201 of the redistribution layer. In this example, a multi-layer metal wiring layer 210 is provided to ensure the signal quality of the packaged device.

In some embodiments, the first functional chip 600 includes a frequency synthesizer chip, the second functional chip 310 includes a power amplifier chip, and the third functional chip 320 includes a low noise amplifier chip.

Exemplarily, Figure 2 shows an antenna radio frequency circuit formed by a chip integrated antenna packaging structure in this embodiment, in which the first antenna 410 is a transmitting antenna, the second antenna 420 is a receiving antenna, and the first functional chip 600 is a frequency In the synthesizer chip, the second functional chip 310 is a power amplifier chip, and the third functional chip 320 is a low-noise amplifier chip. The frequency synthesizer chip is equipped with a standard frequency input terminal 608, a baseband signal 607, an amplifier 601, a filter 602, a mixer 603, a frequency multiplier 604, an analog-to-digital converter 605 (ADC, Analog to Digital Converter) and a digital A working circuit is formed by electrical connection between the digital to analog converter (DAC) 606 (DAC).

In some embodiments, as shown in FIG. 1 , a plurality of first micro-metal balls 610 are provided on the side of the first functional chip 600 close to the substrate 100 . The first micro-metal balls 610 include the first functional chip power input pin 611 , the first functional chip power output pin 612, the first functional chip signal input pin 613 and the first functional chip signal output pin 614. A plurality of substrate micro-pads 103 are provided on the first surface 101 of the substrate 100. The first functional chip 600 is fixedly connected to the substrate micro-pads 103 through the first micro-metal balls 610.

In some embodiments, as shown in FIG. 1 , a plurality of second micro-metal balls 340 are provided on the side of the second functional chip 310 close to the redistribution layer 200 . The second micro-metal balls 340 include the power input pins of the second functional chip. pin 341, the second function chip power output pin 342, the second function chip signal input pin 343 and the second function chip signal output pin 344. It should be noted that the second functional chip 310 is a power amplifier chip, so two second functional chip power input pins 341 and second functional chip power output pins 342 are respectively provided to increase the current draining capability.

In some embodiments, as shown in FIG. 1 , a plurality of third micro-metal balls 350 are provided on the side of the third functional chip 320 close to the redistribution layer 200 . The third micro-metal balls 350 each include a third functional chip power input. Pin 351, the third function chip power output pin 352, the third function chip signal input pin 353 and the third function chip signal output pin 354. The rewiring layer 200 is provided with multiple rewiring layers on one side close to the filling layer 300. The wiring layer micro pad 201, the second micro metal ball 340, and the third micro metal ball 350 are respectively fixedly connected to the rewiring layer micro pad 201.

In some embodiments, as shown in FIG. 1 , the filling layer 300 is provided with at least four metal support pillars 330 , and the metal support pillars 330 include a first metal support pillar 331 , a second metal support pillar 332 , and a third metal support pillar 333 . and a fourth metal support pillar 334. One end of the first metal support pillar 331 is connected to the first antenna 410, and the other end is electrically connected to the second functional chip 310. One end of the second metal support pillar 332 is connected to the signal ground 430 , and the other end is electrically connected to the second functional chip 310 . One end of the third metal support pillar 333 is connected to the signal ground 430 , and the other end is electrically connected to the third functional chip 320 . One end of the fourth metal support pillar 334 is connected to the second antenna 420 , and the other end is electrically connected to the third functional chip 320 .

In this embodiment, by using metal support pillars 330 to connect the first antenna 410 and the second antenna 420 to the second functional chip 310 and the third functional chip 320 respectively, the functional chip and antenna in the chip integrated antenna packaging structure can be realized. precise electrical connections.

Specifically, the signal transmission path of the chip integrated antenna packaging structure in this embodiment is radio frequency signal-second antenna 420-fourth metal support pillar 334-third functional chip signal input pin 353-third functional chip 320-third Functional chip signal output pin 354 - First functional chip signal input pin 613 - First functional chip 600 - First functional chip signal output pin 614 - Second functional chip signal input pin 343 - Second functional chip 310 - The second functional chip signal output pin 344 - the first metal support pillar 331 - the first antenna 410 - transmits the signal. The chip packaging structure in this embodiment shortens the signal transmission link by distributing the first functional chip 600, the second functional chip 310 and the third functional chip 320, the first antenna 410 and the second antenna 420 in a compact manner, so that the signal Vertical transmission can shorten communication delay and reduce energy loss.

In some embodiments, as shown in FIG. 1 , the antenna structure layer 400 includes a signal ground 430 , a dielectric layer and an antenna stacked sequentially in the direction from the filling layer 300 to the antenna structure layer 400 . The antenna includes a first antenna 410 and a second antenna. Antenna 420. As shown in FIG. 3 , the first antenna 410 includes a plurality of first radiating units 412 distributed along a straight line and connected by a first feeder 411 . The second antenna 420 includes a plurality of first radiating units 412 connected by a second feeder 421 and distributed along a straight line. The second radiation unit 422.

In this embodiment, the first antenna 410 and the second antenna 420 are respectively provided with multiple linearly distributed radiating units. Compared with the related art, distributing the antennas in different layers will reduce the radiation efficiency and cause interference. In this example, the first antenna 410 and the second antenna 420 are arranged on the same layer, which can avoid mutual interference between the antennas and significantly improve the antenna radiation efficiency. In addition, the antenna in this application is located on the same layer, the connection layout with each functional chip is more reasonable, and the transmission line is shorter, which can further shorten the communication delay and reduce energy loss.

In one example, Figures 3 to 5 are respectively a top view of the antenna structure layer 400, a cross-sectional view along the dotted line AA' in the top view, and a bottom view. As shown in Figure 3, the first antenna 410 includes a A feeder 411 connects four first radiating units 412 distributed along a straight line, and the second antenna 420 includes four second radiating units 422 connected by a second feeder 421 distributed along a straight line. The projection of each first radiating unit 412 or second radiating unit 422 on the antenna structure layer 400 is a square with a cut angle, and the first radiating unit 412 or the second radiating unit 422 respectively constitute a circularly polarized antenna. It should be noted that the first antenna 410 and the second antenna 420 in this embodiment are both circularly polarized antennas. Those skilled in the art can also design linearly polarized antennas without corner cutting according to actual needs. This application No specific restrictions are made.

In some embodiments, as shown in FIG. 4 , the antenna structure layer 400 is provided with a plurality of metal vias 440 penetrating the upper and lower sides. The metal vias 440 are close to one side of the first antenna 410 , the second antenna 420 and the third antenna 420 . The ports of the first antenna 410 and the second antenna 420 are connected, as shown in Figure 5. The side of the metal via 440 close to the signal ground 430 is connected to the metal pad 450 on the back of the antenna structure layer 400. The metal welding pad on the back of the antenna structure layer 400 The disk 450 is electrically connected to the second metal support pillar 332 and the third metal support pillar 333 .

Based on the same inventive concept, this application also provides a packaging method for a chip integrated antenna packaging structure, as shown in Figure 6 and Figures 6a to 6j, which includes the following steps:

Step S101: As shown in Figure 6a, a sequentially stacked substrate 100 and a redistribution layer 200 are formed. The substrate 100 includes an opposite first surface 101 and a second surface 102. The redistribution layer 200 is located on the second surface 102 of the substrate 100. A plurality of substrate pads 700 are formed on the first surface 101 of the substrate 100 for electrical extraction.

Step S102: As shown in FIG. 6b, the first functional chip 600 is fixedly connected to the first surface 101 of the substrate 100 and the surface of the first functional chip 600 is covered with the protective glue 900.

Step S103: As shown in FIG. 6c, a second functional chip 310 and a third functional chip 320 are formed on the side of the rewiring layer 200 away from the substrate 100. The second functional chip 310 and the third functional chip 320 pass through the rewiring layer in sequence respectively. 200. The substrate 100 is electrically connected to the first functional chip 600.

Step S104: As shown in FIG. 6d, at least four metal support pillars 330 are formed on the side of the redistribution layer 200 away from the substrate 100. The metal support pillars 330 point in the direction of the second surface 102 along the first surface 101 of the substrate 100. The size is larger than the size of the second functional chip 310 and the third functional chip 320 in the direction along the first surface 101 of the substrate 100 pointing toward the second surface 102 . The metal support pillar 330 includes a first metal support pillar 331, a second metal support pillar 332, a third metal support pillar 333 and a fourth metal support pillar 334. The first metal support pillar 331 and the second metal support pillar 332 are respectively connected with the second metal support pillar 331. The functional chip 310 is electrically connected, and the third metal support pillar 333 and the fourth metal support pillar 334 are electrically connected to the third functional chip 320 respectively.

Step S105: As shown in Figure 6e, form an antenna structure layer 400 on the side of the metal support pillar 330 away from the redistribution layer 200. The antenna structure layer 400 includes a first antenna 410, a second antenna 420 and a signal ground 430. The first antenna 410 is electrically connected to the second functional chip 310 through the first metal support pillar 331, the second antenna 420 is electrically connected to the third functional chip 320 through the fourth metal support pillar 334, and the signal ground 430 is electrically connected to the second functional chip 320 through the second metal support pillar 332. The functional chip 310 is electrically connected, and the signal ground 430 is electrically connected to the third functional chip 320 through the third metal support pillar 333 .

Step S106: As shown in Figure 6f, fill the space between the rewiring layer 200 and the antenna structure layer 400 with glue material. The glue material at least partially covers the metal support pillar 330, the second functional chip 310 and the third functional chip 320. The glue material , the metal support pillar 330, the second functional chip 310 and the third functional chip 320 together form the filling layer 300.

Step S107: As shown in Figure 6g, remove the protective glue 900 on the surface of the first functional chip 600.

Step S108: As shown in FIG. 6h, encapsulating material 500 is coated on the outside of the sequentially stacked substrate 100, redistribution layer 200, filling layer 300 and antenna structure layer 400.

Step S109: As shown in Figures 6i and 6j, the packaging material 500 is etched so that at least part of the packaging material 500 exposes the substrate pad 700, and the substrate pad 700 is electroplated until it is flush with the surface of the packaging material 500.

Step S110: As shown in FIG. 6k , a metal solder ball 800 is formed on the side of the substrate pad 700 away from the substrate 100 .

This embodiment is based on through silicon via (TSV) technology and rewiring technology in the semiconductor manufacturing process. The second functional chip 310 and the third functional chip 320 are fixed and implemented in the chip integrated antenna packaging structure through metal support pillars 330 and glue. For circuit connection within the package structure, the first functional chip 600 is designed on the first side 101 of the substrate 100, and the second functional chip 310 and the third functional chip 320 are designed on the rewiring layer 200, which can realize vertical transmission of signals and significantly improve The transmission path of high-frequency signals is shortened, so the high-frequency signal transmission link loss is lower, the transmitting antenna can radiate greater power, the receiving antenna can receive weaker signals, and the dynamic range of the packaged chip is higher, providing higher efficiency. It provides support for communication technologies that are faster, lower-latency, and more portable.

In one example, the packaging method specifically includes the following steps: as shown in FIG. 6a , providing a substrate 100 and a rewiring layer 200 that are stacked in sequence. As shown in Figure 6b, the CMOS frequency synthesizer chip is attached to the first surface 101 of the substrate 100 using flip-chip soldering technology and is coated with soluble organic glue for protection. As shown in Figure 6c, flip-chip soldering technology is used to attach the gallium arsenide power amplifier chip and the gallium arsenide low-noise amplifier chip to the redistribution layer 200. As shown in Figure 6d, six copper pillars are welded on the side of the redistribution layer 200 away from the substrate 100. The diameter of the copper pillars is 20 μm and the height is 100 μm. Four of the copper pillars are respectively connected to the metal solder joints on the redistribution layer 200, and the other two copper pillars are used to strengthen the support. As shown in Figure 6e, the prepared organic substrate 100 and the copper pillars are correspondingly welded and fixed, so that the first antenna 410, the second antenna 420 and the signal ground 430 pass through the copper pillars and the gallium arsenide power amplifier chip and the arsenide power amplifier chip respectively. The gallium low-noise amplifier chips are electrically connected. As shown in Figure 6f, the adhesive material U8410 is filled between the redistribution layer 200 and the antenna structure layer 400. The adhesive material at least partially covers the metal support pillar 330, the second functional chip 310 and the third functional chip 320. The adhesive material, metal The support pillar 330, the second functional chip 310 and the third functional chip 320 together form the filling layer 300. As shown in Figure 6g, the protective glue 900 on the surface of the first functional chip 600 is removed. As shown in FIG. 6h , the outer surfaces of the substrate 100, the redistribution layer 200, the filling layer 300 and the antenna structure layer 400 that are stacked in sequence are coated with injection molding agent R4604 and then molded. It should be noted that the injection molding agent in this example can also be other organic non-conductive materials, which is not specifically required in this application. As shown in FIG. 6i , the injection molding agent R4604 is etched so that at least part of the injection molding agent R4604 exposes the substrate pad 700 . As shown in Figure 6j, the substrate pad 700 is electroplated until it is flush with the surface of the injection molding agent R4604. As shown in FIG. 6k , a number of BGA metal solder balls 800 are planted on the side of the substrate pad 700 away from the substrate 100 . The diameter of the BGA metal solder balls 800 is 0.35 mm.

In some embodiments, as shown in Figure 7 and Figures 7a to 7k, step S101 specifically includes the following steps:

Step S1011: Provide wafer 001, and form several blind holes on the front side of wafer 001.

Step S1012: As shown in Figure 7a, fill the blind hole with conductive material.

Step S1013: As shown in Figures 7b to 7h, a rewiring layer 200 is formed on the front side of the wafer 001. The rewiring layer 200 includes at least one metal wiring layer 210 and a dielectric layer 220 wrapping the metal wiring layer 210.

Step S1014: As shown in FIG. 7i, form a plurality of redistribution layer micro pads 201 on the side of the redistribution layer 200 away from the wafer 001.

Step S1015: As shown in FIG. 7j, the back surface of the wafer 001 is thinned so that the conductive material in the blind hole is exposed to form interconnection vias 110 on the back surface of the wafer 001, thereby obtaining the substrate 100.

Step S1016: As shown in FIG. 7k, a plurality of substrate pads 700 are formed on the back side of the substrate 100, and the substrate pads 700 are electrically connected to the redistribution layer 200 through the interconnection vias 110.

In this embodiment, through silicon via technology and rewiring technology are used to manufacture the transmission path of the antenna circuit, which can reduce the transmission power consumption of the antenna circuit, shorten the transmission path of high-frequency signals, reduce losses, and thereby improve the performance of the packaged chip.

In an example, as shown in Figures 7b to 7h, step S1013 specifically includes the following steps:

First, as shown in Figure 7b, the first metal wiring layer 211 is made using the Damascus process, and then the first silicon dioxide layer is deposited. As shown in Figure 7c, the first silicon dioxide layer is etched, and the through hole formed by etching corresponds to the blind hole in step S1011. As shown in Figure 7d, Ni/Cu is deposited in the through hole formed by etching the first silicon dioxide layer, and is polished using a chemical mechanical polishing (CMP) process. As shown in Figure 7e, the second metal wiring layer 212 is deposited using the Damascus process and polished using the chemical mechanical polishing (CMP) process. As shown in Figure 7f, a second silicon dioxide layer is deposited. As shown in FIG. 7g , the second silicon dioxide layer is etched, and the etched through holes correspond to the first metal wiring layer 210 . As shown in Figure 7h, Ni/Cu is deposited in the through hole formed by etching the second silicon dioxide layer, and is polished using a chemical mechanical polishing (CMP) process.

It should be noted that in step S1014, the third metal wiring layer 213 is formed while forming a plurality of rewiring layer micro pads 201 on the side of the rewiring layer 200 away from the wafer 001.

In some embodiments, as shown in Figure 1 and Figure 3 to Figure 5 and Figure 8, step S105 includes the following steps:

Step S1051: Provide an organic substrate.

Step S1052: Form a first metal layer on the front side of the organic substrate. The first metal layer includes the first antenna 410 and the second antenna 420.

Step S1053: Form a plurality of metal vias 440 at the ports of the first antenna 410 and the second antenna 420 respectively.

Step S1054: Form a second metal layer on the back side of the organic substrate, and form several metal pads 450 on the second metal layer. The side of the metal pads 450 away from the back side of the organic substrate is in contact with the metal via hole 440 on the organic substrate. Correspondingly, the side of the metal pad 450 close to the back side of the organic substrate is connected correspondingly to the position of the metal support pillar 330 on the filling layer 300 .

In this embodiment, the antenna is prepared on the organic substrate, which avoids the need for additional antenna design when the chip is used, thereby reducing the difficulty of using the chip. At the same time, the antenna is prepared on the organic substrate, so that the antenna can be connected with the first functional chip 600 and the first functional chip 600. A vertical signal transmission path is established between the second function chip 310 and the third function chip 320 to further shorten the transmission path of high-frequency signals and improve the performance of the chip integrated antenna packaging structure.

In an example, as shown in Figures 3 to 5, the organic substrate is made of RO3003 with a thickness of 0.1mm. The length and width of the organic substrate are 16mm × 11mm. A first metal layer is made on the front side of the organic substrate. The thickness of the layer is 9 μm. The first metal layer is provided with a first antenna 410 and a second antenna 420. The first antenna 410 and the second antenna 420 are both gold-plated copper and are used for transmitting and receiving signals. The first antenna 410 includes a first feeder line. The second antenna 420 includes four first radiating units 412 connected by 411 and distributed along a straight line. The second antenna 420 includes four second radiating units 422 connected by a second feeder line 421 and distributed along a straight line. Each radiating unit is in the shape of a square with cut corners. , the side length of the square with the cut corners is 1.9mm, and the side length of the cut corners is 0.3mm. A second metal layer is formed on the back side of the organic substrate as a signal ground 430 . Eight metal through holes are respectively formed at positions corresponding to the ports of the first antenna 410 and the second antenna 420. The eight metal through holes are evenly spaced in a circle with a circle diameter of 0.8 mm. A metal pad 450 is formed on the second metal layer. The side of the metal pad 450 away from the back of the organic substrate is connected correspondingly to the metal through hole on the organic substrate. The side of the metal pad 450 close to the back of the organic substrate is connected to the filling. The positions of the metal support pillars 330 on the layer 300 are connected accordingly.

The above-mentioned embodiments of the present application can complement each other without conflict.

Those skilled in the art can understand that the steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, the steps, measures, and solutions in the various operations, methods, and processes disclosed in this application in related technologies can also be alternated, changed, rearranged, decomposed, combined, or deleted.

In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", The orientations or positional relationships indicated by "top", "bottom", "inner", "outside", etc. are based on the orientations or positional relationships shown in the drawings. They are only for the convenience of describing the present application and simplifying the description, and are not indicated or implied. The devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as limiting the application.

The terms “first” and “second” are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, "plurality" means two or more.

In the description of this application, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood on a case-by-case basis.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above are only some of the embodiments of the present application. It should be pointed out that those of ordinary skill in the art can also make several improvements and modifications without departing from the principles of the present application. These improvements and modifications should also be regarded as This is the protection scope of this application.

Claims (10)

1. A chip integrated antenna packaging structure, characterized by including: The substrate includes an opposite first side and a second side, and the first side of the substrate is connected to the first functional chip and the substrate pad; A rewiring layer is located on the second surface of the substrate, and the rewiring layer is electrically connected to the first functional chip and the substrate pad through the substrate; A filling layer is located on the side of the rewiring layer away from the substrate. The filling layer is provided with a second functional chip and a third functional chip on the side close to the substrate. The second functional chip passes through the The rewiring layer and the substrate are electrically connected to the first functional chip and the substrate pad respectively. The third functional chip passes through the rewiring layer and the substrate in sequence and is connected to the first functional chip and the substrate pad respectively. The substrate pad is electrically connected, and the first functional chip is electrically connected through the rewiring layer, the substrate, and the substrate pad; An antenna structure layer is located on the side of the filling layer away from the redistribution layer. The antenna structure layer includes a first antenna, a second antenna and a signal ground. The first antenna and the second antenna are respectively used for For signal transmission and reception, the first antenna is electrically connected to the second functional chip, the second antenna is electrically connected to the third functional chip, and the signal ground is connected to the first antenna and the third functional chip respectively. The second antenna is electrically connected; Encapsulation material, covering the outside of the substrate, the rewiring layer, the filling layer and the antenna structure layer that are stacked in sequence, at least part of the encapsulation material exposes the substrate pad, the The substrate pads are used to lead out electrical connections. 2. The chip integrated antenna packaging structure according to claim 1, wherein the substrate has an interconnection through hole connecting the first surface and the second surface, and the interconnection through hole connects the first surface and the second surface. One end close to the first surface is connected to the substrate pad and the first functional chip, and one end close to the second surface of the interconnection via is connected to the second functional chip through the rewiring layer , the third function chip is electrically connected. 3. The chip integrated antenna packaging structure according to claim 1, wherein the rewiring layer includes at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer. 4. The chip integrated antenna packaging structure according to claim 1, wherein the first functional chip includes a frequency synthesizer chip, the second functional chip includes a power amplifier chip, and the third functional chip includes a low frequency synthesizer chip. Noise amplifier chip. 5. The chip integrated antenna packaging structure according to claim 1, wherein the filling layer is provided with at least four metal support pillars, and the metal support pillars include a first metal support pillar, a second metal support pillar, A third metal support column and a fourth metal support column, one end of the first metal support column is connected to the first antenna, and the other end is electrically connected to the second functional chip; one end of the second metal support column It is connected to the signal ground, and the other end is electrically connected to the second functional chip; one end of the third metal support pillar is connected to the signal ground, and the other end is electrically connected to the third functional chip. One end of the four metal support pillars is connected to the second antenna, and the other end is electrically connected to the third functional chip. 6. The chip integrated antenna packaging structure according to claim 1, wherein the antenna structure layer includes a signal ground, a dielectric layer and an antenna stacked sequentially in the direction in which the filling layer points to the antenna structure layer, The antenna includes a first antenna and a second antenna. The first antenna includes a plurality of first radiating units distributed along a straight line connected by a first feed line. The second antenna includes a second antenna connected by a second feed line. Several second radiating units distributed along a straight line are connected by wires. 7. A packaging method for a chip integrated antenna packaging structure, which is characterized by including: Forming a sequentially stacked substrate and a rewiring layer, the substrate includes an opposite first side and a second side, the rewiring layer is located on the second side of the substrate, and a plurality of rewiring layers are formed on the first side of the substrate. The substrate pad is used to lead out the electricity; Fixedly connecting a first functional chip to the first surface of the substrate and coating the surface of the first functional chip with protective glue; A second functional chip and a third functional chip are formed on the side of the rewiring layer away from the substrate. The second functional chip and the third functional chip pass through the rewiring layer, the substrate and the substrate in sequence respectively. The first functional chip is electrically connected; At least four metal support pillars are formed on a side of the redistribution layer away from the substrate. The size of the metal support pillars in the direction from the first surface to the second surface of the substrate is larger than that of the second functional chip. , the size of the third functional chip in the direction from the first surface of the substrate to the second surface; the metal support pillar includes a first metal support pillar, a second metal support pillar, a third metal support pillar and a third metal support pillar. Four metal support pillars, the first metal support pillar and the second metal support pillar are electrically connected to the second functional chip respectively, the third metal support pillar and the fourth metal support pillar are respectively connected to the The third function chip is electrically connected; An antenna structure layer is formed on the side of the metal support pillar away from the redistribution layer. The antenna structure layer includes a first antenna, a second antenna and a signal ground. The first antenna passes through the first metal support pillar. The second antenna is electrically connected to the third functional chip through the fourth metal support pillar, and the signal ground is electrically connected to the second functional chip through the second metal support pillar. The functional chip is electrically connected, and the signal ground is electrically connected to the third functional chip through the third metal support pillar; Glue material is filled between the rewiring layer and the antenna structure layer, and the glue material at least partially covers the metal support pillar, the second functional chip and the third functional chip, and the glue material , the metal support pillar, the second functional chip and the third functional chip jointly form a filling layer; Remove the protective glue on the surface of the first functional chip; Encapsulating material is coated on the outside of the substrate, the rewiring layer, the filling layer and the antenna structure layer that are stacked in sequence; Etching the packaging material to expose at least a partial area of the packaging material to expose the substrate pad and electroplating the substrate pad to be flush with the surface of the packaging material; A metal solder ball is formed on a side of the substrate pad away from the substrate. 8. The packaging method of a chip integrated antenna packaging structure according to claim 7, characterized in that, forming a sequentially stacked substrate and a rewiring layer, the substrate including an opposite first surface and a second surface, the The rewiring layer is located on the second side of the substrate, and a plurality of substrate pads are formed on the first side of the substrate for electrical extraction, including: A wafer is provided, and a plurality of blind vias are formed on the front side of the wafer; Fill the blind hole with conductive material; A rewiring layer is formed on the front side of the wafer, the rewiring layer includes at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer; Form a plurality of redistribution layer micro pads on the side of the redistribution layer away from the wafer; Perform a thinning process on the back of the wafer to expose the conductive material in the blind hole to form interconnection vias on the back of the wafer to obtain the substrate; A plurality of the substrate pads are formed on the back side of the substrate, and the substrate pads are electrically connected to the rewiring layer through the interconnection via holes. 9. The packaging method of a chip integrated antenna packaging structure according to claim 7, wherein an antenna structure layer is formed on the side of the metal support pillar away from the rewiring layer, and the antenna structure layer includes A first antenna, a second antenna and a signal ground. The first antenna is electrically connected to the second functional chip through the first metal support pillar. The second antenna is electrically connected to the second functional chip through the fourth metal support pillar. The third functional chip is electrically connected. The signal ground is electrically connected to the second functional chip through the second metal support pillar. The signal ground is electrically connected to the third functional chip through the third metal support pillar. Specifically include: Provide organic substrates; A first metal layer is formed on the front side of the organic substrate, and the first metal layer includes a first antenna and a second antenna; Several metal vias are formed at the ports of the first antenna and the second antenna respectively; A second metal layer is formed on the back side of the organic substrate, and several metal pads are formed on the second metal layer. The side of the metal pads away from the back side of the organic substrate is in contact with the side on the organic substrate. The metal via holes are connected correspondingly, and the side of the metal pad close to the back side of the organic substrate is connected correspondingly to the position of the metal support pillar on the filling layer. 10. The packaging method of a chip integrated antenna packaging structure according to claim 9, wherein a first metal layer is formed on the front side of the organic substrate, and the first metal layer includes a first antenna and a second Antenna, specifically including: A group of several first radiating units distributed along a straight line and connected by a first feed line are formed on the front side of the organic substrate, and a group of a plurality of second radiating units distributed along a straight line and connected by a second feeding line are formed on the front side of the organic substrate.