CN116917991A

CN116917991A - Memory chip and control method thereof

Info

Publication number: CN116917991A
Application number: CN202180091677.9A
Authority: CN
Inventors: 焦慧芳; 周国名; 应成伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-20
Filing date: 2021-05-20
Publication date: 2023-10-20
Also published as: WO2022241731A1

Abstract

A memory chip, a circuit assembly, an electronic device, and a method for controlling the memory chip are provided. The memory chip (220-11) includes a reset pin (204), a plurality of command address pins (202), a memory cell (240), and a mode setting circuit (230). When the reset pin (204) receives a low level, a reset mode is entered. The mode setting circuit (230) generates a mode setting signal for setting the memory chip (220-11) to a standard mode or a mirror mode according to the level pattern received by the plurality of command address pins (202) in the reset mode, and causes the memory chip (220-11) to operate in the set mode at the end of the reset. By setting the operation mode using the level pattern received by the plurality of command address pins (202) during reset and causing the memory chip (220-11) to operate in the set mode after the end of reset, mirrored pins that would otherwise set and maintain the operation mode during the normal operation mode can be saved. Thus, the pin count of the memory chip (220-11) may be reduced to make the memory smaller or left as it is to enhance the performance of the memory chip (220-11).

Description

Memory chip and control method thereof

Technical Field

The present disclosure relates to the field of integrated circuits, and more particularly, to memory chips and control methods thereof.

Background

In electronic devices such as computers, there is typically one or more memories to store data and/or commands. Among the many types of memory, volatile (volatile) memory is widely used for its fast performance. Volatile memory can be further divided into two broad categories, static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). The cost, integration level, power consumption and the like of the DRAM are obviously superior to those of the SRAM. One type of DRAM that is widely used is Double Data Rate (DDR) memory.

The JEDEC institute responsible for the computer memory technology standard formally promulgates the latest fifth generation DDR standard, which will increase the actual bandwidth by 36% compared to the fourth generation standard, month 7 in 2020. However, the fifth generation DDR memory is still not ideal in terms of size and/or performance.

Disclosure of Invention

In view of the foregoing, embodiments of the present disclosure are directed to a memory, a circuit assembly, an electronic device, and a method for controlling a memory for reducing the number of pins.

According to a first aspect of the present disclosure, a memory chip is provided. The memory chip includes a first pin, one or more second pins, a memory cell, and a mode setting circuit. The mode setting circuit is configured to generate a mode setting signal for setting an operation mode of the memory chip based on the level pattern on the one or more second pins during a period in which the level on the first pin is the first level; and in response to the level on the first pin transitioning from the first level to the second level, the memory chip operates in a mode set by the mode setting signal. By setting the operation mode using the level pattern received by the plurality of second pins during the first level and causing the memory chip to operate in the set mode after the end of the first level, a third pin that would otherwise set and maintain the operation mode during the normal operation mode can be saved. Therefore, the pin count of the memory chip can be reduced to make the memory chip smaller, or the third pin is left as it is to enhance the performance of the memory chip.

In one possible implementation, the memory chip is a DDR memory chip, the first pin is a reset pin, and the one or more second pins are command/address (CA) pins. By setting the operation mode of the memory chip, for example, the standard mode or the mirror mode, using the level pattern or the combination of level patterns on one or more CA pins during the reset period in which the level on the reset pin is low, the Mirror (MIR) pin dedicated to setting the mirror mode or the standard mode of the memory chip can be avoided, so that the number of pins of the DDR memory chip can be reduced. In other implementations, where the MIR pin is not omitted and is not used to set the mode of operation of the DDR memory chip, the MIR pin may also be used for other purposes, thereby enhancing performance of the DDR memory chip.

In one possible implementation, the memory chip is configured to obtain command or address signals through the one or more second pins after the level on the first pin transitions to the second level. By using the second pins to acquire command and address signals after termination, the second pins can be multiplexed at different stages to reduce the number of pins.

In one possible implementation, the modes of operation include a mirror mode and a standard mode; and a mode setting signal for setting an operation mode of the memory chip to a mirror mode or a standard mode. By setting the mirror mode or the standard mode using different level patterns, the mirror mode or the standard mode of the memory chip can be set in a simplified scheme.

In one possible implementation, the one or more second pins include a first command address pin and a second command address pin. The mode setting circuit is further configured to set the operation mode of the memory chip to a mirror mode if the level of the first command address pin is a low level and the level of the second command address pin is a high level during the level on the first pin is the first level; and setting an operation mode of the memory chip to a standard mode if the level of the first command address pin is a high level and the level of the second command address pin is a low level during the level on the first pin is the first level. By setting the operation mode using the level pattern received by the plurality of command address pins during reset and operating in the set mode after the end of reset, mirror pins that would otherwise set and maintain the operation mode during the normal operation mode can be saved. Therefore, the pin count of the memory chip can be reduced to make the memory chip smaller or left as it is to enhance the performance of the memory chip. In addition, since the operation mode is set using a combination of the level patterns of the plurality of second pins, the setting of the operation mode can be made more accurate, safe, and reliable.

In one possible implementation, the mode setting circuit includes a arbiter and a latch. A determiner configured to generate a determination signal based on a first level on the first pin and a level pattern on the one or more second pins; and a latch configured to generate a mode setting signal based on the decision signal during a period when the level on the first pin is the first level and to transition from the first level to the second level in response to the level on the first pin, the memory chip operating in a mode set by the mode setting signal. By using the arbiter, the operating mode set level that would otherwise be provided by the third pin may be changed to be provided by the arbiter within the memory chip, thereby reducing the use of the third pin or using it for other purposes. By using a latch, the level on the second pin can be decoupled from the mode setting after the first level is over, thereby avoiding that the level on the second pin has an effect on the operation mode during normal operation.

In one possible implementation, the arbiter comprises a first decision circuit, a second decision circuit and a logic gate. A first decision circuit configured to generate a first decision output based on the level pattern on the one or more second pins. A second decision circuit configured to generate a second decision output based on the level pattern on the one or more second pins. Logic circuitry coupled to the first and second decision circuits and configured to generate a decision signal based on the first or second decision outputs during the first level by implementing the decision device as a first decision circuit, a second decision circuit, and a logic gate, the size of the decision device being less affected than DDR particles. For example, for a 25 nm process node, the size of the mode setting circuit including the arbiter and latch may be below 10 square microns, while the DDR chip grain size of, for example, 4Gb is tens of square millimeters.

In one possible implementation, the first decision circuit includes a first P-type field effect transistor, a second P-type field effect transistor, a first N-type field effect transistor, and a second N-type field effect transistor connected in series between a power supply level and ground. The gates of the second P-type field effect transistor and the first N-type field effect transistor are grounded, the gate of the first P-type field effect transistor is coupled to one second pin of the one or more second pins, and the gate of the second N-type field effect transistor is coupled to another second pin of the one or more second pins. By using the first decision circuit thus set, delays in generation and transmission of the decision signal are small, and thus the operation mode of the memory chip can be set accurately and timely.

In one possible implementation, the second decision circuit includes a third P-type field effect transistor, a fourth P-type field effect transistor, a third N-type field effect transistor, and a fourth N-type field effect transistor connected in series between the power supply level and ground. The gates of the fourth and third N-type field effect transistors are coupled to the power supply level, the gate of the third P-type field effect transistor is coupled to another second pin of the one or more second pins, and the gate of the fourth N-type field effect transistor is coupled to a second pin of the one or more second pins. By using the second decision circuit thus set, delays in generation and transmission of the decision signal are small, and thus the operation mode of the memory chip can be set accurately and timely.

In one possible implementation, the mode setting circuit is further configured to generate a first mode control signal for setting the operation mode of the memory chip to the mirror mode if the level of one of the one or more second pins is a third level during the level on the first pin being the first level; and generating a second mode control signal for setting an operation mode of the memory chip to a standard mode if a level of one of the one or more second pins is a fourth level different from the third level during the level on the first pin is the first level. By setting the operation mode of the memory chip using the level pattern on the single second pin, this can further simplify the mode setting circuit and further reduce the occupied area and cost, compared to the combination of the level patterns on the plurality of second pins.

In one possible implementation, the mode setting circuit is further configured to disconnect electrical connection with the one or more second pins in response to the level on the first pin transitioning from the first level to the second level. . By using a switch to disconnect the electrical connection when exiting, for example, a reset mode, it can be ensured that the subsequent level on the second pin does not interfere with the set mode.

According to a second aspect of the present disclosure, a circuit assembly is provided. The circuit assembly comprises a circuit board and a memory chip according to the first aspect. The memory chip is mounted on a circuit board. By using the circuit assembly, it is possible to set the operation mode of the memory chip in the circuit assembly using the level pattern received by the plurality of second pins during the first level and the memory chip operates in the mode set by the mode setting signal after the first level ends. In this way, the third pin that would otherwise set and maintain the operating mode during the normal operating mode can be saved. Therefore, the pin count of the memory chip can be reduced to make the memory chip smaller, or the third pin is left as it is to enhance the performance of the memory chip.

According to a third aspect of the present disclosure, an electronic device is provided. The electronic device comprises a processor and a circuit assembly according to the second aspect. By using the electronic device, it is possible to set the operation mode of the memory chip in the electronic device using the level pattern received by the plurality of second pins during the first level and the memory chip follows the mode set by the mode setting signal after the first level ends. In this way, the third pin that would otherwise set and maintain the operating mode during the normal operating mode can be saved. Therefore, the pin count of the memory chip can be reduced to make the memory chip smaller, or the third pin is left as it is to enhance the performance of the memory chip.

According to a fourth aspect of the present disclosure, a method for controlling a memory chip is provided. The method includes receiving a level via a first pin of a memory chip; generating a mode setting signal for setting an operation mode of the memory chip based on the level pattern on one or more second pins of the memory chip during the level on the first pin being the first level; and in response to the level on the first pin transitioning from the first level to the second level, the memory chip operates in a mode set by the mode setting signal. By setting the operation mode using the level pattern received by the plurality of second pins during the first level and maintaining the set mode after the end of the first level, a third pin that would otherwise set and maintain the operation mode during the normal operation mode can be saved. Therefore, the pin count of the memory chip can be reduced to make the memory chip smaller, or the third pin is left as it is to enhance the performance of the memory chip.

In one possible implementation, the method further includes the memory chip retrieving command or address signals through one or more second pins after the level on the first pin transitions from the first level to the second level. By using the second pins to acquire command and address signals after termination, the second pins can be multiplexed at different stages to reduce the number of pins.

In one possible implementation, the first pin comprises a reset pin and the first level comprises a set low level. By setting the operation mode using the level pattern received by the one or more second pins during reset and causing the memory chip to operate in the mode set by the mode setting signal after the reset is ended, the mirror pins that would otherwise set and maintain the operation mode during the normal operation mode can be saved. Therefore, the pin count of the memory chip can be reduced to make the memory chip smaller or left as it is to enhance the performance of the memory chip.

In one possible implementation, the one or more second pins include a first command address pin and a second command address pin. Generating a mode setting signal for setting an operation mode of the memory chip includes generating a first mode setting signal for setting the operation mode of the memory chip to a mirror mode if a level of the first command address pin is a low level and a level of the second command address pin is a high level during the level on the first pin is the first level; and generating a second mode setting signal for setting an operation mode of the memory chip to a standard mode if the level of the first command address pin is a high level and the level of the second command address pin is a low level during the level on the first pin is the first level. By setting the operation mode using the level pattern received by the plurality of command address pins during reset and causing the memory chip to operate in the mode set by the mode setting signal after the end of reset, the mirror pins that would otherwise set and maintain the operation mode during the normal operation mode can be saved. Therefore, the pin count of the memory chip can be reduced to make the memory chip smaller or left as it is to enhance the performance of the memory chip. In addition, since the operation mode is set using a combination of the level patterns of the plurality of second pins, the setting of the operation mode can be made more accurate, safe, and reliable.

In one possible implementation, generating the mode setting signal for setting the operation mode of the memory chip includes generating a first mode setting signal for setting the operation mode of the memory chip to a mirror mode if the level of one of the one or more second pins is a third level during the level on the first pin is the first level; and generating a second mode setting signal for setting an operation mode of the memory chip to a standard mode if a level of one of the one or more second pins is a fourth level different from the third level during the level on the first pin is the first level. By setting the operation mode of the memory chip using the level pattern on the single second pin, this can further simplify the mode setting circuit and further reduce the occupied area and cost, compared to the combination of the level patterns on the plurality of second pins.

In one possible implementation, causing the memory chip to operate in a mode set by the mode setting signal includes: in response to the level on the first pin transitioning from the first level to the second level, the mode setting circuit in the memory chip is disconnected from the electrical connection with the one or more second pins. By using a switch to disconnect the electrical connection when exiting, for example, a reset mode, it can be ensured that the subsequent level on the second pin does not interfere with the set mode.

According to a fifth aspect of the present disclosure, a package structure is provided. The package structure includes the memory chip according to the first aspect and a package case. The package housing encapsulates the memory chip.

According to a sixth aspect of the present disclosure, a memory chip is provided. The memory chip includes a first pin, one or more second pins, a memory cell, and a mode setting circuit. The mode setting circuit is configured to generate a mode setting signal for setting an operation mode of the memory chip based on the level pattern on the one or more second pins during a period in which the level on the first pin is the first level; and the memory chip is configured to acquire command or address signals through the one or more second pins after the level on the first pin transitions to the second level. By setting the operation mode using the level pattern received by the plurality of second pins during the first level and causing the memory chip to operate in the set mode after the end of the first level, a third pin that would otherwise set and maintain the operation mode during the normal operation mode can be saved. Therefore, the pin count of the memory chip can be reduced to make the memory chip smaller, or the third pin is left as it is to enhance the performance of the memory chip.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

FIG. 1 shows a schematic diagram of an electronic device according to one embodiment of the present disclosure;

FIG. 2 illustrates a schematic diagram of a memory according to one embodiment of the present disclosure;

FIG. 3 illustrates a timing diagram of signal timing of a memory chip according to one embodiment of the present disclosure;

FIG. 4 illustrates a partial schematic block diagram of a memory chip according to one embodiment of the present disclosure;

FIG. 5 shows a schematic block diagram of a mode setting circuit of a memory chip according to one embodiment of the present disclosure;

FIG. 6 shows a circuit schematic of a arbiter according to one embodiment of the disclosure;

fig. 7 shows a circuit schematic of a arbiter according to another embodiment of the disclosure; and

Fig. 8 illustrates a flowchart of a mode control method of a memory chip according to one embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. The term "and/or" means at least one of the two items associated therewith. For example, "a and/or B" means A, B, or a and B. Other explicit and implicit definitions are also possible below.

In the following description of the specific embodiments, some repetition is not described in detail, but it should be understood that the specific embodiments have mutual references and may be combined with each other.

The fifth generation DDR standard uses a supply voltage that drops to 1.1V, with an allowable fluctuation range of 3% (i.e., ±0.033V). Compared with the fourth generation DDR standard, the method has lower power consumption. In addition, the fifth generation DDR standard uses an improved CA pin and a mirror pin is newly introduced. The command signal is multiplexed with the address signal on the CA pin, and the operation mode of the memory chip is set to a standard mode (standard mode) or a mirror mode (mirror mode) by providing a fixed level to the MIR pin. For standard mode and mirror mode, reference may be made to the fifth generation DDR SDRAM standard JESD79-5 published by the Joint electronic device engineering Commission (joint electron device engineering council, JEDEC), which is incorporated herein by reference in its entirety. To meet the above changing needs, the fifth generation DDR standard has a large change in pins relative to the fourth generation DDR standard. For example, to obtain greater bandwidth, a pin strategy of command address signal multiplexing is employed. In order to meet the requirements of system stability under low voltage, high frequency operating conditions, the fifth generation DDR standard adds more ground signals to meet the requirements of the shortest current return path.

To meet the increased demands for functionality and performance, the data and control signals required for DDR memory chips require more pins to transmit. However, the increased number of pins is against the trend of miniaturization of electronic products. The fifth generation DDR standard still does the same number of external pins as the fourth generation DDR standard with the addition of some of the necessary pins. It is anticipated that the next generation standard DDR interface will continue to grow in transmission rate and the pin resources will be more stressed, so it is desirable to be able to reduce or at least maintain the number of existing pins while increasing transmission rate and functionality.

In embodiments of the present disclosure, control signals and/or data signals to be transmitted through different pins are time-multiplexed on some pins (i.e., level signals on these pins may perform a first function during a first period and a second function different from the first function during a second period different from the first period), the number of pins occupied by control signals and data signals may be reduced, and the saved pins may be used to transmit signals of other functions, thereby allowing the DDR memory chip more space for function setup flexibility. For example, the MIR pin in the fifth generation DDR standard may be omitted or left as a pin for enhancing the performance of the double data rate memory by a mode setting circuit provided inside the memory and setting the operation mode of the memory during, for example, a power-on reset of the memory chip through the CA pin. Therefore, the pin resources can be saved under the conditions that the original time sequence is not influenced, extra time delay is not introduced, and the load of the system is not increased.

Fig. 1 shows a schematic diagram of an electronic device 100 according to one embodiment of the present disclosure. In one embodiment, electronic device 100 may be a computer, server, or other existing electronic device having memory, such as DDR memory, or a future-occurring electronic device. Included within the electronic device 100 are one or more circuit components, such as a processor, motherboard, graphics card, power supply, and the like, that are not shown in fig. 1. One or more circuit components may include one or more electronic components and are joined or assembled with one another to form another component. For example, a processor, DDR memory, or graphics card, etc. may be mounted on the motherboard to form a mounted motherboard assembly. The DDR memory may be a DDR memory conforming to the current fifth generation DDR standard or future DDR standard. Although DDR memory is illustrated as an example in the present disclosure, embodiments of the present disclosure are not limited to DDR memory. For example, some embodiments of the present disclosure may also be applicable to Quad Data Rate (QDR) memory.

Fig. 2 shows a schematic diagram of a memory 200 according to one embodiment of the present disclosure. In one embodiment, memory 200 is, for example, a DDR memory. The memory 200 is exemplified as an on-board memory plugged into a connector slot on a printed circuit board, however, the present disclosure is not limited thereto. In this embodiment, the memory 200 includes a plurality of memory chips 220-11, 220-12 … 220-1N and 220-21,220-22 … 220-2N in chip form, where N represents a positive integer and the memory is collectively represented by reference numeral 220. Although the memory chip 220 is shown in fig. 2 in the form of an on-board memory chip, this is merely illustrative and not limiting of the scope of the present disclosure. The memory chip 220 may also be part of other types of devices or chips with memory functions. For example, in a system on chip (SoC), the memory 200 may be part of the SoC chip. The SoC chip may include a processor, interface circuits, and the like in addition to the memory 200. The memory chip may be a memory chip having a single die structure, or may be a package obtained by stacking a plurality of dies or memory chips and packaging them together, or a part thereof, such as a system in package (system in package, siP) chip. Each memory chip includes a plurality of pins for passing electrical signals such as addresses, data, and/or commands. The pins of the memory may be chip interfaces on the memory chip or chip package, represented by connection interfaces such as wires, interconnect lines, pads, bumps (bumps), or solder balls.

The memory chip of DDR memory 200, such as memory chip 220-11, has a RESET pin for transmitting a RESET (RESET_n) signal when, for example, powered up. The memory chip also has, for example, multiple CA pins for transmitting commands and/or addresses during normal operation. One CA pin can be used for both transmitting commands and transmitting addresses in a time division multiplexed manner. But this introduces additional latency to the command or address. For example, on the first rising edge, the signal on the CA pin is sampled to resolve the command, and on the second rising edge, the signal on the CA pin is sampled again to resolve the address information.

On the other hand, the CA pin is not used during some time periods. For example, during the period when the RESET signal reset_n received by the RESET pin is low, the level on the CA pin is maintained between VSS and VDD and is not used to transfer meaningful data. In other words, the level of the CA pin of a conventional memory chip during reset does not result in any operation. In one embodiment of the present disclosure, the operation mode of the DDR memory may be set by receiving a specific level pattern using one or more CA pins during a period in which the RESET signal reset_n is low. In embodiments of the present disclosure, the level pattern may include levels or combinations of levels that one or more pins exhibit over a period of time, such as a single constant level on a single pin, multiple levels over time on a single pin, a combination of multiple respective constant levels on multiple pins that may be the same or different from each other, and a combination of multiple respective levels over time on multiple pins that may be the same or different from each other. Further, the operation mode of the memory chip means a mode in which the memory chip operates according to a predetermined specification or rule. For example, the mirror mode indicates a mode in which the CA pin of the memory chip can mirror-switch for data transmission, and the standard mode indicates a mode in which the mirror-switch is not performed on the CA pin.

In one embodiment, the DDR memory has two modes of operation, a mirror mode and a standard mode. In particular, the DDR memory chip separately provides one Mirror (MIR) pin to receive a set level and operates in a corresponding operation mode according to the received level. Specifically, when the MIR pin receives a high level VDDQ, the DDR memory chip enters mirror mode, and when the MIR pin receives a low level VSSQ, the DDR memory chip enters standard mode.

Fig. 3 illustrates a timing diagram of signal timing 300 of a memory chip according to one embodiment of the present disclosure. Ck_t and ck_c represent clock signals received by the DDR memory chip, VPP represents a DRAM activation power signal, VDD/VDDQ represents a power signal, reset_n represents a RESET signal, and CA<1>And CA<0>Respectively represent pins CA<1>Sum pin CA<0>And a level signal thereon. At T _A Reset_n is set low, and the DDR memory chip thereby enters the RESET phase. Pin CA<1>Sum pin CA<0>The levels on the memory chip exhibit a level pattern accordingly for setting the operation mode of the memory chip. With reset_n at T _B Pulled high, pin CA<1>Sum pin CA<0>The level above begins to characterize the command and/or address. Although pin CA is used herein <1>Sum pin CA<0>To describe, it is understood that other CA pins are similar and may be used to set the mode of operation or perform other operations.

In one embodiment of the present disclosure, the DDR memory chip may be set to either mirror mode or standard mode by applying a specific level pattern on one or more CA pins during RESET, i.e., RESET_N is low. Further, when reset_n is pulled high to end the RESET, the DDR memory chip may remain in the set mode and the CA pin is decoupled from the mode setup function so that the CA pin may perform the transfer of commands and/or addresses and the level on the CA pin does not change the set mode. Although described herein using the CA pin, other pins of the memory chip may also be used to set the operating mode of the DDR memory chip during reset as long as the level on that pin is not otherwise used to perform a particular function during reset or is not practical for the operation of the memory. In addition, the pins may also be time division multiplexed for setting other functions or operations of the DDR memory chip. Some specific example embodiments of the present disclosure are specifically described below in conjunction with fig. 4-7.

FIG. 4 illustrates a partial schematic block diagram of a memory chip 220-11 according to one embodiment of the present disclosure. In order not to affect the description of the present disclosure, only some portions related to the embodiments of the present disclosure are shown in fig. 4, and other portions are omitted here. It is understood that memory chip 220-11 may include many more components than those shown in FIG. 4. The memory chip 220-11 includes a first pin 204, one or more second pins 202, a mode setting circuit 210, a controller 230, and a memory unit 240. Alternatively, the controller 230 may be located outside the memory chip 220-11 and coupled with the memory chip 220-11 to control the operation of the memory chip 220-11. The one or more second pins 202 include a second pin 202-1 … … second pin 202-M, where M represents an integer greater than 0. In one embodiment, the first pin 204 is a reset pin. Alternatively, the first pin may be other pins than the reset pin, so long as the level on one or more of the second pins 202 may be used to set the mode of operation of the memory chip including the memory cells during the time that the pin is at a particular level and the level on one or more of the second pins 202 may be used to perform other functions than setting the mode of operation of the memory chip 220-11 during the time that the first pin is at other levels than the particular level. In one embodiment, the second pin 202 is a CA pin. Alternatively, other pins such as the DQ pin, DQS_c pin, and/or DQS_t pin as described above may also be used as the second pin.

When the mode setting circuit 210 receives a set low level transmitted via the first pin 204 indicating that the memory chip 220-11 enters a reset phase, the mode setting circuit 210 may generate a mode setting signal for setting an operation mode of the memory chip 220-11 based on the level pattern on the one or more second pins 202. In one embodiment, the mode of operation may be set based on a level pattern on one second pin (e.g., second pin 202-1). For example, if the level on the second pin 202-1 is low during the reset phase, the memory chip 220-11 enters a mirror mode. If the level on the second pin 202-1 is high and low during the reset phase, the memory chip 220-11 enters the normal mode. For another example, if the level on the second pin 202-1 changes from low to high during the reset phase, the memory chip 220-11 is set to mirror mode. If the level on the second pin 202-1 goes from high to low during the reset phase, the memory chip 220-11 is set to standard mode.

In other embodiments, the mode of operation may be set based on a combination of the level patterns on the plurality of second pins. For example, if the levels on the second pin 202-1 and the second pin 202-2 are low and high, respectively, during the reset phase, the memory chip 220-11 is set to mirror mode. If the levels on the second pin 202-1 and the second pin 202-2 are high and low, respectively, during the reset phase, the memory chip 220-11 is set to the standard mode. Other combinations and variations of the level patterns are possible, provided that each level pattern can correspond to a unique mode of operation.

When the mode setting circuit 210 receives a pulled-up level on the first pin 204 indicating the end of the reset phase, the mode setting circuit 210 causes the memory chip 220-11 to operate in accordance with the operating mode set by the mode setting signal, e.g., the mode setting circuit 210 continuously or periodically provides the mode setting signal to cause the memory chip 220-11 to operate in accordance with the operating mode set by the mode setting signal, or the mode setting circuit 210 stops providing the mode setting signal and the controller provides an alternate level signal by itself to cause the memory chip 220-11 to operate in accordance with the set operating mode in response to stopping receiving the mode setting signal. The present disclosure is not limited in the manner in which the memory chip 220-11 is caused to operate in the operating mode set by the mode setting signal by the mode setting circuit 210 after the pulled-up level on the first pin 204 that indicates the end of the reset phase. In one embodiment, the memory chip 220-11 further includes one or more switches S1, such as P-type metal oxide field effect (MOSFET) switches, coupled between the mode setting circuit 210 and the one or more second pins 202, wherein control terminals of the one or more switches S1 are coupled to the first pin 204. When the level on the first pin 204 is pulled high, the high level causes the one or more switches S1 to open to disconnect the mode setting circuit 210 from the electrical connection with the one or more second pins 202, so that the mode setting circuit 210 no longer generates a mode setting signal for setting the operating mode of the memory chip 220-11 further from the level input of the one or more second pins 202, and the memory chip 220-11 can thereby maintain the set operating mode. In other embodiments, one or more switches S1 may be located inside the mode setting circuit 210 and be part of the mode setting circuit 210. Other ways of maintaining the mode of operation are possible, for example as shown in fig. 5 and 6. Alternatively, an N-type MOSFET may be used as the switch S1. In this case, an inverter may be coupled to the gate of the N-type MOSFET to invert the relatively low reset signal, and the inverted high signal may turn on the N-type MOSFET so that the level pattern on the one or more second pins 202 may be used to set the mode of operation of the memory chip.

In another embodiment, the mode setting circuit 210 may also generate a mode setting signal for setting the operation mode of the memory chip 220-11 based on the level pattern on the one or more second pins 202 when the first pin 204 transmits a high level. For example, the first pin 204 is coupled to an inverter that outputs a low level after receiving a high level input on the first pin 204. The low level may be the same as the operation when the first pin 204 is set low into the reset mode, and will not be described again. Correspondingly, when the level of the first pin 204 is adjusted to a low level, the inverter outputs a high level, ending the reset phase, and the mode setting circuit 210 no longer generates a mode setting signal for setting the operating mode of the memory chip 220-11 further from the level input of the one or more second pins 202.

Fig. 5 shows a schematic block diagram of a mode setting circuit 211 of a memory chip according to one embodiment of the present disclosure. In one embodiment, mode setting circuit 211 is one implementation of mode setting circuit 210 of fig. 4, where mode setting circuit 211 includes a arbiter 212 and a latch 214. The arbiter 212 is configured to generate a decision signal based on the first level on the first pin 204 and the level pattern on the one or more second pins 202 and the latch 214 latches the decision signal to provide a mode setting signal for setting the operation mode of the memory chip. A memory chip controller, located in the memory chip, coupled to the latch 214 may set the mode of operation of the memory chip based on the mode setting signal. Alternatively, the mode setting signal may also be received by a controller external to the memory chip that is electrically coupled to the mode setting circuit 211 to set the operating mode of the memory chip. In one embodiment, the first level on the first pin 204 is, for example, a low level on the reset pin, and the level pattern on the one or more second pins 202 is, for example, the level pattern on the 202-1 and 202-2 pins in the second pins 202-1, 202-2 … … 202-N in FIG. 3. In one embodiment, the second pin 202-1 may be a CA <0> pin of a plurality of CA pins in the DDR memory chip, and the second pin 202-2 may be a CA <1> pin of a plurality of CA pins. The other CA pins are not used during reset or are used to set other functions than setting the mode of operation of the memory chip.

In one embodiment, if the levels on the CA <0> and CA <1> pins are low and high, respectively, then the arbiter 212 generates a first decision signal based on the low and high levels and the signal from the reset pin that is set low, and the latch 214 generates a first mode set signal for setting the operating mode of the memory chip to the standard mode based on the first decision signal and the signal from the reset pin that is set low, and if the levels on the CA <0> and CA <1> pins are high and low, respectively, then the arbiter 212 generates a second decision signal based on the high and low levels and the signal from the reset pin that is set low, and the latch 214 generates a second mode set signal for setting the operating mode of the memory chip to the mirror mode based on the second decision signal and the signal from the reset pin that is set low. After the level on the first pin is pulled high, latch 214 outputs or asserts the previously (i.e., during reset) output mode setting signal regardless of the output level pattern of decision 212. The mode set latch 214 causes the memory chip to operate in the currently set mode of operation because the controller receives the maintained mode set signal. If the operating mode of the memory chip needs to be changed, it is necessary to wait for the next arrival of the first level (e.g., reset signal). Thus, the memory chip can operate in a stable operation mode. By using a scheme of a level pattern of multiple pins, accuracy, safety, and reliability of pin time division multiplexing can be ensured. Alternatively, other CA pins may also be used as the second pin to transmit a level pattern for setting the operation mode of the memory chip.

In another embodiment, the standard mode may be set by a level pattern on only a single CA pin. For example, if the level on the CA <1> pin is a high level during reset, the mode setting circuit 211 generates a first mode setting signal for setting the operation mode of the memory chip to the standard mode based on the set low level and the high level on the reset pin, and if the level on the CA <1> pin is a low level during reset, the mode setting circuit 211 generates a second mode setting signal for setting the operation mode of the memory chip to the mirror mode based on the set low level and the low level on the reset pin. At this time, the unselected CA pins, such as other CA pins than CA <1>, are not involved in setting the operation mode of the memory chip, or may be used for other functions, which the present disclosure does not limit. It will be appreciated that any other CA pin may also be selected as an alternative pin to CA <1> to set the mode of operation of the memory chip during reset. This arrangement uses fewer circuit devices, such as fewer transistors, than using a level pattern on multiple pins, which may correspondingly reduce the footprint of the arbiter 212 on the DDR memory chip.

While the level of the second pin is shown as being electrically separated from the mode setting at the end of the first level by latch 214, it is understood that this is by way of illustration only and is not limiting as to the scope of the present disclosure. The level of the second pin may also be electrically separated from the mode setting using switch S1 as described above. For example, in one embodiment, a controller for setting an operating mode of a memory chip has a state memory circuit that generates a response output in real time for setting the operating mode of the memory chip upon receipt of an input signal, and that can maintain a previous corresponding output upon receipt of no input signal. When the level on the first pin is high, the switch S1 in fig. 4 is turned on, the memory mode setting circuit 210 receives the level pattern on the second pin 202 via the switch S1, and the memory mode setting circuit 210 generates a mode setting signal for setting the operation mode of the memory chip based on the level pattern and the level on the first pin. For example, the memory mode setting circuit 210 may include a arbiter 211 to generate a decision signal and use the decision signal directly as a mode setting signal. A state memory circuit of the controller sets an operation mode of the memory chip upon receiving the mode setting signal. While when the level on the first pin is low, the switch S1 in fig. 4 is turned off, the memory mode setting circuit 210 cannot receive the level pattern on the second pin 202, and thus does not generate a mode setting signal for setting the operation mode of the memory chip. At this time, the state memory circuit of the controller maintains the memory chip in the previously set operation mode. This may provide a stable mode set level to the controller in the DDR memory chip during operation of the memory chip, such that the DDR memory chip operates in either a standard mode or a mirrored mode without requiring a continuous level supply from the MIR pin. This reduces the pin requirements for the DDR memory chip. In other embodiments, if the MIR pin is not removed, the pin that is the MIR pin may be left to its own use, e.g., by introducing a new function into the memory chip or enhancing the access performance of the memory chip, the new function and storage performance being independent of the mirror function. While one embodiment of the present disclosure is described with the MIR pin as an example, it is to be understood that this is merely illustrative and is not limiting of the scope of the present disclosure.

Fig. 6 shows a circuit schematic of decision 212 according to one embodiment of the present disclosure. Decision 212 includes a first decision circuit 212-1, a second decision circuit 212-2, an inverter 216, and a NAND gate 217. Inverter 216 is configured to invert the first level to generate a first inverted level. In one embodiment, inverter 216 receives a RESET input reset_n. Accordingly, when the RESET input reset_n is low, the inverter 216 outputs a high logic level "1". Since the nand gate 217 receives the output of the inverter 216, the nand gate 217 may output a low level only when the inverter 216 receives a low level. Thus, during the first level, the arbiter 212 generates a decision signal for setting the operation mode of the memory chip. It will be appreciated that a high level of the non-reset input may also be applicable, for example, where decision 212 does not include inverter 216 but provides a high level directly to NAND gate 217.

The first decision circuit 212-1 is configured to generate a first decision output based on the level pattern on the one or more second pins. In one embodiment, the first decision circuit 212-1 is configured to generate a first decision output based on the level pattern on the second pin CA <1> and the second pin CA <0>. The first decision circuit 212-1 includes a first P-type field effect transistor M1, a second P-type field effect transistor M2, a first N-type field effect transistor M3, and a second N-type field effect transistor M4 connected in series between the power supply level VDD and the ground GND. The gates of the second P-type field effect transistor M2 and the first N-type field effect transistor M3 are grounded, the gate M1 of the first P-type field effect transistor is coupled to the second pin CA <1>, and the gate of the second N-type field effect transistor is coupled to the second pin CA <0>.

The second decision circuit 212-2 is configured to generate a second decision output based on the level pattern on the one or more second pins. In one embodiment, second decision circuit 212-2 is configured to generate a second decision output based on the second pin CA <1> and the level pattern on second pin CA <0 >. The second decision circuit 212-1 includes a third P-type field effect transistor M5, a fourth P-type field effect transistor M6, a third N-type field effect transistor M7, and a fourth N-type field effect transistor M8 connected in series between the power supply level VDD and the ground GND. The gates of the fourth P-type field effect transistor M6 and the third N-type field effect transistor M7 are coupled to the power supply level VDD, the gate of the third P-type field effect transistor M5 is coupled to the second pin CA <0>, and the gate of the fourth N-type field effect transistor M8 is coupled to the second pin CA <1>.

When the level on the second pin CA <1> is low and the level on the second pin CA <0> is high, the first P-type field effect transistor M1 and the second P-type field effect transistor M2 in the upper half branch of the first decision circuit 212-1 are turned on, and the first N-type field effect transistor M3 and the second N-type field effect transistor M4 in the lower half branch of the first decision circuit 212-1 are turned off. The first decision circuit 212-1 thus provides a first decision output that is high. The third P-type field effect transistor M5 in the upper half leg of the second decision circuit 212-2 is turned off and the fourth N-type field effect transistor M8 in the lower half leg of the second decision circuit 212-2 is turned off. The second decision circuit 212-2 does not provide a second decision output at this time. Accordingly, the nand gate 217 is configured to generate a mode setting signal to set an operation mode of the memory chip based on the first decision output and the first inversion level. In one embodiment, NAND gate 217 generates a low output at output OUT based on inputs that are both high. The memory mode setting circuit 210 thus outputs a low level, for example, sets the memory chip to a mirror mode.

Conversely, when the level on the second pin CA <1> is high and the level on the second pin CA <0> is low, the first PFET M1 in the upper half branch of the first decision circuit 212-1 is turned off and the second NFET M4 in the lower half branch of the first decision circuit 212-1 is turned off. The first decision circuit 212-1 thus does not provide a first decision output. The third P-type field effect transistor M5 in the upper half leg of the second decision circuit 212-2 is turned off and the third N-type field effect transistor M7 and the fourth N-type field effect transistor M8 in the lower half leg of the second decision circuit 212-2 are turned on. The second decision circuit 212-2 now provides a low level second decision output. Accordingly, the nand gate 217 is configured to generate a mode setting signal to set an operation mode of the memory chip based on the second decision output and the first inversion level. In one embodiment, NAND gate 217 generates a high output at output OUT based on the second decision output being both low and the inverting input being high. The memory mode setting circuit 210 thus outputs a high level, for example, sets the memory chip to a standard mode.

By using the determiner 212 shown in fig. 6, the determiner 212 has excellent noise immunity in addition to being able to set the operation mode of the memory chip during reset as described above. In some cases, there may be noise on the first pin CA <1>, the second pin CA <0>, the ground pin GND, and the power pin VDD. The noise-mixed level signal can easily cross the switching threshold voltages of the first P-type field effect transistor M1, the second P-type field effect transistor M2, the third N-type field effect transistor M7 and the fourth N-type field effect transistor M8, so that the first P-type field effect transistor M1, the second P-type field effect transistor M2, the third N-type field effect transistor M7 and the fourth N-type field effect transistor M8 cannot be completely turned on, and thus cannot completely reach the level swing of all 0 or all 1. By adding the first N-type field effect transistor M3, the second N-type field effect transistor M4, the third P-type field effect transistor M5 and the fourth P-type field effect transistor M6, it is possible to help achieve a level swing of all 0 or all 1 in the presence of noise on the first pin CA <1>, the second pin CA <0>, the ground pin GND and the power supply pin VDD, so that the influence of noise can be overcome and the decision device 212 is prevented from providing an erroneous output level.

Although one specific decision circuit configuration of decision 212 is shown in fig. 6, this is merely illustrative and not limiting of the scope of the present disclosure. Other configurations are possible. Fig. 7 shows a circuit configuration of another specific decision device 213. The decision 213 may use a second pin to generate the decision signal. In one embodiment, the determiner 213 includes a first P-type field effect transistor M1, a second P-type field effect transistor M2, a third N-type field effect transistor M7, and a fourth N-type field effect transistor M8 sequentially connected in series between the power supply voltage VDD and the ground GND. The gates of the first and fourth PFETs M1 and M8 receive CA <1>, the gate of the second PFET M2 is grounded, the gate of the third NFET M7 is coupled to the supply voltage VDD, and the node between the second and third PFETs M2 and M7 is coupled to the NAND gate 217. The first input N1 in the nand gate 217 receives a low level when CA <1> is "1", and the first input N1 in the nand gate 217 receives a high level when CA <1> is "0". The operation of the nand gate 217 and the inverter 216 in the decision device 213 is the same as the operation of the nand gate 217 and the inverter 216 in fig. 6, and will not be described again. The single decision circuit described above may use fewer transistors and occupy less chip area and reduce cost compared to the configuration shown in fig. 6.

Fig. 8 illustrates a flow chart of a method 800 of mode control of a memory chip according to one embodiment of the present disclosure. It will be appreciated that the various aspects described above with respect to fig. 1-7 may be selectively applied to the method 800. At 802, a level is received via a first pin of a memory chip. At 804, during a period when the level on the first pins is a first level, a mode setting signal for setting an operation mode of the memory chip is generated based on the level pattern on the one or more second pins of the memory chip. At 806, in response to detecting the transition of the level on the first pin from the first level to the second level, the memory chip is caused to operate in an operational mode set by the mode setting signal.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Claims

A memory chip, comprising:

a first pin;

one or more second pins;

a memory unit;

A mode setting circuit configured to:

generating a mode setting signal for setting an operation mode of the memory chip based on the level pattern on the one or more second pins during a period in which the level on the first pin is a first level; and

in response to a transition of the level on the first pin from a first level to a second level, the memory chip operates in a mode set by the mode setting signal.
The memory chip of claim 1, wherein the memory chip is configured to obtain command or address signals through the one or more second pins after the level on the first pin transitions to a second level.
The memory chip of claim 1 or 2, wherein the modes of operation include a mirror mode and a standard mode; and

the mode setting signal is used to set an operation mode of the memory chip to the mirror mode or the standard mode.
The memory chip of any one of claims 1-3, wherein the mode setting circuit comprises:

a determiner configured to generate a determination signal based on the first level on the first pin and a level pattern on the one or more second pins; and

A latch configured to generate the mode setting signal based on the decision signal during a time when the level on the first pin is the first level and to generate the mode setting signal in response to the level on the first pin transitioning from the first level to a second level.
The memory chip of claim 4, wherein the arbiter comprises:

a first decision circuit configured to generate a first decision output based on the level pattern on the one or more second pins;

a second decision circuit configured to generate a second decision output based on the level pattern on the one or more second pins; and

logic circuitry coupled to the first decision circuitry and the second decision circuitry and configured to generate the decision signal based on the first decision output or the second decision output during the first level.
The memory chip of claim 5, wherein the first decision circuit comprises:

a first P-type field effect transistor, a second P-type field effect transistor, a first N-type field effect transistor, and a second N-type field effect transistor connected in series between a power supply level and ground, gates of the second P-type field effect transistor and the first N-type field effect transistor being grounded, a gate of the first P-type field effect transistor being coupled to one of the one or more second pins, and a gate of the second N-type field effect transistor being coupled to another of the one or more second pins.
The memory chip of claim 6, wherein the second decision circuit comprises:

a third P-type field effect transistor, a fourth P-type field effect transistor, a third N-type field effect transistor, and a fourth N-type field effect transistor connected in series between the power supply level and the ground, gates of the fourth P-type field effect transistor and the third N-type field effect transistor being coupled to the power supply level, a gate of the third P-type field effect transistor being coupled to the other of the one or more second pins, and a gate of the fourth N-type field effect transistor being coupled to the one of the one or more second pins.
The memory chip of any of claims 1-3, wherein the mode setting circuit is further configured to:

generating a first mode control signal for setting an operation mode of the memory chip to a mirror mode if a level of one of the one or more second pins is a third level during the level on the first pin is the first level; and

during the level on the first pin is a first level, if the level of the one or more second pins is a fourth level different from the third level, a second mode control signal for setting an operation mode of the memory chip to a standard mode is generated.
The memory chip of any one of claims 1-8, wherein the mode setting circuit is further configured to disconnect electrical connection with the one or more second pins in response to a level on the first pin transitioning from the first level to the second level.
A circuit assembly, comprising:

a circuit board; and

the memory chip of any one of claims 1-9, mounted on the circuit board.
An electronic device, comprising:

a processor; and

the circuit assembly of claim 10.
A package structure, comprising:

the memory chip of any one of claims 1-9, and

and a package housing encapsulating the memory chip.
A method for controlling a memory chip, comprising:

receiving a level via a first pin of the memory chip;

generating a mode setting signal for setting an operation mode of the memory chip based on a level pattern on one or more second pins of the memory chip during a period in which a level on the first pin is a first level; and

the memory chip is caused to operate in a mode set by the mode setting signal in response to a transition of the level on the first pin from a first level to a second level.
The method of claim 13, wherein the first pin comprises a reset pin and the first level comprises a set low level.
The method of claim 13 or 14, further comprising:

after the level on the first pin transitions from the first level to the second level, the memory chip retrieves command or address signals through the one or more second pins.
The method of any of claims 13-15, wherein the one or more second pins include a first command address pin and a second command address pin; and

generating a mode setting signal for setting an operation mode of the memory chip includes:

generating a first mode setting signal for setting an operation mode of the memory chip to a mirror mode if a level of the first command address pin is a low level and a level of the second command address pin is a high level during the level on the first pin is a first level; and

during the level on the first pin is a first level, if the level of the first command address pin is a high level and the level of the second command address pin is a low level, a second mode setting signal for setting the operation mode of the memory chip to a standard mode is generated.
The method of any of claims 13-15, wherein generating a mode setting signal for setting an operating mode of the memory chip comprises:

generating a first mode setting signal for setting an operation mode of the memory chip to a mirror mode if a level of one of the one or more second pins is a third level during the level on the first pin is the first level; and

during the level on the first pin is a first level, if the level of the one or more second pins is a fourth level different from the third level, a second mode setting signal for setting an operation mode of the memory chip to a standard mode is generated.
The method of any of claims 13-17, wherein causing the memory chip to operate in a mode set by the mode set signal comprises: in response to a level transition on the first pin from the first level to the second level, the mode setting circuit in the memory chip is disconnected from electrical connection with the one or more second pins.