CN116860676A - High-speed long-distance on-board chip communication system and method for aerospace distributed system - Google Patents

Abstract

The invention relates to a high-speed long-distance board-level chip-to-chip communication system and a method of an aerospace distributed system, which are designed based on hardware schemes of SPI and LVDS, wherein a left-side board-level FPGA/DSP/ARM chip is used as a host of the SPI, a right-side board-level FPGA/DSP/ARM chip is used as a slave of the SPI, the master-slave uses SPI_CLK, SPI_MOSI, SPI_CS and SPI_MISO 4 interfaces which are commonly used by the SPI, and link transmission between chips at two sides is realized by adopting LVDS transceiver chips; when the host computer communicates with the corresponding slave computer, the host computer sets the chip selection CS signal line, and the invention designs an inter-board communication method suitable for different types of chips, which has the advantages of high communication rate and strong anti-interference capability and is suitable for an aerospace distributed system.

Description

High-speed long-distance on-board chip communication system and method for aerospace distributed system

Technical Field

The invention belongs to the technical field of data transmission, and particularly relates to a high-speed long-distance on-board chip communication system and method of an aerospace distributed system.

Background

There are a large number of distributed electronic systems in satellite or space stations, and as the complexity of the aerospace distributed electronic systems increases, various controller module combinations of FPGA or DSP or ARM will appear in each electronic system, and there are huge data transmission and instruction transmission requirements between the controller modules of these systems. However, the communication modes adopted by the controllers of the equipment nodes in the aerospace distributed system are not completely the same, which can cause the network environment in the aerospace distributed system to be divided into independent areas, and the consistency of the communication modes among the systems cannot be maintained. And considering that the information transmission delays of the independent partition networks are different, the information of each node in the system is collected to cover the maximum delay time of all communication modes in the system. SPI is used as a high-speed, full duplex and synchronous communication bus, and can only carry out short-distance inter-chip communication in a board, and is widely used for the inter-chip communication in a board at present, but is not applied to the high-speed long-distance inter-chip communication in an aerospace distributed system.

Disclosure of Invention

The invention provides a high-speed long-distance on-board chip communication system and method for an aerospace distributed system, which are used for solving the technical problems of high-speed, long-distance, low-power consumption and anti-interference communication in the aerospace distributed system by adopting an SPI communication bus protocol.

The invention provides a high-speed long-distance board-level chip-to-chip communication system of an aerospace distributed system, which comprises: a host chip, a slave chip and a middle LVDS interface chip,

the host chip reads the host sending buffer area and judges whether the host chip has instruction data to send to the slave chip, if no instruction data is sent to the slave chip, the host chip waits for the next communication period;

the intermediate LVDS interface chip comprises a host side transmitting driver, a slave side receiving driver, a slave side transmitting driver, a host side receiving driver,

if the host chip judges that the instruction data is sent to the slave chip, the master chip and the slave chip communicate with each other, the host chip generates a first signal, and communication starts; the method comprises the steps that a first signal is sent to a sending driver at the host side, the first signal is converted into a first differential signal through the sending driver at the host side for inter-board transmission, and a receiving driver at the slave side receives the first differential signal and converts the first differential signal into a first signal to be sent to a slave chip;

the slave chip generates a second signal, the second signal is sent to the slave side sending driver, the second signal is converted into a second differential signal by the slave side sending driver for inter-board transmission, and the host side receiving driver receives the second differential signal and converts the second differential signal into a second signal to be sent to the host chip.

Further, the communication between the master chip and the slave chip further includes:

the host chip reads the host receiving buffer area and judges whether the receiving check bit of the host chip is correct or not, when the receiving check bit is incorrect, the last data packet is retransmitted to the host sending buffer area, when the receiving check bit is correct, the receiving data is stored in the host receiving buffer area, meanwhile, the sending data is stored in the host sending buffer area for sending, and the data packet transmission in one communication period of the host is finished;

when communication starts, the slave machine reads the receiving buffer zone of the slave machine, judges whether the receiving check bit of the slave machine is correct or not, sends the check bit zero sent by the slave machine when the receiving check bit is correct, stores the received data in the receiving buffer zone of the slave machine, simultaneously stores the sent data in the sending buffer zone of the slave machine for sending, and the data packet transmission in one communication period of the slave machine is finished, so that the communication in one communication period of the master machine and the slave machine is finished.

Further, the host chip comprises a first interface and a second interface, the host chip sends a first signal to the host side sending driver through the first interface,

the host side receiving driver sends a second signal to a second interface of the host chip;

the slave chip comprises a third interface and a fourth interface, and receives a first signal sent by a driver from the slave side of the intermediate LVDS interface chip through the third interface; the slave chip sends a second signal to the slave-side transmit driver of the intermediate LVDS interface chip via the fourth interface.

Further, the first interface of the host chip comprises a first SPI_CLK sub-interface, a first SPI_MOSI sub-interface and a first SPI_CS sub-interface; the slave chip third interface comprises a second SPI_CLK sub-interface, a second SPI_MOSI sub-interface and a second SPI_CS sub-interface;

the host side transmitting driver comprises a first input interface, a second input interface and a third input interface, wherein the first differential signal output interface, the second differential signal output interface and the third differential signal output interface;

the host side receiving driver comprises a first differential signal receiving interface, a second differential signal receiving interface, a third differential signal receiving interface, a first output interface, a second output interface and a third output interface;

based on an SPI communication protocol, the first signal comprises an SPI_CLK signal, an SPI_MOSI signal and an SPI_CS signal, the host chip sends the SPI_CLK signal to the first input interface through the first SPI_CLK sub-interface, the SPI_MOSI signal is sent to the second input interface through the first SPI_MOSI sub-interface, and the SPI_CS signal is sent to the third input interface through the first SPI_CS sub-interface;

the host side transmitting driver converts the SPI_CLK signal, the SPI_MOSI signal and the SPI_CS signal into a first differential signal group, wherein the first differential signal group comprises the SPI_CLK differential signal, the SPI_MOSI differential signal and the SPI_CS differential signal which are respectively output through a first differential signal output interface, a second differential signal output interface and a third differential signal output interface;

the slave side receiving driver respectively receives SPI_CLK differential signals, SPI_MOSI differential signals and SPI_CS differential signals from the first differential signal output interface, the second differential signal output interface and the third differential signal output interface by utilizing the first differential signal receiving interface, the second differential signal receiving interface and the third differential signal receiving interface, and respectively converts the SPI_CLK signals, the SPI_MOSI signals and the SPI_CS signals into SPI_CLK signals, SPI_MOSI signals and SPI_CS signals and then respectively outputs the SPI_CLK signals through the first output interface, the second output interface and the third output interface;

the SPI_CLK signal output by the first output interface is received from the second SPI_CLK sub-interface of the chip, the SPI_MOSI signal output by the second output interface is received by the second SPI_MOSI sub-interface, and the SPI_CS signal output by the third output interface is received by the second SPI_CS sub-interface.

Further, the fourth interface of the slave chip is a first SPI_MISO interface, and the second interface of the host chip is a second SPI_MISO interface;

the slave-side transmitting driver comprises a fourth input interface and a fourth differential signal output interface;

the host side receiving driver comprises a fourth differential signal receiving interface and a fourth output interface;

based on an SPI communication protocol, the second signal is an SPI_MISO signal, and the SPI_MISO signal is sent from the chip to the fourth input interface through the first SPI_MISO interface;

the slave side transmitting driver converts the SPI_MISO signal into an SPI_MISO differential signal as a second differential signal and outputs the SPI_MISO differential signal through a fourth differential signal output interface;

the host side receiving driver receives the SPI_MISO differential signal from the fourth differential signal output interface by using the fourth differential signal receiving interface, converts the SPI_MISO differential signal into the SPI_MISO signal and outputs the SPI_MISO signal through the fourth output interface;

the second SPI_MISO interface of the host chip receives the SPI_MISO signal output by the fourth output interface.

Further, the host chip or the slave chip is an FPGA, and the GPIOs of the FPGA chip are configured to be an spi_clk interface, an spi_mosi interface, an spi_cs interface, and an spi_miso interface of an SPI protocol for communication.

Further, the host chip or the slave chip is a DSP or ARM, and the SPI_CLK interface, the SPI_MOSI interface, the SPI_CS interface and the SPI_MISO interface of the SPI hard core of the DSP or the ARM chip are utilized for communication.

The invention also provides a high-speed long-distance board-level chip-to-chip communication method of the aerospace distributed system, which comprises the following steps:

the process of the host chip sending the first signal to the slave chip is as follows: the host chip sends a first signal to the intermediate LVDS interface chip, the intermediate LVDS interface chip comprises a host side sending driver, a slave side receiving driver, a slave side sending driver and a host side receiving driver, the host side sending driver receives the first signal and converts the first signal into a first differential signal group and then sends the first differential signal group to the slave side receiving driver, and the slave side receiving driver converts the first differential signal group into the first signal and sends the first signal to the slave chip;

the process of sending the second signal from the chip to the host chip is: the slave-side transmission driver receives the second signal transmitted from the chip and converts it into a second differential signal to be transmitted to the host-side reception driver, and the host-side reception driver converts the second differential signal into the second signal to be transmitted to the host chip.

Further, the sending, by the host chip, the first signal to the slave chip further includes:

based on an SPI communication protocol, the first signal comprises an SPI_CLK signal, an SPI_MOSI signal and an SPI_CS signal, and the host chip sends the SPI_CLK signal, the SPI_MOSI signal and the SPI_CS signal to a host side sending driver;

the host side transmitting driver respectively converts the SPI_CLK signal, the SPI_MOSI signal and the SPI_CS signal into a first differential signal group and outputs the first differential signal group, wherein the first differential signal group comprises the SPI_CLK differential signal, the SPI_MOSI differential signal and the SPI_CS differential signal;

the slave side receiving driver receives the SPI_CLK differential signal, the SPI_MOSI differential signal and the SPI_CS differential signal, and respectively converts the signals into the SPI_CLK signal, the SPI_MOSI signal and the SPI_CS signal and then respectively outputs the signals;

the SPI_CLK signal, the SPI_MOSI signal, and the SPI_CS signal are received from the chip.

Further, transmitting the second signal from the chip to the host chip further includes:

based on the SPI communication protocol, the second signal is an SPI_MISO signal, and the SPI_MISO signal is sent from the chip to the slave side sending driver;

the slave-side transmitting driver converts the spi_miso into an spi_miso differential signal as a second differential signal output;

the host side receiving driver receives the SPI_MISO differential signal, converts the SPI_MISO differential signal into an SPI_MISO signal and outputs the SPI_MISO signal;

the host chip receives the spi_miso signal.

The invention can realize long-distance high-speed communication of different controllers by combining the advantages of SPI and LVDS, is very suitable for the communication process in an aerospace distributed system, has consistent slave interfaces, and can be used by plug and play and equivalently replaced. The invention can be applied to the communication of each module of the aerospace distributed system, so that the communication between the distributed systems has the advantages of high transmission rate, long transmission distance, low power consumption and strong anti-interference performance.

Drawings

FIG. 1 is a schematic communication diagram of a left-side board level master and a right-side board level slave of the present invention.

Fig. 2 is a functional diagram of a left side board level master and a right side board level slave of the present invention.

FIG. 3 is a flow chart of a master-slave transmission process of the present invention.

Fig. 4 is a schematic diagram of the content of a master-slave transport protocol packet format according to the present invention.

Detailed Description

In the following description, specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details; in other instances, well-known features have not been described in detail in order to avoid obscuring the invention.

The invention provides a high-speed long-distance on-board chip communication system and method for an aerospace distributed system.

The invention relates to an aerospace distributed system high-speed long-distance board-level chip-to-chip communication system, which comprises: a host chip, a slave chip and a middle LVDS interface chip.

The host chip comprises a first interface and a second interface, and the host chip sends a first signal to the intermediate LVDS interface chip through the first interface.

The intermediate LVDS interface chip includes a host side transmission driver LVDS31-1, a slave side reception driver LVDS32-1, a slave side transmission driver LVDS31-2, and a host side reception driver LVDS32-2, and the host side transmission driver receives the first signal and converts it into a first differential signal group and then transmits it to the slave side reception driver LVDS32-1, and the slave side reception driver LVDS32-1 converts the first differential signal group into the first signal and transmits it to the slave chip.

The slave-side transmission driver LVDS31-2 receives the second signal transmitted from the chip and converts it into a second differential signal and transmits it to the host-side reception driver LVDS32-2, and the host-side reception driver LVDS32-2 converts the second differential signal into a second signal and transmits it to the second interface of the host chip.

The slave chip comprises a third interface and a fourth interface, and receives a first signal sent by a driver from the slave side of the intermediate LVDS interface chip through the third interface; the slave chip sends a second signal to the slave-side transmit driver of the intermediate LVDS interface chip via the fourth interface.

In one embodiment, taking dual-full-scale communication between a left-side board host computer and a right-side board slave computer as an example, as shown in fig. 1, the communication schematic diagram of the left-side board host computer and the right-side board slave computer includes a left-side board FPGA/DSP/ARM chip, a right-side board FPGA/DSP/ARM chip and a middle LVDS interface chip; the master control chip of the SPI communication host is an FPGA or a DSP or an ARM chip, the slave of the SPI communication host is a right-side-plate-level FPGA/DSP/ARM, and the master control chip of the SPI communication slave is an FPGA or a DSP or an ARM chip; when the master control chips of the left side plate level master computer and the right side plate level slave computer are FPGA, the master-slave computer needs to configure GPIO of the master-slave computer into 4 interfaces of SPI_CLK, SPI_MOSI, SPI_CS and SPI_MISO for communication; when the main control chips of the left side plate level main machine and the right side plate level auxiliary machine are DSPs or ARM with SPI hard cores, the main machine can communicate by using 4 interfaces of SPI_CLK, SPI_MOSI, SPI_CS and SPI_MISO of the SPI hard cores.

In one embodiment, as shown in fig. 2, the left side board FPGA/DSP/ARM and the right side board FPGA/DSP/ARM each include:

SPI_CLK, for clock signal, generated by left side board stage host;

SPI_MOSI is used for data output of the left side plate level host computer and data input of the right side plate level slave computer;

SPI_CS, which is used for the enabling signal input of the right side plate slave machine and is output and controlled by the left side plate master machine;

SPI_MISO is used for the data input of the left side plate level host computer and the data output of the right side plate level slave computer.

In one embodiment, the intermediate LVDS interface chip includes a host side transmit driver LVDS31-1, a slave side transmit driver LVDS31-2 two-piece transmit driver and a slave side receive driver LVDS32-1, a host side receive driver LVDS32-2 two-piece receive driver. The LVDS31-1 and LVDS31-2 transmitting drivers convert single-ended signals into differential signals, and the LVDS32-1 and LVDS32-2 receiving drivers convert the differential signals into single-ended signals, so that the differential signals are used for long-distance transmission.

In one embodiment, as shown in fig. 1, the left-side board host sends spi_clk signal, spi_mosi signal, and spi_cs signal through the first spi_clk sub-interface, the first spi_mosi sub-interface, and the first spi_cs sub-interface respectively, which form first signals, which are respectively converted into spi_clk differential signal, spi_mosi differential signal, and spi_cs differential signal by the host-side sending driver LVDS31-1 through the first input interface TIN1, the second input interface TIN2, and the third input interface TIN3 of the host-side sending driver LVDS31-1, and are output as a first differential signal group, the spi_clk differential signal is output by the first differential signal output interfaces dout1+ and DOUT1-, the spi_mosi differential signal is output by the second differential signal output interfaces dout2+ and DOUT2-, and the spi_cs differential signal is output by the third differential signal output interfaces dout3+ and DOUT 3-. The three pairs of differential output signals are respectively converted into SPI_CLK signals, SPI_MOSI signals and SPI_CS signals after being received by the first differential signal receiving interfaces RIN1+ and RIN1-, the second differential signal receiving interfaces RIN2+ and RIN2-, and the third differential signal receiving interfaces RIN3+ and RIN 3-of the LVDS32-1 receiving driver, and are respectively transmitted to three signal receiving ends of a second SPI_CLK sub-interface, a second SPI_MOSI sub-interface and a second SPI_CS sub-interface of the right side plate slave machine through the first output interface DOUT1, the second output interface DOUT2 and the third output interface DOUT 3.

Meanwhile, the single-ended transmission second signal SPI_MISO of the right side plate slave machine is converted into DOUT1+ and DOUT 1-pair differential signals by the LVDS31-2 transmission driver, the pair of differential output signals are output by the fourth input interface TIN1, the pair of differential output signals are received by the fourth differential signal receiving interfaces RIN1+ and RIN 1-of the LVDS32-2 receiving driver, then converted into SPI_MISO signals, and then the single-ended output signals are transmitted to the second SPI_MISO interface of the left side plate slave machine by the fourth output interface DOUT 1.

In one embodiment, the left side board level host controls the SPI_CS signal, and communication begins when SPI_CS is pulled low; when spi_cs is pulled high, the communication ends.

The invention also provides a high-speed long-distance board-level chip-to-chip communication method of the aerospace distributed system, which comprises the following steps:

the host chip sends a first signal to the slave chip: the host chip transmits the first signal to the intermediate LVDS interface chip, which includes a host side transmission driver LVDS31-1, a slave side reception driver LVDS32-1, a slave side transmission driver LVDS31-2, and a host side reception driver LVDS32-2, the host side transmission driver receiving the first signal and converting it into a first differential signal group and then transmitting it to the slave side reception driver LVDS32-1, and the slave side reception driver LVDS32-1 converting the first differential signal group into the first signal and transmitting it to the slave chip.

Transmitting a second signal from the chip to the host chip: the slave-side transmission driver LVDS31-2 receives the second signal transmitted from the chip and converts it into a second differential signal and transmits it to the host-side reception driver LVDS32-2, and the host-side reception driver LVDS32-2 converts the second differential signal into a second signal and transmits it to the host chip.

In one embodiment, as shown in fig. 3, which is a flow chart of a master-slave transmission process of the present invention, first, a host chip reads its receiving buffer and transmitting buffer, determines whether the host chip has instruction data to transmit to a slave chip, and if no instruction data is transmitted to the slave chip, waits for a next communication cycle.

If the host chip is judged to have instruction data and sends the instruction data to the slave chip, the host chip generates an SPI_CS signal, generates an SPI_CLK signal and an SPI_MOSI signal, and starts communication; the SPI_CS signal, the SPI_CLK signal and the SPI_MOSI signal are sent to a host side sending driver and converted into an SPI_CS differential signal, an SPI_CLK differential signal and an SPI_MOSI differential signal for board-to-board transmission, and a slave side receiving driver receives the differential signals and converts them back into the SPI_CS signal, the SPI_CLK signal and the SPI_MOSI signal to be sent to a slave chip.

Meanwhile, an SPI_MISO signal is generated from the chip and sent to the sending driver, the SPI_MISO signal is converted into a pair of differential signals through the sending driver of the slave side for inter-board transmission, and the pair of differential signals are converted into corresponding single-ended signals through the receiving driver of the host side for input to the host.

In each SPI_CLK clock cycle, transmission is performed between the master and slave chips.

The host chip reads the host receiving buffer area and judges whether the receiving check bit of the host chip is correct or not, if not, the last SPI protocol data packet is retransmitted to the host transmitting buffer area, and if the receiving check bit is correct, the receiving data is stored in the host receiving buffer area, and meanwhile, the transmitting data is stored in the host transmitting buffer area for transmitting, and the protocol packet transmission in one communication period of the host is ended.

When communication starts, the slave reads the receiving buffer zone of the slave, judges whether the receiving check bit of the slave is correct or not, sends the check bit zero sent by the slave when the receiving check bit is incorrect, stores the received data in the receiving buffer zone of the slave and simultaneously stores the sent data in the sending buffer zone of the slave for sending, and the SPI protocol data packet transmission in one communication period of the slave is finished, so that the SPI protocol data packet transmission in one communication period of the master and the slave is finished.

In one embodiment, as shown in fig. 4, the protocol packet format of the master-slave machine for full duplex data transmission includes a packet header bit, a data bit and a check bit, where the packet header bit is a fixed byte, the data bit is information that the master-slave machine transmits to each other, and the check bit is an accumulated sum of the data bits.

The invention is based on SPI communication protocol, combines LVDS hardware to design interface, the master-slave machine can be controllers with different properties, the left-side-plate FPGA/DSP/ARM can be used as the host machine of SPI communication, the master control chip can be FPGA or DSP or ARM chip, the right-side-plate FPGA/DSP/ARM can be used as the slave machine of SPI communication, and the master control chip can be FPGA or DSP or ARM chip; each path of SPI needs to be configured into 4 interfaces of common SPI_CLK, SPI_MOSI, SPI_CS and SPI_MISO for communication, when the left side board level host computer pulls down a chip selection SPI_CS signal and is configured to generate a corresponding SPI_CLK signal, the communication starts, the master-slave machine performs full duplex data communication, when the left side board level host computer pulls up a Gao Pianxuan SPI_CS signal, the communication ends, and the next round of communication is prepared. The invention can realize long-distance high-speed communication of different controllers by combining the advantages of SPI protocol and LVDS, is very suitable for the communication process in an aerospace distributed system, has consistent slave interfaces, and can be used by plug and play and equivalently replaced.

While the present invention has been described in detail with reference to the drawings, the present invention is not limited to the specific details of the foregoing embodiments, and various equivalent changes may be made to the technical solution of the present invention within the scope of the technical concept of the present invention, and all such equivalent changes belong to the protection scope of the present invention.

Claims (10)

1. An aerospace distributed system high-speed long-distance board-level inter-chip communication system, comprising: a host chip, a slave chip and a middle LVDS interface chip,

the host chip reads the host sending buffer area and judges whether the host chip has instruction data to send to the slave chip, if no instruction data is sent to the slave chip, the host chip waits for the next communication period;

the intermediate LVDS interface chip comprises a host side transmitting driver, a slave side receiving driver, a slave side transmitting driver, a host side receiving driver,

if the host chip judges that the instruction data is sent to the slave chip, the master chip and the slave chip communicate with each other, the host chip generates a first signal, and communication starts; the method comprises the steps that a first signal is sent to a sending driver at the host side, the first signal is converted into a first differential signal through the sending driver at the host side for inter-board transmission, and a receiving driver at the slave side receives the first differential signal and converts the first differential signal into a first signal to be sent to a slave chip;

the slave chip generates a second signal, the second signal is sent to the slave side sending driver, the second signal is converted into a second differential signal by the slave side sending driver for inter-board transmission, and the host side receiving driver receives the second differential signal and converts the second differential signal into a second signal to be sent to the host chip.

2. The system of claim 1, wherein the communication between the master-slave chips further comprises:

the host chip reads the host receiving buffer area and judges whether the receiving check bit of the host chip is correct or not, when the receiving check bit is incorrect, the last data packet is retransmitted to the host sending buffer area, when the receiving check bit is correct, the receiving data is stored in the host receiving buffer area, meanwhile, the sending data is stored in the host sending buffer area for sending, and the data packet transmission in one communication period of the host is finished;

when communication starts, the slave machine reads the receiving buffer zone of the slave machine, judges whether the receiving check bit of the slave machine is correct or not, sends the check bit zero sent by the slave machine when the receiving check bit is correct, stores the received data in the receiving buffer zone of the slave machine, simultaneously stores the sent data in the sending buffer zone of the slave machine for sending, and the data packet transmission in one communication period of the slave machine is finished, so that the communication in one communication period of the master machine and the slave machine is finished.

3. The system of claim 1, wherein the host chip includes a first interface through which the host chip sends the first signal to the host side send driver and a second interface,

the host side receiving driver sends a second signal to a second interface of the host chip;

the slave chip comprises a third interface and a fourth interface, and receives a first signal sent by a driver from the slave side of the intermediate LVDS interface chip through the third interface; the slave chip sends a second signal to the slave-side transmit driver of the intermediate LVDS interface chip via the fourth interface.

4. The system of claim 3, wherein the host chip first interface comprises a first spi_clk sub-interface, a first spi_mosi sub-interface, a first spi_cs sub-interface; the slave chip third interface comprises a second SPI_CLK sub-interface, a second SPI_MOSI sub-interface and a second SPI_CS sub-interface;

the host side transmitting driver comprises a first input interface, a second input interface and a third input interface, wherein the first differential signal output interface, the second differential signal output interface and the third differential signal output interface;

the host side receiving driver comprises a first differential signal receiving interface, a second differential signal receiving interface, a third differential signal receiving interface, a first output interface, a second output interface and a third output interface;

based on an SPI communication protocol, the first signal comprises an SPI_CLK signal, an SPI_MOSI signal and an SPI_CS signal, the host chip sends the SPI_CLK signal to the first input interface through the first SPI_CLK sub-interface, the SPI_MOSI signal is sent to the second input interface through the first SPI_MOSI sub-interface, and the SPI_CS signal is sent to the third input interface through the first SPI_CS sub-interface;

the host side transmitting driver converts the SPI_CLK signal, the SPI_MOSI signal and the SPI_CS signal into a first differential signal group, wherein the first differential signal group comprises the SPI_CLK differential signal, the SPI_MOSI differential signal and the SPI_CS differential signal which are respectively output through a first differential signal output interface, a second differential signal output interface and a third differential signal output interface;

the slave side receiving driver respectively receives SPI_CLK differential signals, SPI_MOSI differential signals and SPI_CS differential signals from the first differential signal output interface, the second differential signal output interface and the third differential signal output interface by utilizing the first differential signal receiving interface, the second differential signal receiving interface and the third differential signal receiving interface, and respectively converts the SPI_CLK signals, the SPI_MOSI signals and the SPI_CS signals into SPI_CLK signals, SPI_MOSI signals and SPI_CS signals and then respectively outputs the SPI_CLK signals through the first output interface, the second output interface and the third output interface;

the SPI_CLK signal output by the first output interface is received from the second SPI_CLK sub-interface of the chip, the SPI_MOSI signal output by the second output interface is received by the second SPI_MOSI sub-interface, and the SPI_CS signal output by the third output interface is received by the second SPI_CS sub-interface.

5. The system of claim 4, wherein the fourth interface of the slave chip is a first spi_miso interface and the second interface of the master chip is a second spi_miso interface;

the slave-side transmitting driver comprises a fourth input interface and a fourth differential signal output interface;

the host side receiving driver comprises a fourth differential signal receiving interface and a fourth output interface;

based on an SPI communication protocol, the second signal is an SPI_MISO signal, and the SPI_MISO signal is sent from the chip to the fourth input interface through the first SPI_MISO interface;

the slave side transmitting driver converts the SPI_MISO signal into an SPI_MISO differential signal as a second differential signal and outputs the SPI_MISO differential signal through a fourth differential signal output interface;

the host side receiving driver receives the SPI_MISO differential signal from the fourth differential signal output interface by using the fourth differential signal receiving interface, converts the SPI_MISO differential signal into the SPI_MISO signal and outputs the SPI_MISO signal through the fourth output interface;

the second SPI_MISO interface of the host chip receives the SPI_MISO signal output by the fourth output interface.

6. The system of claim 5, wherein the host chip or slave chip is an FPGA, and wherein the GPIOs of the FPGA chip are configured as an spi_clk interface, an spi_mosi interface, an spi_cs interface, and an spi_miso interface of an SPI protocol for communication.

7. The system of claim 5, wherein the host or slave chip is a DSP or ARM, and communicates using the spi_clk interface, the spi_mosi interface, the spi_cs interface, and the spi_miso interface of the SPI hard core of the DSP or ARM chip.

8. The high-speed long-distance board-level chip-to-chip communication method of the aerospace distributed system is characterized by comprising the following steps of:

the process of the host chip sending the first signal to the slave chip is as follows: the host chip sends a first signal to the intermediate LVDS interface chip, the intermediate LVDS interface chip comprises a host side sending driver, a slave side receiving driver, a slave side sending driver and a host side receiving driver, the host side sending driver receives the first signal and converts the first signal into a first differential signal group and then sends the first differential signal group to the slave side receiving driver, and the slave side receiving driver converts the first differential signal group into the first signal and sends the first signal to the slave chip;

the process of sending the second signal from the chip to the host chip is: the slave-side transmission driver receives the second signal transmitted from the chip and converts it into a second differential signal to be transmitted to the host-side reception driver, and the host-side reception driver converts the second differential signal into the second signal to be transmitted to the host chip.

9. The method of claim 8, wherein the host chip transmitting the first signal to the slave chip further comprises:

based on an SPI communication protocol, the first signal comprises an SPI_CLK signal, an SPI_MOSI signal and an SPI_CS signal, and the host chip sends the SPI_CLK signal, the SPI_MOSI signal and the SPI_CS signal to a host side sending driver;

the host side transmitting driver respectively converts the SPI_CLK signal, the SPI_MOSI signal and the SPI_CS signal into a first differential signal group and outputs the first differential signal group, wherein the first differential signal group comprises the SPI_CLK differential signal, the SPI_MOSI differential signal and the SPI_CS differential signal;

the slave side receiving driver receives the SPI_CLK differential signal, the SPI_MOSI differential signal and the SPI_CS differential signal, and respectively converts the signals into the SPI_CLK signal, the SPI_MOSI signal and the SPI_CS signal and then respectively outputs the signals;

the SPI_CLK signal, the SPI_MOSI signal, and the SPI_CS signal are received from the chip.

10. The method of claim 8, wherein transmitting the second signal from the chip to the host chip further comprises:

based on the SPI communication protocol, the second signal is an SPI_MISO signal, and the SPI_MISO signal is sent from the chip to the slave side sending driver;

the slave-side transmitting driver converts the spi_miso into an spi_miso differential signal as a second differential signal output;

the host side receiving driver receives the SPI_MISO differential signal, converts the SPI_MISO differential signal into an SPI_MISO signal and outputs the SPI_MISO signal;

the host chip receives the spi_miso signal.