CN116578528A - Multi-FPGA prototype verification platform hardware architecture of multi-mode hybrid interconnection architecture - Google Patents
Multi-FPGA prototype verification platform hardware architecture of multi-mode hybrid interconnection architecture Download PDFInfo
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- G—PHYSICS
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- G06F15/163—Interprocessor communication
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Abstract
The invention discloses a multi-FPGA prototype verification platform hardware architecture of a multi-mode hybrid interconnection architecture, which comprises a high-speed switching network, a plurality of circuit board cards and a plurality of high-speed serial transceivers, wherein a plurality of FPGAs are arranged in each circuit board card, the FPGAs in the same circuit board card are directly connected in a board by utilizing an LVDS interface, the FPGAs among different circuit board cards are connected with the plurality of high-speed serial transceivers through the high-speed switching network, and the FPGAs in the same circuit board card are not directly connected in a board through the high-speed switching network and the high-speed serial transceivers. Communication interconnection based on a high-speed switching network is added between the FPGAs, various architectures can be realized by changing the connection relation of high-speed serial transceivers in and between boards, the flexibility and the expandability of a platform are enhanced, the bandwidth is increased by thousands of times, the simulation performance is improved, the pin resources of the FPGAs are saved, and the division and adjustment of the FPGA resources and the bandwidth resources are realized.
Description
Technical Field
The invention belongs to the technical field of FPGA hardware architecture, and particularly relates to a multi-FPGA prototype verification platform hardware architecture of a multi-mode hybrid interconnection architecture.
Background
For large ASIC designs, when performing FPGA prototype verification, one FPGA often contains incomplete designs, and multiple FPGAs need to be interconnected to form a multi-FPGA system to verify the whole design. At this time, the ASIC design needs to be partitioned, and a part of the design is placed on each FPGA. The end-to-end communication is performed in a TDM (time division multiplexing) mode between the FPGAs of most of the multi-FPGA prototype verification systems at present, so that the main frequency inside the FPGAs and the inter-FPGA bandwidth have a tight coupling relationship, namely: when the communication bandwidth between the FPGA is determined, if the number of signals to be transmitted between two chips is large, the time division multiplexing rate is inevitably increased, so that the main frequency of the FPGA system is reduced, and the simulation performance is reduced.
In addition, if the FPGA prototype verification of the larger-scale ASIC design is performed, more FPGA resources are needed, and because the number of FPGA pins is limited, when more FPGA chips are interconnected, the number of pin resources between every two FPGAs is less, and under the condition that the number of interconnection signals is kept unchanged, the time division multiplexing rate is increased, so that the signal transmission delay is increased, and the main frequency is reduced. One solution has been to limit the number of FPGAs directly connected to a single FPGA to ensure the number of channels physically connected between FPGAs, and to the case where there is a communication requirement for logic between two FPGAs and no physical connection channel between two FPGAs, a multi-hop transmission is used. Although the method can solve the problem of reduction of the number of physical channels, as the signals can be transmitted to the target FPGA only by multiple hops, the signal delay is increased, and finally the main frequency of the FPGA is reduced, so that the simulation performance is reduced. Therefore, the traditional time division multiplexing mode also limits the scale expansion of the multi-FPGA prototype verification system.
Disclosure of Invention
Aiming at the technical problems, the invention provides a hardware architecture of a multi-FPGA prototype verification platform of a multi-mode hybrid interconnection architecture.
The technical scheme adopted for solving the technical problems is as follows:
a multi-FPGA prototype verification platform hardware architecture of a multi-mode hybrid interconnection architecture comprises a high-speed switching network, a plurality of circuit board cards and a plurality of high-speed serial transceivers, wherein a plurality of FPGAs are placed in each circuit board card, the FPGAs in the same circuit board card are directly connected in a board by utilizing LVDS interfaces, the FPGAs among different circuit board cards are connected with the plurality of high-speed serial transceivers through the high-speed switching network, and the FPGAs in the same circuit board card are not directly connected in a board by the high-speed switching network and the high-speed serial transceivers.
Preferably, the FPGAs between different circuit board cards are connected with the multipath high-speed serial transceiver through a high-speed switching network, comprising:
the FPGA of one circuit board card is connected to the high-speed switching network through different paths of high-speed serial transceivers respectively, and then connected to the FPGA of the other circuit board card through different paths of high-speed serial transceivers.
Preferably, a plurality of FPGAs in the same circuit board card are not directly connected in the board through a high-speed switching network and a high-speed serial transceiver, including:
any FPGA of the same circuit board card is connected to the high-speed switching network through the corresponding high-speed serial transceiver, and then is connected to other FPGAs of the same circuit board card through other high-speed serial transceivers of different paths.
Preferably, the high-speed serial transceiver includes at least one of a GTH port, a GTX port, a GTY port, a GTP port, a GTZ port, and a GTM port.
Preferably, the FPGAs between different circuit board cards can also be directly connected by cables through reserved ports based on LVDS.
Preferably, the implementation of the high-speed switching network includes message switching or point-to-point direct communication.
Preferably, the peripheral interface is accessible to the hardware architecture through a high-speed switching network, wherein the peripheral interface comprises at least one of an I2C interface, a UART interface, an SPI interface, a QSPI interface, a JTAG interface, and a GPIO interface.
Compared with the prior art, the hardware architecture of the multi-FPGA prototype verification platform of the multi-mode hybrid interconnection architecture has the following specific advantages:
(1) The flexibility and the expandability of the platform are enhanced, when the capacity of the system is required to be expanded, the newly added part can be connected through the optical fiber and the high-speed switching network, and the newly added equipment is connected into the high-speed switching network to realize without adjusting and modifying the existing system;
(2) Compared with LVDS ports based on a TDM mode, the bandwidth of a high-speed switching network based on GTH or other high-speed transceivers is increased by hundreds of thousands of times, so that the simulation performance is improved;
(3) Based on the LVDS ports of TDM, more FPGA pins are needed, so compared with the traditional platform, the platform has the advantages that the interconnection bandwidth between FPGAs is increased, and meanwhile, the pin resources of the FPGAs are saved;
(4) The platform naturally supports cloud processing, and can change the network communication state of a high-speed communication port between the FPGAs through the route reconstruction of a high-speed switching network, so that the division and adjustment of FPGA resources and bandwidth resources are realized.
Drawings
FIG. 1 is a schematic diagram of an exemplary architecture of a multi-FPGA hardware simulation platform according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of an exemplary architecture of a multi-FPGA hardware simulation platform provided in another embodiment of the present invention.
Detailed Description
In order to make the technical scheme of the present invention better understood by those skilled in the art, the present invention will be further described in detail with reference to the accompanying drawings.
In one embodiment, a hardware architecture of a multi-FPGA prototype verification platform of a multi-mode hybrid interconnection architecture comprises a high-speed switching network, a plurality of circuit board cards and a plurality of high-speed serial transceivers, wherein a plurality of FPGAs are placed in each circuit board card, the FPGAs in the same circuit board card are directly connected in the board by utilizing an LVDS interface, the FPGAs between different circuit board cards are connected with the plurality of high-speed serial transceivers through the high-speed switching network, and the FPGAs in the same circuit board card are not directly connected in the board through the high-speed switching network and the high-speed serial transceivers.
In one embodiment, the FPGA between different circuit board cards is connected to the multi-way high-speed serial transceiver through a high-speed switching network, comprising:
the FPGA (Field Programmable Gate Array ) of one circuit board card is connected to the high-speed switching network through different paths of high-speed serial transceivers respectively, and then connected to the FPGA of the other circuit board card through different paths of high-speed serial transceivers.
In one embodiment, a plurality of FPGAs in the same circuit board card are in-board non-direct connection through a high-speed switching network and a high-speed serial transceiver, comprising:
any FPGA of the same circuit board card is connected to the high-speed switching network through the corresponding high-speed serial transceiver, and then is connected to other FPGAs of the same circuit board card through other high-speed serial transceivers of different paths.
In one embodiment, the high speed serial transceiver includes at least one of a GTH port, a GTX port, a GTY port, a GTP port, a GTZ port, and a GTM port.
Specifically, GTH, GTX, GTY, GTP, GTZ, GTM port: GT, gigabyte Transceiver, G-bit transceivers, commonly referred to as Serdes, high speed transceivers, GT, etc. GTH, GTX, GTY, GTP, GTZ, GTM is different high-speed serial transceivers developed according to different processes and requirements in each series of FPGA of Xilinx, and the supported highest linear speed is ordered as GTP < GTX < GTH < GTZ < GTY < GTM.
In one embodiment, the FPGAs between different circuit board cards may also be directly connected by cables through reserved LVDS-based ports.
In particular, LVDS (Low-Voltage Differential Signaling, low voltage differential signaling) is a differential signaling technology with Low power consumption, low bit error rate, low crosstalk, and Low radiation. The FPGAs of the multi-FPGA hardware simulation platform can be connected through LVDS ports, and can also be connected to a switching network through a GTH or other high-speed serial transceivers for interconnection. Further, for delay sensitive signals, it is proposed to communicate by means of time division multiplexing through LVDS ports. While insensitive to delay, but with high communication bandwidth requirements, it is recommended to communicate in a message exchange via a GTH or other high speed serial transceiver.
In this embodiment, the hardware simulation platform system uses a circuit board card as a unit, a plurality of FPGAs are placed in a single circuit board card, and the FPGAs are directly connected in a board by using an LVDS interface. Meanwhile, the FPGA between the circuit board cards can be connected through high-speed exchange interconnection, and also can be directly connected through reserved ports based on LVDS by using cables.
One embodiment is illustrated in fig. 1 below, taking a GTH or other high speed serial transceiver based high speed switching network as an example.
And 4 FPGAs are placed on a single circuit board card, every two FPGAs are directly connected through an LVDS interface, and meanwhile, each FPGA is connected into a high-speed switching network through a plurality of GTH or other high-speed serial transceiver ports to be interconnected with FPGAs on other circuit board cards. Meanwhile, the FPGAs in the single circuit board card are also interconnected through a high-speed switching network.
In one embodiment, the implementation of the high speed switching network includes message switching or point-to-point direct communication.
In one embodiment, the peripheral interface is accessible to the hardware architecture via a high-speed switching network, wherein the peripheral interface includes at least one of an I2C interface, a UART interface, an SPI interface, a QSPI interface, a JTAG interface, and a GPIO interface.
Further, the implementation manner of the high-speed switching network comprises a plurality of switching manners such as message switching or point-to-point direct connection communication. Meanwhile, the peripheral interface can be accessed into the system through a switching network, and the peripheral interface comprises: I2C, UART, SPI, QSPI, JTAG, GPIO, etc., to realize the user's need for different peripheral interfaces during prototype verification. The I2C bus is a simple, bi-directional two-wire synchronous serial bus developed by Philips corporation. It requires only two wires to transfer information between devices connected to the bus. UART (Universal Asynchronous Receiver/Transmitter ) is a universal serial data bus for asynchronous communications that communicates bi-directionally, enabling full duplex transmission and reception. SPI (Serial Peripheral Interface ), is a high-speed, full duplex, synchronous communications bus. QSPI: the queue SPI is an extension of an SPI interface which is proposed by a Motorola company, the Motorola company enhances the functions of the SPI interface on the basis of an SPI protocol, a queue transmission mechanism is increased, and a queue serial peripheral interface protocol (namely QSPI protocol) is proposed, and is generally used for connecting single, double or four (data lines) SPI Flash storage media. JTAG (Joint Test Action Group ), is an International Standard test protocol (IEEE 1149.1 compliant) and is used primarily for on-chip testing. Most advanced devices now support the JTAG protocol, such as DSP, FPGA devices, etc. The standard JTAG interface is 4 lines: TMS, TCK, TDI, TDO, respectively, mode select, clock, data input and data output lines. GPIO (General purpose input/output), P0-P3 with a function similar to 8051, can be used by a user freely by program control, and the PIN can be used as General Purpose Input (GPI) or General Purpose Output (GPO) or General Purpose Input and Output (GPIO) according to practical considerations, such as clk generator, chip select, etc.
Furthermore, the division and adjustment of FPGA resources and bandwidth resources can be realized by reconstructing the routes of the high-speed switching network, changing the network communication state of GTH or other high-speed serial transceiver ports between FPGAs, for example: the resource pool is provided with 12 FPGAs, and 4 FPGAs in the 12 FPGAs can be divided into A groups for A users to use through route configuration. The remaining 8 FPGAs are divided into B groups for use by B users. And no communication exists between the FPGA used by the users in the group A and the group B, so that 2 independent FPGA verification environments are formed. The FPGA resources can be freely combined through route configuration according to the demands of users on the resources.
Specifically, compared with the traditional multi-FPGA hardware simulation platform, the innovation point is that communication interconnection based on a high-speed switching network is added between FPGAs, and various architectures can be realized by changing the connection between the in-board LVDS and the high-speed serial transceiver between boards, as shown in fig. 2.
Compared with the prior art, the hardware architecture of the multi-FPGA prototype verification platform of the multi-mode hybrid interconnection architecture has the following specific advantages:
(1) The flexibility and the expandability of the platform are enhanced, when the capacity of the system is required to be expanded, the newly added part can be connected through the optical fiber and the high-speed switching network, and the newly added equipment is connected into the high-speed switching network to realize without adjusting and modifying the existing system;
(2) Compared with LVDS ports based on a TDM mode, the bandwidth of a high-speed switching network based on GTH or other high-speed transceivers is increased by hundreds of thousands of times, so that the simulation performance is improved;
(3) Based on the LVDS ports of TDM, more FPGA pins are needed, so compared with the traditional platform, the platform has the advantages that the interconnection bandwidth between FPGAs is increased, and meanwhile, the pin resources of the FPGAs are saved;
(4) The platform is naturally suitable for cloud processing, and can change the network communication state of the GTH between the FPGAs through the route reconstruction of the high-speed switching network, so that the division and adjustment of FPGA resources and bandwidth resources are realized.
The multi-FPGA prototype verification platform hardware architecture of the multi-mode hybrid interconnection architecture provided by the invention is described in detail above. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the core concepts of the invention. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (7)
1. The hardware architecture of the multi-FPGA prototype verification platform of the multi-mode hybrid interconnection architecture is characterized by comprising a high-speed switching network, a plurality of circuit board cards and a plurality of high-speed serial transceivers, wherein a plurality of FPGAs are placed in each circuit board card, the FPGAs in the same circuit board card are directly connected in a board by utilizing an LVDS interface, the FPGAs between different circuit board cards are connected with the plurality of high-speed serial transceivers through the high-speed switching network, and the FPGAs in the same circuit board card are not directly connected in a board through the high-speed switching network and the high-speed serial transceivers.
2. The hardware architecture of claim 1 wherein the FPGAs between the different circuit board cards are connected through the high speed switching network and the multiple high speed serial transceivers, comprising:
the FPGA of one circuit board card is connected to the high-speed switching network through different paths of high-speed serial transceivers respectively, and then connected to the FPGA of the other circuit board card through different paths of high-speed serial transceivers.
3. The hardware architecture of claim 2 wherein the plurality of FPGAs within the same circuit board card are not directly connected on-board through the high speed switching network and the high speed serial transceiver, comprising:
any FPGA of the same circuit board card is connected to the high-speed switching network through a corresponding high-speed serial transceiver, and then is connected to other FPGAs of the same circuit board card through other high-speed serial transceivers of different paths.
4. The hardware architecture of claim 3 wherein the high speed serial transceiver comprises at least one of a GTH port, a GTX port, a GTY port, a GTP port, a GTZ port, and a GTM port.
5. The hardware architecture of claim 4 wherein FPGAs between different circuit board cards can also be directly connected by cables through reserved LVDS-based ports.
6. The hardware architecture of claim 5, wherein the implementation of the high-speed switching network comprises message switching or point-to-point direct communication.
7. The hardware architecture of claim 6 wherein a peripheral interface is accessible to the hardware architecture through the high speed switching network, wherein the peripheral interface comprises at least one of an I2C interface, a UART interface, an SPI interface, a QSPI interface, a JTAG interface, and a GPIO interface.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117272892A (en) * | 2023-11-21 | 2023-12-22 | 芯瞳半导体技术(山东)有限公司 | Circuit verification method and device, storage medium and electronic equipment |
| CN118690695A (en) * | 2024-08-23 | 2024-09-24 | 湖南泛联新安信息科技有限公司 | A multi-FPGA simulation verification method and system for network-centric architecture |
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- 2023-04-17 CN CN202310403569.1A patent/CN116578528A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117272892A (en) * | 2023-11-21 | 2023-12-22 | 芯瞳半导体技术(山东)有限公司 | Circuit verification method and device, storage medium and electronic equipment |
| CN117272892B (en) * | 2023-11-21 | 2024-03-26 | 芯瞳半导体技术(山东)有限公司 | Circuit verification method, device, storage medium and electronic equipment |
| CN118690695A (en) * | 2024-08-23 | 2024-09-24 | 湖南泛联新安信息科技有限公司 | A multi-FPGA simulation verification method and system for network-centric architecture |
| CN118690695B (en) * | 2024-08-23 | 2024-11-19 | 湖南泛联新安信息科技有限公司 | Multi-FPGA simulation verification method and system for network center architecture |
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