CN116845109A - Electrostatic doped tunneling field effect transistor - Google Patents

Abstract

The invention provides an electrostatic field doped tunneling field effect transistor, which is characterized in that different metal materials are deposited on oxide layers on a source region and a drain region to form a bias electrode, a certain bias voltage is applied, a large number of electrons or holes are induced in the source region and the drain region by utilizing an electrode bias principle, N-type or P-type doping is formed, and the on-off of a device channel is controlled by utilizing a double-gate structure. In the on state, a very narrow N is formed between the source region and the channel region of the device ⁺ In the pocket region, the tunneling barrier width is reduced and the on-current is increased. A P-type gap is formed between the drain region and the channel region of the device in the off state, and the potential barrier width near the drain region can be adjusted by changing the length of the gap, so that the purpose of reducing bipolar current is achieved.

Description

An electrostatically doped tunneling field effect transistor

Technical field

The invention belongs to the technical field of nanoelectronics and relates to an electrostatic field doped tunneling field effect transistor.

Background technique

As the size of MOSFETs continues to decrease, energy consumption issues have also become an important factor restricting the size reduction of MOSFETs. According to semiconductor physics knowledge, the minimum value of the MOSFET's subthreshold swing (SS) is 60mV/dec. One of the most effective solutions for reducing integrated circuit power consumption is to reduce the supply voltage. However, the sub-threshold slope has a minimum value, which determines that when the power supply voltage drops, the difference between the turn-on current and the turn-off current will also decrease accordingly. When the transistor is in the on state, the current value should not be too small, so the turn-on current should not be reduced as much as possible. This means that as the power supply voltage decreases, the turn-off current of the device will increase accordingly, which will greatly increase the static power of the circuit. Consumption. In order to solve this problem, tunnel field effect transistor (TFET) is widely used.

TFET breaks the constraints of the sub-threshold slope of traditional MOSFET. When the power supply voltage decreases, the off-current can still be maintained at a low level. However, it also has some shortcomings. The most important shortcoming is that because carriers rely on the tunneling effect to tunnel between energy bands, the on-current is significantly reduced compared with MOSFET. In addition, taking N-type TFET as an example, when a negative gate voltage is applied, the barrier width between the drain region and the channel region is small, and tunneling can also occur, forming a bipolar current. Therefore, how to increase the on-current of TFET devices while reducing their bipolar current is an urgent problem that needs to be solved.

Contents of the invention

The purpose of the present invention is to solve the problem in the prior art of increasing the on-current of a tunneling field effect transistor device while reducing its bipolar current, and to provide an electrostatic field doped tunneling field effect transistor.

In order to achieve the above objectives, the present invention adopts the following technical solutions to achieve:

An electrostatic field doped tunneling field effect transistor includes a P-type heavily doped source region, an N-type heavily doped pocket region, a P-type lightly doped channel region and an N-type heavily doped drain region arranged laterally;

Above and below the P-type heavily doped source region are a top first polarity gate oxide layer and a bottom first polarity gate oxide layer, and above the top first polarity gate oxide layer is the top A first polarity gate electrode, below the bottom first polarity gate oxide layer is a bottom first polarity gate electrode, and a source electrode contact region is provided on the side of the P-type heavily doped source region;

Above and below the P-type lightly doped channel region are a top control gate oxide layer and a bottom control gate oxide layer respectively. Above the top control gate oxide layer is a top control gate electrode, and the bottom control gate oxide layer is Below the gate oxide layer is the bottom control gate electrode;

Above and below the N-type heavily doped drain region are a top second polarity gate oxide layer and a bottom second polarity gate oxide layer respectively, and above the top second polarity gate oxide layer is the top A second polarity gate electrode. Below the bottom second polarity gate oxide layer is a bottom second polarity gate electrode, and a drain electrode contact region is provided on the side of the N-type heavily doped drain region.

Further improvements of the present invention are:

The top first polarity gate oxide layer and the bottom first polarity gate oxide layer have the same thickness and are made of the same material.

The top second polarity gate oxide layer and the bottom second polarity gate oxide layer have the same thickness and are made of the same material.

The top first polarity gate electrode and the bottom first polarity gate electrode have the same work function, and the top second polarity gate electrode and the bottom second polarity gate electrode have the same work function.

The N-type heavily doped pocket region has a doping concentration of 4×10 ¹⁹ cm ^-3 and a length of 1 nm to 9 nm.

The doping concentration of the P-type lightly doped channel region is 1×10 ¹⁷ cm ^-3 .

Above and below the N-type heavily doped pocket region are the top sidewalls of the source region-channel region and the bottom sidewalls of the source region-channel region; the top side of the P-type lightly doped channel region is close to the N-type A drain region-channel region top spacer is provided on one side of the heavily doped drain region, and a drain region-channel region bottom is provided below the P-type lightly doped channel region and close to the N-type heavily doped drain region. side walls.

The length of the sidewalls at the top of the drain region and the channel region is 5 nm to 30 nm; the length of the sidewalls at the bottom of the drain region and the channel region is 5 nm and 30 nm.

The source electrode contact area and the drain electrode contact area are both made of nickel silicide, and their Schottky barrier height is 0.45 eV.

The field effect transistor has a symmetrical structure above and below the central axis along the horizontal direction.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention proposes an electrostatic field doped tunneling field effect transistor, which forms bias electrodes by depositing different metal materials on the oxide layers on the source and drain regions, and applies a certain bias voltage. Based on the setting principle, a large number of electrons or holes are induced in the source and drain regions to form N-type or P-type doping, and the double-gate structure is used to control the opening and closing of the device channel. In the on state, an extremely narrow N ⁺ pocket region is formed between the source region and the channel region of the device, the tunnel barrier width decreases, and the conduction current increases. In the off state, a P-type gap is formed between the drain region and the channel region of the device. By changing the length of this gap, the barrier width near the drain region can be adjusted to reduce the bipolar current.

Description of the drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and therefore do not It should be regarded as a limitation of the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of the final structure of the electrostatically doped tunneling field effect transistor of the present invention;

Figure 2 is a schematic diagram of the initial structure of the electrostatically doped tunneling field effect transistor of the present invention.

Among them: 1-P-type lightly doped channel region, 2-N-type heavily doped pocket region, 3a-top control gate oxide layer, 3b-bottom control gate oxide layer, 3c-top first polarity gate Oxide layer, 3d-bottom first polarity gate oxide layer, 3e-top second polarity gate oxide layer, 3f-bottom second polarity gate oxide layer, 4a-top control gate electrode, 4b-bottom control Gate electrode, 5a-top first polarity gate electrode, 5b-bottom first polarity gate electrode, 6a-top second polarity gate electrode, 6b-bottom second polarity gate electrode, 7-P type heavily doped Source region, 8-N-type heavily doped drain region, 9a-source electrode contact region, 9b-drain electrode contact region, 10a-source region-top sidewall of channel region, 10b-source region-bottom sidewall of channel region , 11a-drain region-top sidewall of the channel region, 11b-drain region-bottom sidewall of the channel region, 12-P-type lightly doped channel and drain region, 13-N-type heavily doped source region.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, rather than all embodiments. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Therefore, the following detailed description of the embodiments of the invention provided in the appended drawings is not intended to limit the scope of the claimed invention, but rather to represent selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

It should be noted that similar reference numerals and letters represent similar items in the following figures, therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures.

In the description of the embodiments of the present invention, it should be noted that if the terms “upper”, “lower”, “horizontal”, “inner”, etc. appear to indicate an orientation or positional relationship, they are based on the orientation or positional relationship shown in the drawings. , or the orientation or positional relationship in which the product of the invention is usually placed when used, is only for the convenience of describing the invention and simplifying the description, and does not indicate or imply that the device or component referred to must have a specific orientation or be constructed in a specific orientation. and operation, and therefore cannot be construed as limitations of the present invention. In addition, the terms "first", "second", etc. are only used to differentiate descriptions and are not to be understood as indicating or implying relative importance.

In addition, if the term "level" appears, it does not mean that the component is required to be absolutely horizontal, but may be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical". It does not mean that the structure must be completely horizontal, but can be slightly tilted.

In the description of the embodiments of the present invention, it should also be noted that, unless otherwise clearly stated and limited, the terms "setting", "installation", "connecting" and "connecting" should be understood in a broad sense. For example, they can It can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or it can be an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

The present invention proposes an electrostatically doped tunneling field effect transistor based on the principle of polarity bias. The bias electrode is formed by depositing different metal materials on the oxide layer on the source and drain regions, and a certain bias is applied. Set voltage, use the electrode bias principle to induce a large number of electrons or holes in the source and drain regions, forming N-type or P-type doping, and use the double-gate structure to control the opening and closing of the device channel. Taking the N-type TFET device as an example, when it is turned on, an extremely narrow N ⁺ pocket region is formed between the source region and the channel region of the device. The width of the tunnel barrier decreases and the conduction current increases. In the off state, a P-type gap is formed between the drain region and the channel region of the device. By changing the length of this gap, the barrier width near the drain region can be adjusted to reduce the bipolar current.

The present invention will be described in further detail below in conjunction with the accompanying drawings:

Refer to Figure 1, which is a schematic diagram of the final structure of the electrostatically doped tunneling field effect transistor in the present invention. The field effect transistor includes a P-type heavily doped source region 7, an N-type heavily doped pocket region 2, and a P-type lightly doped source region arranged laterally. Impurity channel region 1 and N-type heavily doped drain region 8; above and below the P-type heavily doped source region 7 are the top first polarity gate oxide layer 3c and the bottom first polarity gate oxide layer 3c, respectively. Layer 3d, the top first polar gate oxide layer 3c and the bottom first polar gate oxide layer 3d have the same thickness and are made of the same material, the top first polar gate oxide layer 3c Above is the top first polarity gate electrode 5a, below the bottom first polarity gate oxide layer 3d is the bottom first polarity gate electrode 5b, the top first polarity gate electrode 5a and the bottom first polarity gate electrode 5b The polar gate electrode 5b has the same work function, and a source electrode contact region 9a is provided on the side of the P-type heavily doped source region 7. The source electrode contact region 9a is composed of nickel silicide, and its Schottky barrier height is 0.45eV. ; Above and below the P-type lightly doped channel region 1 are the top control gate oxide layer 3a and the bottom control gate oxide layer 3b respectively. The doping concentration of the P-type lightly doped channel region 1 is 1× 10 ¹⁷ cm ^-3 , a drain region-channel top spacer 11a is provided above the P-type lightly doped channel region 1 and close to the side of the N-type heavily doped drain region 8. The drain region-channel region The length of the spacer 11a at the top of the region is 5nm~30nm. A drain region-channel region bottom spacer 11b is provided below the P-type lightly doped channel region 1 and close to the side of the N-type heavily doped drain region 8, so The length of the sidewall 11b at the bottom of the drain region-channel region is 5 nm to 30 nm; above the top control gate oxide layer 3a is the top control gate electrode 4a, and below the bottom control gate oxide layer 3b is the bottom control gate electrode 4a. Gate electrode 4b; above and below the N-type heavily doped drain region 8 are a top second polarity gate oxide layer 3e and a bottom second polarity gate oxide layer 3f respectively. The top second polarity gate The polar oxide layer 3e and the bottom second polarity gate oxide layer 3f have the same thickness and are made of the same material. Above the top second polarity gate oxide layer 3e is the top second polarity gate electrode 6a , below the bottom second polarity gate oxide layer 3f is the bottom second polarity gate electrode 6b, the top second polarity gate electrode 6a and the bottom second polarity gate electrode 6b have the same work function, A drain electrode contact region 9b is provided on the side of the N-type heavily doped drain region 8. The drain electrode contact region 9b is made of nickel silicide and has a Schottky barrier height of 0.45 eV. The N-type heavily doped pocket region 2 has a doping concentration of 4×10 ¹⁹ cm ^-3 and a length of 1 nm to 9 nm. The top and bottom of the N-type heavily doped pocket region 2 are the source region and the top of the channel region respectively. Sidewalls 10a and source area-channel area bottom sidewalls 10b.

Refer to Figure 2, which is a schematic diagram of the initial structure of the electrostatically doped tunneling field effect transistor in the present invention. The initial structure includes a lateral N-type heavily doped source region 13 and a P-type lightly doped channel and drain region 12. According to the polarity bias principle, when a certain negative bias voltage is applied to the top first polarity gate electrode 5a and the bottom first polarity gate electrode 5b, a large number of holes are induced in part of the source region below them, forming a P-type heavily doped Impurity source area 7. When a certain forward bias voltage is applied between the top second polarity gate electrode 6a and the bottom second polarity gate electrode 6b, a large number of electrons are induced in a part of the drain region below, forming an N-type heavily doped drain region 8. The P-type heavily doped source region and the N-type heavily doped drain region are both formed by electrostatic doping, without the need for traditional chemical doping steps such as ion implantation, and a standard PN junction can be realized within a range of several nanometers.

The specific working principle of the electrostatically doped tunneling field effect transistor in the present invention is:

1. When in the on state, the field effect transistor forms a PNPN structure, and the conduction current increases.

For N-type tunneling field effect transistors, the work function of the first polarity gate electrode is small (<4.33eV), and when a large enough negative voltage (<-0.7V) is applied, according to the polar bias principle, the A large number of holes will be induced in part of the source region below, forming a P-type heavily doped region. Therefore, the N-type heavily doped source region of the initial structure is replaced by a P-type heavily doped source region and an N-type heavily doped pocket region. At the same time, the work function of the second polarity gate electrode is also small (<4.5eV), and when a large enough positive voltage (>0.7V) is applied, according to the polarity bias principle, part of the drain area below it will sense A large number of electrons are generated to form an N-type heavily doped region. Therefore, the P-type lightly doped region of the initial structure is replaced by the P-type lightly doped channel and the N-type heavily doped drain region. In summary, the field effect transistor forms a PNPN structure. The characteristics of this structure are: in the on state, The N-type heavily doped pocket part between the source region and the channel will introduce a local minimum point in the energy band, causing the tunneling barrier width to decrease rapidly and the tunneling probability of carriers to greatly increase. Therefore, the conduction The current flow also increases.

2. In the off state, the bipolar current decreases.

For N-type devices, when a large enough negative voltage (<-0.7V) is applied to the control gate electrode, the energy band of the channel is raised. When the valence band of the channel is higher than the conduction band of the drain region, the carriers The interband tunneling effect may occur between the channel and the drain region, and the bipolar current increases. Moreover, the probability of carrier tunneling is inversely proportional to the tunneling barrier width near the drain region. The greater the tunneling barrier width, the smaller the tunneling probability and the smaller the bipolar current. Since an increase in bipolar current will seriously reduce the performance of the TFET device, the gap length L between the drain region and the channel can be increased by reducing the length of the second polarity gate electrode while the total length of the device remains unchanged. _gap , further reducing the bipolar current. Therefore, the tunneling barrier width near the drain region of the device is controllable.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims (10)

1. The electrostatic field doped tunneling field effect transistor is characterized by comprising a P-type heavy doped source region (7), an N-type heavy doped pocket region (2), a P-type light doped channel region (1) and an N-type heavy doped drain region (8) which are transversely and sequentially arranged;

the top and the bottom of the P-type heavily doped source region (7) are respectively a top first polar gate oxide layer (3 c) and a bottom first polar gate oxide layer (3 d), the top of the top first polar gate oxide layer (3 c) is a top first polar gate electrode (5 a), the bottom of the bottom first polar gate oxide layer (3 d) is a bottom first polar gate electrode (5 b), and a source electrode contact region (9 a) is arranged on the side surface of the P-type heavily doped source region (7);

the upper part and the lower part of the P-type lightly doped channel region (1) are respectively a top control gate oxide layer (3 a) and a bottom control gate oxide layer (3 b), a top control gate electrode (4 a) is arranged above the top control gate oxide layer (3 a), and a bottom control gate electrode (4 b) is arranged below the bottom control gate oxide layer (3 b);

the top and the bottom of the N-type heavily doped drain region (8) are respectively a top second polar gate oxide layer (3 e) and a bottom second polar gate oxide layer (3 f), the top of the top second polar gate oxide layer (3 e) is a top second polar gate electrode (6 a), the bottom of the bottom second polar gate oxide layer (3 f) is a bottom second polar gate electrode (6 b), and a drain electrode contact region (9 b) is arranged on the side face of the N-type heavily doped drain region (8).

2. An electrostatic field doped tunneling field effect transistor according to claim 1, characterized in that said top (3 c) and bottom (3 d) first polar gate oxide layers are of the same thickness and made of the same material.

3. An electrostatic field doped tunneling field effect transistor according to claim 1, characterized in that said top (3 e) and bottom (3 f) second polar gate oxide layers are of the same thickness and made of the same material.

4. An electrostatic field doped tunneling field effect transistor according to claim 1, characterized in that said top first polarity gate electrode (5 a) and bottom first polarity gate electrode (5 b) have the same work function, and said top second polarity gate electrode (6 a) and bottom second polarity gate electrode (6 b) have the same work function.

5. The electrostatic field doped tunneling field effect transistor according to claim 1, wherein said N-type heavy materialThe doping concentration of the doped pocket region (2) is 4 multiplied by 10 ¹⁹ cm ^-3 The length is 1 nm-9 nm.

6. An electrostatic field doped tunneling field effect transistor according to claim 1, wherein said P-type lightly doped channel region (1) has a doping concentration of 1 x 10 ¹⁷ cm ^-3 。

7. An electrostatic field doped tunneling field effect transistor according to claim 1, wherein the top and bottom of said N-type heavily doped pocket region (2) are a source-channel region top sidewall (10 a) and a source-channel region bottom sidewall (10 b), respectively; a drain region-channel region top side wall (11 a) is arranged on one side, close to the N-type heavily doped drain region (8), of the upper side of the P-type lightly doped channel region (1), and a drain region-channel region bottom side wall (11 b) is arranged on one side, close to the N-type heavily doped drain region (8), of the lower side of the P-type lightly doped channel region (1).

8. An electrostatic field doped tunneling field effect transistor according to claim 7, wherein said drain-channel region top sidewall (11 a) has a length of 5nm to 30nm; the length of the drain region-channel region bottom side wall (11 b) is 5 nm-30 nm.

9. An electrostatic field doped tunneling field effect transistor according to claim 1, characterized in that said source electrode contact region (9 a) and drain electrode contact region (9 b) are each comprised of nickel silicide with a schottky barrier height of 0.45eV.

10. An electrostatic field doped tunneling field effect transistor according to claim 1 wherein said field effect transistor has a central axis in a horizontal direction and has a symmetrical structure in two parts above and below said central axis.