CN110797408A - A Dynamic Threshold Tunneling Field Effect Double Gate Device - Google Patents

Abstract

The invention discloses a dynamic threshold tunneling field effect double gate device. It consists of a control gate electrode, an independent bias gate electrode, a source region, a drain region, a channel region and a control gate dielectric layer; wherein, the independent bias gate electrode is located at the bottom of the threshold tunneling field effect double gate device. Under the bias gate dielectric layer, the independent bias gate dielectric layer is isolated from the channel region; the source region and the drain region are respectively located on two sides of the channel region, and are isolated from the control gate by the control gate dielectric. The device involved in the invention can work independently under gate control conditions, provides a selection scheme for low power consumption circuit design, and has greater sensitivity to threshold voltage adjustment than traditional T-FinFET devices and SOI tunneling devices. Furthermore, its electrical performance is superior to conventional T‑FinFET devices and SOI tunneling devices. Through separate voltage modulation of independently biased gates, gate lengths can be reduced to 20 nanometers and below, while maintaining relatively ideal device performance.

Description

A Dynamic Threshold Tunneling Field Effect Double Gate Device

technical field

The invention relates to the field of semiconductor integrated circuit devices, in particular to a dynamic threshold tunneling field effect double gate device.

Background technique

As the size of integrated circuit devices continues to decrease in accordance with Moore's Law, metal oxide semiconductor field effect devices under the traditional planar bulk silicon process encounter development bottlenecks such as short channel effect and gate leakage current. For example, tunneling devices, impact ionization devices, negative capacitance devices, etc. continue to emerge. Among them, conventional tunneling field effect double-gate devices, also known as: T-FinFET, because of its excellent sub-threshold characteristics that break the sub-threshold limit of traditional FinFETs and very low leakage current, nano-T-FinFET is considered to have application potential in 10-5 nanometer integrated circuits.

The substrate bias of bulk silicon devices and the back gate bias of dual-gate devices can change the threshold voltage of the device. Such independent gate bias operation can control the threshold voltage through an external bias signal, so in the field of power management such as There are important applications in low-power memory circuits. In T-FinFET, an independent bias electrode is introduced for independent body potential adjustment, which can adjust parameters such as the threshold voltage of T-FinFET, improve various electrical characteristics of the device, and provide a variety of options and optimizations for applications. A dynamic threshold tunneling field effect double gate device (Dynamic Threshold Tunneling FinFET, abbreviated as DT T-FinFET). This scheme is suitable for SOI type T-FinFET, which can form bias electrode under the bottom oxide layer substrate.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a dynamic threshold tunneling field effect double gate device, which consists of a control gate electrode, an independently biased gate electrode, a source region, a drain region, a channel region, a control gate dielectric layer and an independently biased gate dielectric layer wherein, the independent bias gate electrode is located under the independent bias gate dielectric layer at the bottom of the threshold tunneling field effect dual gate device, and is separated from the channel region by a metal substrate and an independent bias gate dielectric layer ; the control gate electrode and the channel region are isolated by a control gate dielectric layer, and the control gate dielectric layer surrounds the channel region from three sides; the source region and the drain region are respectively located at two sides of the channel region terminal and is isolated from the control gate by the control gate dielectric layer.

Preferably, the material constituting the channel region is an undoped or lightly doped semiconductor material;

The material constituting the source region and the drain region is a semiconductor material with a doping concentration of 5×10 ¹⁸ cm-3 to 2×10 ²¹ cm-3, and the doping types are different, the former is P-doped, the latter is N Doping, or vice versa.

Preferably, the material constituting the channel region is a silicon material with a boron doping concentration of 1×10 ¹⁷ cm-3; the material constituting the source region is a silicon material with a phosphorus doping concentration of 1×10 ²⁰ cm-3 , the drain region material is silicon material with boron doping concentration of 5×10 ¹⁸ cm-3.

Preferably, the thickness of the independently biased gate electrode is 5-20 nanometers; the thickness of the independently biased gate dielectric layer is 1.2-20 nanometers; the thickness of the control gate electrode is 5-20 nanometers; the control The thickness of the gate dielectric layer is 1.2-2 nanometers; the width of the channel region is 3-10 nanometers, and the height is 3-50 nanometers.

The channel region of the above-mentioned dynamic threshold tunneling field effect double-gate device is an undoped or lightly doped semiconductor material, such as a silicon material with a boron doping concentration of 1×10 ¹⁷ cm ^-3 . The source region and the drain region are heavily doped semiconductor materials, such as silicon materials with boron doping and phosphorus doping concentrations of 1×10 ²⁰ cm ^-3 and 5×10 ¹⁸ cm ^-3 respectively. The material and work function of the control gate electrode are adjustable, or high dielectric constant materials and metal gate materials are used, and the thickness is also adjustable, generally controlled at more than 1-2 nanometers. The dielectric material and thickness of the bias dielectric layer can be adjusted. For example, if silicon oxide material is used, the thickness can be maintained at 1 to 20 nanometers. The height and width of the semiconductor material in the channel region can be adjusted according to the channel length and width of the device.

Beneficial effects: The dynamic threshold tunneling field effect double gate device provided by the present invention has two electrically independent gate electrodes: an independent bias gate electrode and a control gate electrode. Compared with the conventional tunneling field effect double-gate device (T-FinFET), the structure of the device allows different operating voltages to be applied on the independently biased gate electrode and the control gate electrode, so that the device can operate on an independent biased gate electrode. Provides convenience for circuit application and power consumption control of the device under certain conditions. When the dynamic threshold tunneling field effect dual-gate device (DT T-FinFET) works under the condition of independent bias gate control, the device doping and size parameters are not changed, and changing the bias voltage of the independent bias gate electrode will change the device's Current-voltage characteristics. For example, reducing the bias voltage of the independently biased gate electrode will increase the threshold voltage of the control gate and reduce the drive current of the entire device. This result provides an alternative for low-power circuit design such as memory cell circuit design. When the independently biased gate-controlled nano-dynamic threshold tunneling field effect double-gate device operates under the common gate condition, compared with the conventional tunneling double-gate device (T-FinFET) with the same structure, it can maintain the off-state When the current is similar, the on-state current is effectively increased, thereby improving the current switching ratio of the device and enhancing the driving capability of the device. The present invention provides an alternative for nano-DT T-FinFET performance optimization, circuit applications, etc. that allow bias gate electrode control.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a dynamic threshold tunneling field effect dual-gate device according to the present invention.

FIG. 2 shows the influence of the bias gate electrode on the drain current characteristic of a dynamic threshold tunneling field effect dual-gate device of the present invention.

FIG. 3 shows the relationship between the threshold voltage and the sub-threshold slope of a dynamic threshold tunneling field effect dual-gate device of the present invention, which are adjusted by the biased gate electrode.

FIG. 4 shows the relationship between the on-state current, the off-state current and the current switching ratio being adjusted by the bias electrode of a dynamic threshold tunneling field effect dual-gate device of the present invention.

FIG. 5 shows the adjustment relationship between the maximum transconductance and the drain-induced barrier lowering effect of a dynamic threshold tunneling field effect dual-gate device of the present invention by the bias electrode.

6 is a comparison of the drain current characteristics of a dynamic threshold tunneling field effect dual-gate device of the present invention under common gate operation and a corresponding conventional dual-gate tunneling device.

FIG. 7 is the drift relationship between the threshold voltage and the sub-threshold slope with the channel length of a dynamic threshold tunneling field effect dual-gate device under common gate operation according to the present invention.

FIG. 8 shows the relationship between on-state current, off-state current and current switching ratio with channel length under common gate operation of a dynamic threshold tunneling field effect dual-gate device of the present invention.

FIG. 9 shows the relationship between the maximum transconductance and the drain-induced barrier reduction effect with the channel length of a dynamic threshold tunneling field effect dual-gate device under common gate operation according to the present invention.

In the figure: 1- control gate electrode, 2- source electrode, 3- drain electrode, 4- independent bias gate dielectric layer, 5- control gate dielectric layer, 6- bias gate electrode.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings:

Referring to FIG. 1 , in this embodiment, the nano-dynamic threshold tunneling field effect dual-gate device controlled by the bias gate consists of an independent bias gate electrode 6 , a control gate electrode 1 , a bias gate dielectric layer 4 , The control gate dielectric layer 5, the channel region surrounded by the control gate dielectric layer 5, the source electrode 2 and the drain electrode 3 are composed. The source electrode region is called the source region, the drain electrode region is called the drain region, the control gate electrode completely surrounds the channel region of the device, and the independent bias gate electrode is drawn out through the metal part of the substrate.

In the first embodiment, both ends of the channel region are source regions and drain regions of different materials; the channel region is low-doped.

In the second embodiment, the two ends of the channel region are the source region and the drain region of the same material; wherein: the source region is a P-type heavily doped silicon material, the drain region is an N-type doped silicon material, and the channel is N-type lightly doped silicon material.

The device is prepared according to the existing method, and the preparation process is as follows:

a) LOCOS isolation with a silicon nitride hard mask on a silicon wafer;

b) depositing Si3N4/Poly-Si as a hard mask for silicon Fin;

c) Photolithography defines and etches the silicon Fin strips;

d) Forming 70nm thick SiO2 sidewalls,

e) Implant arsenic in the source and drain regions;

f) After removing the sidewall, the width of the trench is defined by photolithography, that is, the gate length of the device;

g) etching the initially formed Si3N4 and SiO2, and then etching silicon to form silicon Fin bodies and trenches;

h) After forming the Si3N4 sidewall, continue to etch the silicon to expose the silicon at the bottom of the Fin channel. The purpose of this operation is to facilitate subsequent oxidation;

i) The bottom of the Fin channel is then completely oxidized, thereby forming a biased gate dielectric layer structure;

j) After removing Si3N4, perform 20nm sacrificial oxidation to improve the interface damage of etching;

k) Then grow 4nm gate oxide, and photolithographically etch to form a polysilicon gate;

l) The standard CMOS process completes the preparation of contact holes and metal electrodes;

m) Fabrication of a nano-tunneling field effect double-gate device controlled by a bias gate.

The present invention will be further described below in conjunction with specific embodiments, but the present invention is not limited to the following embodiments.

Example 1:

The structure of the dynamic threshold nano-tunneling field effect dual-gate device is shown in Figure 1, in which the work function of the independently biased gate electrode and the control gate electrode material is set to 4.1 electron volts; the thickness of the independently biased gate dielectric layer is 15 nm The control gate dielectric layer is a silicon oxide layer with a thickness of 1.5 nanometers; the channel region is a silicon material with a boron doping concentration of 1×10 ¹⁷ cm ^-3 , with a width of 5 nanometers and a height of 20 nanometers; the source region is The silicon material with phosphorus doping concentration is 1×10 ²⁰ cm ^-3 ; the drain region is silicon material with phosphorus doping concentration 5×10 ¹⁸ cm ^-3 ; the lengths of source and drain regions of the device are both 30 nanometers.

The performance of the dynamic threshold nano-tunneling field effect dual-gate device with a gate length of 40 nanometers under independent bias gate control and dual gate control is compared and analyzed, and the results are shown in Figure 2-6.

Referring to Figure 2, increasing the bias voltage of the independently biased gate electrode will reduce the threshold voltage of the control gate and increase the on-state current of the device. On-state current, the subthreshold slope of the device degrades. Reducing the voltage of the independent bias gate electrode to the point where the gate electrode of the independent bias is biased under the condition of zero bias voltage or even negative bias voltage can increase the threshold voltage of the control gate, and reduce the on-state current to minimum value. For example, when the voltage of the independently biased gate electrode is reduced from 0.6V to 0V, the off-state current of the device is reduced by 3 orders of magnitude, and the on-state current is only reduced by a factor of 2. When the independent bias gate electrode voltage continues to drop, the off-state current keeps the minimum value unchanged, the threshold voltage increases, and the on-state current decreases at the same time, which can be used for low-power circuit design to adjust the drive current.

Referring to Figure 3, it can be seen more clearly that the bias voltage of the independent bias gate voltage is reduced from 0.8V to -2V, and the threshold voltage of the control gate is increased from 0.2V to 0.9V, the change of the threshold voltage is obvious. The dotted line in the figure is parallel to the threshold voltage vs. independently biased gate voltage curve, with a slope of 0.245. This slope reflects the adjustment sensitivity of the independent bias gate voltage to the threshold voltage change, and is also an intuitive reflection of the coupling strength between the independent bias gate and the control gate electrode. Theoretical calculations give this slope of 0.15 for the independently biased gate controlled DT T-FinFET device, compared to 0.2 for the FinFET dual gate device compared. The factor of our proposed independent gate-controlled nano-tunneling field effect double-gate device is higher than that of the above structure, indicating that the independent bias gate has a higher sensitivity to the regulation of the threshold voltage of the DT T-FinFET. As can be seen from Figure 3, a positive independent bias gate voltage will degrade the switching characteristics of the device, and the subthreshold slope of the device will increase rapidly. Reducing the independent bias gate voltage to negative bias improves the switching characteristics of the device, so that the sub-threshold slope at the starting point of the device transfer curve remains below 55mV/dec and continues to decrease.

Referring to Figure 4, when the independent bias gate voltage increases from -2V to 0.8V, the on-state current continues to increase, with a total increase of more than 2 orders of magnitude; the off-state current decreases first and then increases, and at -1V maintained at a minimum of about 10 ^-15 A between 0.2V. Therefore, the switching current ratio of the device increases first and then decreases, and has ideal switching characteristics when the independent bias gate voltage is between -1V and 0.2V.

Referring to Figure 5, when the independent bias gate voltage of the device increases from -2V to 0.8V, the maximum transconductance continues to increase by about 2 orders of magnitude; the drain-induced barrier lowering effect decreases with the bias gate voltage While decreasing, it tends to a constant value of about 0.2V when the bias gate voltage is less than 0V.

Referring to Figure 6, the current-voltage characteristics of the dynamic threshold tunneling field effect dual-gate device, that is, DT T-FinFET, are compared with conventional T-FinFET devices and SOI tunneling devices. Among them, in order to ensure the fairness of the comparison, Compared with the former, it has the same geometric structure, and the former fills the corresponding bias gate part with the insulating dielectric material silicon oxide; compared with the latter, it has the same cross-sectional area of the conductive channel. It can be seen from Figure 6 that the three devices have similar off-state currents. At the same time, when the device undergoes strong tunneling in the working state, the introduction of an independent bias gate makes there actually two tunneling regions in the channel region. The independent bias gate and the control gate are respectively connected to the top and bottom to generate tunneling current. Therefore, the driving current of the DT T-FinFET device is larger than that of the ordinary T-FinFET, and it is also larger than the on-state current of the corresponding SOI tunneling device.

Based on the above results, DT T-FinFET has achieved the maximum gate control capability, and the obtained device performance is better than that of ordinary T-FinFET devices and SOI tunneling devices, and it can be applied after the device size is reduced to 15nm and below technology nodes. potential. The device characteristics of the device operating under common gate conditions as the channel length shrinks are given in Figures 7-9.

Referring to Figure 7, the threshold voltage and subthreshold slope of a DT T-FinFET drift with channel length. The threshold voltage decreases with the decrease of the channel length of the device, and the drift of the threshold voltage is 0.25V after the channel length is reduced from 50 nm to 15 nm; the subthreshold slope decreases first and then increases with the decrease of the device channel length, When the channel length is more than 20 nanometers, it is within 50mV/dec.

Referring to Figure 8, the DT T-FinFET on-state current increases with decreasing channel region length, and the on-state current increases by more than an order of magnitude from 50 nm to 15 nm. Off-state current increases when the device channel length is less than 20 nanometers. Therefore, the switching current ratio of the device shows a trend of first increasing and then decreasing as the channel length decreases, and it maintains an ideal switching characteristic above 20 nanometers.

Referring to Figure 9, the maximum transconductance of the DT T-FinFET increases with a smaller channel length, reaching 3.3 microsiemens at a channel region length of 15 nm, and the drain induced barrier lowering effect decreases with the channel length Small and tends to a constant value of about 0.2V, with a small amount of drift.

Based on the above results, considering the device characteristics such as threshold voltage drift, subthreshold slope drift, switching current ratio, leakage-induced barrier reduction effect, and maximum transconductance, the dynamic threshold tunneling field effect dual-gate device (DT T-FinFET) can be Pushing channel lengths down to 20 nanometers and maintaining relatively desirable device performance is expected to push further to 15 nanometers and below.

The DT T-FinFET provided by the present invention can provide independent bias gate operation, thereby providing a selection scheme for nano-tunneling devices used in low-power circuit design. At the same time, compared with the corresponding ordinary T-FinFET devices and SOI tunneling devices, the dynamic threshold tunneling field effect double-gate device can provide a higher driving current while maintaining a similar off-state current, thereby improving the current switching ratio. Improve device switching characteristics. Under certain device design tolerance requirements, the dynamic threshold tunneling field effect dual-gate device can reduce the device gate length to 20 nanometers or less, and maintain relatively ideal device performance.

The foregoing are merely some of the embodiments of the present invention. For those of ordinary skill in the art, without departing from the inventive concept of the present invention, several modifications and improvements can be made, which all belong to the protection scope of the present invention.

Claims (4)

1. A dynamic threshold tunneling field effect dual-gate device, comprising a control gate electrode, an independently biased gate electrode, a source region, a drain region, a channel region, a control gate dielectric layer and an independently biased gate dielectric layer; Wherein, the independent bias gate electrode is located under the independent bias gate dielectric layer at the bottom of the threshold tunneling field effect dual gate device, and is separated from the channel region by the metal substrate and the independent bias gate dielectric layer; The control gate electrode is isolated from the channel region by a control gate dielectric layer, and the control gate dielectric layer surrounds the channel region from three sides; The source region and the drain region are respectively located at two ends of the channel region, and are isolated from the control gate by a control gate dielectric layer. 2. A kind of dynamic threshold tunneling field effect double-gate device according to claim 1, characterized in that: the material constituting the channel region is an undoped or lightly doped semiconductor material; The material constituting the source region and the drain region is a semiconductor material with a doping concentration of 5×10 ¹⁸ cm-3 to 2×10 ²¹ cm-3, and the doping types are different, the former is P-doped, the latter is N Doping, or vice versa. 3 . The dynamic threshold tunneling field effect dual-gate device according to claim 2 , wherein the material constituting the channel region is a silicon material with a boron doping concentration of 1×10 ¹⁷ cm −3 ; 4 . The source region material is a silicon material with a phosphorus doping concentration of 1×10 ²⁰ cm-3, and the drain region material is a silicon material with a boron doping concentration of 5×10 ¹⁸ cm-3. 4. a kind of dynamic threshold tunneling field effect double gate device according to any one of claims 1-3, is characterized in that: The thickness of the independently biased gate electrode is 5-20 nanometers; The thickness of the independent bias gate dielectric layer is 1.2-20 nanometers; The thickness of the control gate electrode is 5-20 nanometers; The thickness of the control gate dielectric layer is 1.2-2 nanometers; The width of the channel region is 3-10 nanometers, and the height is 3-50 nanometers.

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