CN116798874A - A method and system for improving temperature uniformity of multi-chip interconnection structures - Google Patents

Abstract

The application relates to the technical field of chip heat dissipation, and provides a method and a system for improving the temperature uniformity of a multi-chip interconnection structure, wherein the method comprises the steps of arranging a plurality of heat dissipation elements on a substrate to form a heat dissipation layer, wherein the heat dissipation capacity of the heat dissipation elements arranged at a position close to a second side of the heat dissipation layer is higher than that of the heat dissipation elements arranged at a position close to a first side of the heat dissipation layer; disposing a heat dissipation layer on a chip interconnect layer, wherein the chip interconnect layer comprises a plurality of dies; and disposing a cover plate layer on the heat dissipation layer, wherein heat generated by the chip interconnection layer is conducted to the cover plate layer by the heat dissipation layer, and heat exchange is performed by the cover plate layer and the heat dissipation layer. The application can effectively improve the temperature uniformity of the multi-chip interconnection structure.

Description

A method and system for improving temperature uniformity of multi-chip interconnection structures

Technical field

The present invention generally relates to the technical field of chip heat dissipation. Specifically, the present invention relates to a method and system for improving the temperature uniformity of a multi-chip interconnection structure.

Background technique

As the integration scale of chips becomes larger and larger, the power required per unit area of the chip is also increasing. The increase in the power per unit area of the chip will lead to an increase in the heat flow density (heat flux) on the chip, which will increase the heat generated by the chip, thereby causing the chip's heat dissipation problem to become more serious. Especially for multi-chip interconnected wafer-level chips, since multiple chips are connected to each other, when the chip heats up severely and the temperature distribution is uneven, it is easy to cause damage to devices and equipment. Therefore, it is necessary to propose a method that can improve the temperature uniformity of multi-chip interconnect structures.

Contents of the invention

In order to at least partially solve the above-mentioned problems in the prior art, the present invention proposes a method for improving the temperature uniformity of a multi-chip interconnect structure, which includes the following steps:

A plurality of heat dissipation elements are arranged on the substrate to form a heat dissipation layer, wherein the heat dissipation ability of the heat dissipation elements disposed close to the second side of the heat dissipation layer is higher than that of the heat dissipation element disposed close to the first side opposite to the second side of the heat dissipation layer. The heat dissipation capacity of the heat dissipation element at the location;

disposing the heat dissipation layer on a chip interconnect layer, wherein the chip interconnect layer includes a plurality of dies; and

A cover plate layer is arranged on the heat dissipation layer, wherein the heat dissipation layer conducts the heat generated by the chip interconnection layer to the cover plate layer, and the cover plate layer conducts heat exchange with the heat dissipation layer. .

In one embodiment of the present invention, arranging the heat dissipation layer on the chip interconnect layer includes arranging at least one of a plurality of heat dissipation elements on one of the plurality of dies.

In one embodiment of the invention it is provided that each heat dissipation element is arranged on one of the plurality of dies.

In one embodiment of the present invention, heat exchange between the cover plate layer and the heat dissipation layer includes:

A coolant inlet is provided on a first side of the cover layer, wherein the first side of the cover layer corresponds to the first side of the heat dissipation layer;

A coolant outlet is provided on a second side of the cover layer, the second side of the cover layer corresponding to the first side of the heat dissipation layer; and

The coolant flows from the first side to the second side of the cover layer while exchanging heat with the heat dissipation layer, and flows out from the coolant outlet.

In one embodiment of the present invention, the method for improving the temperature uniformity of a multi-chip interconnection structure further includes:

A thermal conductive layer is provided between the substrate and the chip interconnect layer, wherein the thermal conductive layer is configured to conduct heat generated by the die to the heat dissipation element.

In one embodiment of the invention, it is provided that a plurality of heat dissipation elements are configured with different structures to have different heat dissipation capabilities.

In one embodiment of the present invention, configuring multiple heat dissipation elements to have different structures includes:

A plurality of the heat dissipation elements are configured to include linear fins, wavy fins or zigzag fins, wherein the heat dissipation capacity of the zigzag fins is greater than the heat dissipation capacity of the wavy fins, and the wavy fins The heat dissipation capacity of the linear fins is greater than the heat dissipation capacity of the linear fins.

In one embodiment of the present invention, configuring multiple heat dissipation elements to have different structures includes:

A plurality of the heat dissipation elements is configured to consist of a plurality of fins, a plurality of fins and fin pins, or a plurality of fin pins, wherein the heat dissipation capacity of the fin pins is greater than the heat dissipation capacity of the fins. .

In one embodiment of the present invention, configuring multiple heat dissipation elements to have different structures includes:

Constructing a plurality of the heat dissipation elements to include fin pins of different shapes, the shapes of the fin pins including cylindrical and square cylindrical fins, wherein the heat dissipation capacity of the square cylindrical fin pins is greater than the heat dissipation capacity of the cylindrical fin pins; and / or

A plurality of the heat dissipation elements are configured to include fins of different sizes, wherein a plurality of first size fins has a heat dissipation capacity greater than a plurality of second size fins, the first size being smaller than the second size. ;and / or

A plurality of the heat dissipation elements are configured to include fin pins with different spacing, wherein the heat dissipation capacity of the fin pins at a first spacing is greater than the heat dissipation capacity of the fin pins at a second spacing, and the first spacing is smaller than the fin pins. Describe the second distance.

The present invention also proposes a system for improving the temperature uniformity of a multi-chip interconnection structure, including:

a chip interconnect layer, which includes multiple dies;

a heat dissipation layer disposed on the chip interconnect layer, the heat dissipation layer comprising a plurality of heat dissipation elements, wherein the heat dissipation element disposed close to the second side of the heat dissipation layer has a higher heat dissipation capacity than the heat dissipation element disposed close to the heat dissipation layer the heat dissipation capacity of the heat dissipation element at the location of the first side; and

A cover plate layer is arranged on the heat dissipation layer, wherein the heat dissipation layer conducts the heat generated by the chip interconnect layer to the cover plate layer, and the cover plate layer exchanges heat with the heat dissipation layer.

The present invention at least has the following beneficial effects: The present invention proposes a method for improving the temperature uniformity of a multi-chip interconnection structure, in which the heat dissipation elements are constructed to have different structures to have different heat dissipation capabilities, and the heat dissipation elements are arranged close to the heat dissipation layer. The heat dissipation capacity of the heat dissipation element at the position on the second side is higher than the heat dissipation capacity of the heat dissipation element disposed close to the first side of the heat dissipation layer, which can effectively improve the temperature uniformity of the multi-chip interconnection structure.

Description of the drawings

To further elucidate the advantages and features of various embodiments of the invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It will be understood that the drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be labeled with the same or similar reference numerals, for purposes of clarity and clarity.

FIG. 1 shows a schematic diagram of the hierarchical structure of a heat dissipation system for a multi-chip interconnection structure in one embodiment of the present invention.

FIG. 2A shows a schematic structural diagram of a heat dissipation layer in an embodiment of the present invention.

FIG. 2B shows a schematic plan view of a heat dissipation layer in one embodiment of the present invention.

FIG. 3A shows a schematic structural diagram of a heat dissipation element in an embodiment of the present invention.

Figure 3B shows a schematic plan view of a heat dissipation element in one embodiment of the present invention.

Figure 4 shows a schematic diagram of heat dissipation elements with different structures in one embodiment of the present invention.

FIG. 5A shows a schematic diagram of a heat dissipation element with different structures in another embodiment of the present invention.

FIG. 5B shows a schematic plan view of a heat dissipation element with different structures in another embodiment of the present invention.

Figure 6 shows a schematic diagram of a heat dissipation element with different structures in another embodiment of the present invention.

7A-G show a schematic diagram of an array of heat dissipation elements from the first side to the second side of the heat dissipation system in one embodiment of the present invention.

Figure 8 shows a schematic temperature diagram of a simulation experiment of a heat dissipation system with multiple identical heat dissipation elements in one embodiment of the present invention.

Figure 9 shows a schematic temperature diagram of a simulation experiment of a heat dissipation system according to the method for improving the temperature uniformity of a multi-chip interconnect structure in an embodiment of the present invention.

FIG. 10 shows a schematic flowchart of a method for improving the temperature uniformity of a multi-chip interconnection structure in an embodiment of the present invention.

FIG. 11A shows a schematic structural diagram of an array of heat dissipation elements in one embodiment of the present invention.

Figure 11B shows a schematic plan view of an array of heat dissipation elements in one embodiment of the present invention.

Detailed ways

It should be noted that components in the various figures may be exaggerated for illustration and are not necessarily proportionally correct. In the various figures, identical or functionally identical components are assigned the same reference numerals.

In the present invention, unless otherwise specified, “arranged on,” “arranged on,” and “arranged on” do not exclude the presence of intermediates between the two. In addition, "arranged on or above" only indicates the relative positional relationship between the two components. Under certain circumstances, such as after reversing the product direction, it can also be converted to "arranged on or below", and vice versa. Of course.

In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be construed as limiting.

In the present invention, unless otherwise specified, the quantifiers "a" and "一" do not exclude the scenario of multiple elements.

It should also be noted here that in the embodiments of the present invention, for the sake of clarity and simplicity, only some parts or assemblies may be shown. However, those of ordinary skill in the art can understand that under the teachings of the present invention, they may be modified according to specific The scene needs to add the required parts or components. In addition, features of different embodiments of the invention may be combined with each other unless stated otherwise. For example, a certain feature in the second embodiment can be used to replace a corresponding feature in the first embodiment or a feature with the same or similar function, and the resulting embodiment also falls within the disclosure scope or recording scope of the present application.

It should also be noted here that within the scope of the present invention, terms such as "the same", "equal", and "equal to" do not mean that the two values are absolutely equal, but allow a certain reasonable error. That is to say, the The wording also covers "substantially the same", "substantially equal", and "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to", etc. indicating directions also include the meanings of "substantially perpendicular to" and "substantially parallel to".

In the present invention, the term "heat dissipation capacity" refers to the value of heat dissipation per unit area per unit time.

In addition, the numbering of the steps of each method of the present invention does not limit the execution order of the method steps. Unless otherwise stated, method steps may be performed in a different order.

The present invention will be further described below in conjunction with specific embodiments and with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of the hierarchical structure of a heat dissipation system for a multi-chip interconnection structure in one embodiment of the present invention. As shown in FIG. 1 , the heat dissipation system includes a cover layer 101 , a heat dissipation layer 102 and a chip interconnection layer 103 .

The heat dissipation layer 102 is arranged on the chip interconnection layer 103, and the cover layer 101 is arranged on the heat dissipation layer 102, wherein the heat dissipation layer 102 conducts the heat generated by the chip interconnection layer 103 to the Cover layer 101, and heat exchange is performed on the cover layer 101. The chip interconnect layer 103 includes a plurality of die 108, wherein the plurality of die 108 are connected to each other.

The cover layer 101 and the heat dissipation layer 102 can be integrally formed through a welding process to form a complete liquid cooling heat dissipation device. A coolant inlet 104 is provided on a first side of the cover layer 101 , and a coolant outlet 105 is provided on a second side of the cover layer 101 opposite to the first side. The coolant inlet 104 The coolant outlet 104 can be connected to a water inlet pipe, and the coolant outlet 104 can be connected to a water outlet pipe, wherein the coolant can flow from the first side to the second side of the cover layer 101 and take away the heat conducted to the cover layer 101 .

FIG. 2A shows a schematic structural diagram of a heat dissipation layer in an embodiment of the present invention. FIG. 2B shows a schematic plan view of a heat dissipation layer in one embodiment of the present invention. As shown in FIGS. 2A and 2B , the heat dissipation layer 102 includes a substrate 106 and a plurality of heat dissipation elements 107 , wherein a plurality of the heat dissipation elements 107 are arranged on the substrate 106 . At least one of the plurality of heat dissipation elements 107 is arranged above one of the plurality of die 108 . Preferably, as shown in FIG. 1 , the plurality of heat dissipation elements 107 are arranged together with the plurality of die 108 . One correspondence. The heat dissipation layer 102 is attached to the chip interconnection layer 103, and a thermal conductive layer can be provided between the substrate 106 and the chip interconnection layer 103 to conduct the heat generated when the die 108 is working to the chip interconnection layer 103. Heat dissipation element 107.

FIG. 3A shows a schematic structural diagram of a heat dissipation element in an embodiment of the present invention. Figure 3B shows a schematic plan view of a heat dissipation element in one embodiment of the present invention. As shown in FIGS. 3A and 3B , the heat dissipation element 107 is arranged on the substrate 106 , and the heat dissipation element 107 may include a first area and a second area, and the first area is located in the center of the heat dissipation element. , the second area is located around the first area, wherein the heat dissipation element is configured such that the heat dissipation capacity in the first area is greater than or equal to the heat dissipation capacity in the second area. For example, the heat dissipation element may include fin pins 301 and fins 302, wherein the fin pins 301 may be arranged on the first area, the fins 302 may be arranged on the second area, and a plurality of the fins may be arranged on the first area. Flow channels may be formed between the sheets 302.

In the first aspect, the heat dissipation effect of the heat dissipation system provided by the present invention can be determined by the flow rate of the coolant. Through simulation experiments, it was found that the faster the coolant flow rate, the better the heat dissipation effect of the heat dissipation system. However, when the coolant flow rate reaches a critical value, even if the coolant flow rate continues to be increased, it is difficult to continue to improve the heat dissipation effect of the heat dissipation system. According to the results of the simulation experiment, the flow rate of the coolant may preferably be 0.6m/s to 1.5m/s.

In addition, according to the results of the simulation experiment, the temperature of the heat dissipation system is lower on the first side close to the coolant inlet 104 and the temperature is higher on the second side close to the coolant outlet 104. This is because the coolant gradually flows during the flow process. This is caused by absorbing the heat generated by the crystal grains 108 . In the embodiment of the present invention, the temperature of the hot spot on the second side close to the coolant outlet 104 reaches a maximum of 70 degrees Celsius, which can well meet the heat dissipation requirements of a multi-chip interconnected wafer-level chip with a power density of 25 kW, and the hot spot The temperature does not exceed 70 degrees Celsius.

According to the results of the simulation experiment, the temperature of the die 108 on the first side close to the heat dissipation system is lower, and the temperature of the die 108 close to the second side of the heat dissipation system is higher. Therefore, in another embodiment of the present invention, in order to improve the temperature uniformity of the chip, heat dissipation elements 107 with different heat dissipation capabilities can be arranged at different positions above the chip. Specifically, heat dissipation elements 107 are arranged close to the second side of the heat dissipation system. The heat dissipation capacity of the heat dissipation element 107 at the position is higher than the heat dissipation capacity of the heat dissipation element 107 at the position close to the first side of the heat dissipation system, thereby improving the temperature uniformity of the chip.

In the present invention, the heat dissipation capability of the heat dissipation element 107 is determined by the structure of the heat dissipation element 107 . Figure 4 shows a schematic diagram of heat dissipation elements with different structures in one embodiment of the present invention. As shown in FIG. 4 , the heat dissipation element 107 may only include fins 302 , or the heat dissipation element 107 may include fin pins 301 and fins 302 , or the heat dissipation element 107 may only include fin pins 301 , which only include The heat dissipation capacity of the heat dissipation element 107 of the fin pins 301 is higher than that of the heat dissipation element 107 including the fin pins 301 and fins 302, and the heat dissipation capacity of the heat dissipation element 107 including the fin pins 301 and fins 302 is higher than that of the heat dissipation element 107 including only the fins. The heat dissipation capacity of the heat dissipation element 107 is 302.

FIG. 5A shows a schematic diagram of heat dissipation elements with different structures in another embodiment of the present invention. FIG. 5B shows a schematic plan view of a heat dissipation element with different structures in another embodiment of the present invention. As shown in FIG. 5A-B, in the heat dissipation element 107 including only fins 302, the fins 302 can be linear fins 501, wavy fins 502 or zigzag fins 503, wherein there are zigzag fins. The heat dissipation capacity of the heat dissipation element 107 with the fins 503 is higher than that of the heat dissipation element 107 with the corrugated fins 502, and the heat dissipation capacity of the heat dissipation element 107 with the corrugated fins 502 is higher than that of the heat dissipation element with the straight fins 501 107 heat dissipation capacity.

Figure 6 shows a schematic diagram of a heat dissipation element with different structures in another embodiment of the present invention. As shown in FIG. 6 , in the heat dissipation element 107 that only includes fin pins 301 , the fin pins 301 can be arranged in an aligned or staggered arrangement. The heat dissipation capacity of the heat dissipation element 107 in which the fin pins 301 are staggered is higher than that of the fin pins. 301 The heat dissipation capability of the symmetrically arranged heat dissipation elements 107. Furthermore, the shape of the fin pins 301 can also be replaced from a cylinder to a square pillar or other structure, where the heat dissipation capacity of the square column fin pins is higher than that of the cylindrical fin pins. Further, the heat dissipation capacity of the heat dissipation element can be adjusted by adjusting the diameter of the fin pins 301 and the spacing between the plurality of fin pins 301. The smaller the diameter of the fin pins 301, the smaller the spacing between the plurality of fin pins 301. , the higher the heat dissipation capacity of the cooling element. Furthermore, the heat dissipation capacity of the heat dissipation element can be adjusted by adjusting the diameter of the fin pins 301 and the spacing between the plurality of fin pins 301 .

Figure 8 shows a schematic temperature diagram of a simulation experiment of a heat dissipation system with multiple identical heat dissipation elements in one embodiment of the present invention. As shown in Figure 8, when the heat dissipation unit is the same, the temperature uniformity of the heat dissipation system is relatively poor. The temperature difference in the high heat source area can reach 15°C, and the temperature difference in the bottom heat source area can reach 18°C.

Figure 10 shows a schematic flow chart of a method for improving the temperature uniformity of a multi-chip interconnect structure in an embodiment of the present invention. As shown in Figure 10, the method may include the following steps:

Step 1001. Arrange a plurality of heat dissipation elements 107 on the substrate 106 to form a heat dissipation layer 102, wherein the heat dissipation ability of the heat dissipation elements 107 arranged close to the second side of the heat dissipation layer 102 is higher than that of the heat dissipation elements 107 arranged close to the heat dissipation layer 102. The heat dissipation capability of the heat dissipation element 107 at the location of the first side.

Step 1002: Arrange the heat dissipation layer 102 on the chip interconnection layer 103, where the chip interconnection layer 103 includes a plurality of dies 108.

Step 1003: Arrange the cover layer 101 on the heat dissipation layer 102, wherein the heat dissipation layer 102 conducts the heat generated by the chip interconnect layer 103 to the cover layer 101, and the cover layer 101 exchanges heat with the heat dissipation layer 102.

According to this method, the heat dissipation elements 107 with increasingly higher heat dissipation capabilities may be arranged sequentially from the first side to the second side of the heat dissipation system. 7A-G show a schematic diagram of an array of heat dissipation elements from the first side to the second side of the heat dissipation system in one embodiment of the present invention. As shown in Figures 7A-G, in the heat dissipation system provided with 7×7 heat dissipation elements 107 as shown in Figure 1, the seven heat dissipation elements in a row are the first heat dissipation element 701 from the first side to the second side. , the second heat dissipation element 702...the seventh heat dissipation element 707. Among them, the first heat dissipation element 701 also has the weakest heat dissipation ability. From the first heat dissipation element 701 to the seventh heat dissipation element 707, by adjusting the diameter, spacing, shape, and arrangement of the fin pins 301 on the heat dissipation element, the heat dissipation of the heat dissipation element can be improved. The ability is getting higher and higher. After connecting the first to seventh heat dissipation elements 701-707, a row of heat dissipation elements of the heat dissipation system can be formed. FIG. 11A shows a schematic structural diagram of an array of heat dissipation elements in one embodiment of the present invention. Figure 11B shows a schematic plan view of an array of heat dissipation elements in one embodiment of the present invention.

Figure 9 shows a schematic temperature diagram of a simulation experiment of a heat dissipation system according to the method for improving the temperature uniformity of a multi-chip interconnect structure in an embodiment of the present invention. Since the change of hot spot temperature in the direction from the first side to the second side of the heat dissipation system has symmetrical periodicity, Figure 9 only shows the simulation experimental results on one row of heat dissipation elements, as shown in Figure 9, where the temperature uniformity Significant improvement has been achieved. The temperature difference in the high heat source area is only 2℃, and the temperature difference in the bottom heat source area is only 8℃.

According to simulation experiments, the change of hot spot temperature in the direction from the first side to the second side of the heat dissipation system has a symmetrical periodicity. Therefore, during the processing process, multiple rows of identical heat dissipation elements 107 can be processed first and then combined in parallel. into a whole with the same heat dissipation effect. Taking the heat dissipation system provided with 7×7 heat dissipation elements 107 shown in FIG. 1 as an example, a unit with a size of, for example, 196 mm×196 mm×9 mm can be split into seven units of 196 mm×28 mm×9 mm and then combined together.

In addition, for chips with a higher power density, such as chips with a power density of 50W/cm2 to 500W/cm2, the heat dissipation element 107 can use a microfluidic structure. For chips with a power density of 1000W/cm2 or above, the heat dissipation element 107 Element 107 may use a multi-phase, air bubble convection structure.

Although various embodiments of the present invention are described above, it should be understood that they are presented by way of example only and not by way of limitation. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made without departing from the spirit and scope of the invention. Accordingly, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely in accordance with the appended claims and their equivalents.

Claims (10)

1. A method for improving the temperature uniformity of a multi-chip interconnection structure, which is characterized by comprising the following steps: A plurality of heat dissipation elements are arranged on the substrate to form a heat dissipation layer, wherein the heat dissipation ability of the heat dissipation elements disposed close to the second side of the heat dissipation layer is higher than that of the heat dissipation element disposed close to the first side opposite to the second side of the heat dissipation layer. The heat dissipation capacity of the heat dissipation element at the location; disposing the heat dissipation layer on a chip interconnect layer, wherein the chip interconnect layer includes a plurality of dies; and A cover plate layer is arranged on the heat dissipation layer, wherein the heat dissipation layer conducts the heat generated by the chip interconnection layer to the cover plate layer, and the cover plate layer conducts heat exchange with the heat dissipation layer. . 2. The method for improving temperature uniformity of a multi-chip interconnection structure according to claim 1, wherein arranging the heat dissipation layer on the chip interconnection layer includes arranging at least one of a plurality of heat dissipation elements on the chip interconnection layer. on one of multiple grains. 3. The method for improving temperature uniformity of a multi-chip interconnection structure according to claim 2, wherein each heat dissipation element is arranged on one of the plurality of dies. 4. The method for improving the temperature uniformity of a multi-chip interconnection structure according to claim 1, wherein the heat exchange between the cover layer and the heat dissipation layer includes: A coolant inlet is provided on a first side of the cover layer, wherein the first side of the cover layer corresponds to the first side of the heat dissipation layer; A coolant outlet is provided on a second side of the cover layer, the second side of the cover layer corresponding to the first side of the heat dissipation layer; and The coolant flows from the first side to the second side of the cover layer while exchanging heat with the heat dissipation layer, and flows out from the coolant outlet. 5. The method for improving the temperature uniformity of a multi-chip interconnection structure according to claim 1, further comprising: A thermal conductive layer is provided between the substrate and the chip interconnect layer, wherein the thermal conductive layer is configured to conduct heat generated by the die to the heat dissipation element. 6. The method for improving temperature uniformity of a multi-chip interconnection structure according to claim 1, characterized in that a plurality of heat dissipation elements are configured to have different structures to have different heat dissipation capabilities. 7. The method for improving temperature uniformity of a multi-chip interconnection structure according to claim 6, wherein configuring multiple heat dissipation elements to have different structures includes: A plurality of the heat dissipation elements are configured to include linear fins, wavy fins or zigzag fins, wherein the heat dissipation capacity of the zigzag fins is greater than the heat dissipation capacity of the wavy fins, and the wavy fins The heat dissipation capacity of the linear fins is greater than the heat dissipation capacity of the linear fins. 8. The method for improving the temperature uniformity of a multi-chip interconnection structure according to claim 7, wherein configuring multiple heat dissipation elements to have different structures includes: A plurality of the heat dissipation elements is configured to consist of a plurality of fins, a plurality of fins and fin pins, or a plurality of fin pins, wherein the heat dissipation capacity of the fin pins is greater than the heat dissipation capacity of the fins. . 9. The method for improving temperature uniformity of a multi-chip interconnection structure according to claim 8, wherein configuring multiple heat dissipation elements to have different structures includes: Constructing a plurality of the heat dissipation elements to include fin pins of different shapes, the shapes of the fin pins including cylindrical and square cylindrical fins, wherein the heat dissipation capacity of the square cylindrical fin pins is greater than the heat dissipation capacity of the cylindrical fin pins; and / or A plurality of the heat dissipation elements are configured to include fins of different sizes, wherein a plurality of first size fins has a heat dissipation capacity greater than a plurality of second size fins, the first size being smaller than the second size. ;and / or A plurality of the heat dissipation elements are configured to include fin pins with different spacing, wherein the heat dissipation capacity of the fin pins at a first spacing is greater than the heat dissipation capacity of the fin pins at a second spacing, and the first spacing is smaller than the fin pins. Describe the second distance. 10. A system for improving the temperature uniformity of a multi-chip interconnection structure, which is characterized by including: a chip interconnect layer, which includes multiple dies; a heat dissipation layer disposed on the chip interconnect layer, the heat dissipation layer comprising a plurality of heat dissipation elements, wherein the heat dissipation element disposed close to the second side of the heat dissipation layer has a higher heat dissipation capacity than the heat dissipation element disposed close to the heat dissipation layer the heat dissipation capacity of the heat dissipation element at the location of the first side; and A cover plate layer is arranged on the heat dissipation layer, wherein the heat dissipation layer conducts the heat generated by the chip interconnect layer to the cover plate layer, and the cover plate layer exchanges heat with the heat dissipation layer.