CN116798496A - Chip and electronic equipment thereof - Google Patents

Abstract

The application relates to the field of integrated circuit design, in particular to a chip and an electronic device thereof, wherein the chip comprises a fuse trimming circuit, and the application is characterized in that the fuse trimming circuit can comprise: the device comprises an inverting delay unit, a fuse reading unit, a fuse burning unit and a latch unit. In the power-on process of the chip, the fuse reading unit reads the burning state of the fuse resistor, the reading result is latched by the latching unit, after the chip works normally, the inverted delay unit sends out an enabling signal to close the fuse reading unit, the fuse reading passage can not have current to pass, power consumption can not be generated, and the power consumption of the whole integrated circuit can be reduced. The fuse trimming circuit also comprises a common gate amplifier which amplifies the comparison result of the reference resistor and the fuse resistor and is used for judging whether the fuse is blown or not, and the blowing threshold value can be set by the fuse trimming circuit.

Description

Chip and electronic equipment thereof

Technical Field

The present application relates to the field of integrated circuit design, and in particular, to a chip and an electronic device thereof.

Background

Fuse resistance or electrically programmable fuses (electrically programmable fuse, eFUSEs) or electrical fuses are one-time programmable memories widely used in integrated circuits or chips and may be used to modify the identity, function, etc. of an integrated circuit, for example, to effect curing of parameters of some integrated circuits in the event of a fuse resistance blow.

In the existing fuse trimming circuit, when a chip works normally and a fuse is not burnt, current flows through a fuse resistor to generate current consumption; in the other technology, after the fuse resistor is burned, although the fuse resistor is opened by default, the fuse resistor is not burned completely during the burning, the resistance value may be only a few kiloohms, and the leakage current still exists, in particular, when a plurality of fuse circuits are arranged in a chip, the circuit power consumption is increased. Therefore, there is a need for a fuse trimming circuit for an integrated circuit or chip, wherein no current path exists in the fuse trimming circuit for reading the fuse resistor after the power is applied.

In addition, the common gate amplifier is adopted to amplify the comparison result of the reference resistor and the fuse resistor, and is used for judging whether the fuse resistor is blown or not, and the threshold value of the blowing of the fuse can be set. Under the test mode of the fuse resistor, the threshold value of the fuse resistor is judged to be higher than the threshold value of the resistor in normal operation, a stricter condition is provided for the fuse resistor to verify whether the fuse resistor is blown or not, the fuse resistor screened by factory test is realized, and whether the fuse resistor is blown or not can be accurately and reliably judged when a user uses the fuse resistor, so that the reliability is higher.

Disclosure of Invention

The application aims to provide a chip.

A first aspect of the present application provides a chip including a fuse trimming circuit, characterized in that the fuse trimming circuit includes: the device comprises an inverting delay unit, a fuse reading unit, a fuse burning unit and a latch unit. In the power-on process of the chip, the fuse reading unit reads the burning state of the fuse resistor, the reading result is latched by the latching unit, and after the chip works normally, the inverted delay unit sends out an enabling signal to close the fuse reading unit.

That is, in the embodiment of the present application, the first fuse resistor may be the fuse resistor in fig. 2, the inverting delay unit may be referred to as a switch control unit, the fuse reading unit may be the inverter transmission unit in fig. 2, and the fuse programming unit may be the control fuse programming unit in fig. 2. In the fuse trimming circuit, corresponding switching units are provided for fuse read paths formed through fuse resistances, the switching units being capable of achieving turning on and off of the respective fuse read paths. And the switch control units are arranged on the switch units and used for controlling the switch units to be turned on and turned off, and when the chip works normally, the switch control units control the switch units to be in a turned-off state, so that the fuse reading passage is turned off, namely, the passage corresponding to the resistance state of the fuse can be read, and in the running process of the integrated circuit, the fuse reading passage can not have current to pass, power consumption can not be generated, and the power consumption of the whole integrated circuit can be reduced.

In a possible implementation of the first aspect, the fuse trimming circuit further includes: the common gate amplifier unit is used for determining a first logic signal according to the fusing state of the first fuse resistor;

the inverter transmission unit is connected with the common gate amplifier unit and is used for inverting the first logic signal to obtain a second logic signal;

and the latch unit is connected with the inverter transmission unit and is used for latching the second logic signal.

In a possible implementation manner of the first aspect, the switching unit includes a first switching unit, a second switching unit and a third switching unit, where the first switching unit includes a first switching tube, the second switching unit includes a second switching tube, and the third switching unit includes a third switching tube.

In a possible implementation manner of the first aspect, the common gate amplifier unit includes a fourth switching tube, a fifth switching tube, a sixth switching tube, and a seventh switching tube, where gates of the fourth switching tube and the fifth switching tube are connected to the first node, gates of the sixth switching tube and the seventh switching tube are connected to the second node, an input terminal of the fifth switching tube and the first fuse resistor are connected to the third node, and an output terminal of the fifth switching tube and an input terminal of the seventh switching tube are connected to the fourth node.

In a possible implementation manner of the first aspect, the inverter transmission unit includes an eighth switching tube and a ninth switching tube, where an output terminal of the eighth switching tube and an input terminal of the ninth switching tube are connected to the fifth node.

In a possible implementation of the first aspect, the method further includes: the first switch control unit is used for generating a first switch signal, a second switch signal and a third switch signal according to signals in the power-on process of the chip.

In a possible implementation manner of the first aspect, when the first switching signal is at a low level, the first switching tube of the first switching unit is turned on, the second switching signal is at a high level, the second switching tube of the second switching unit is turned on, the third switching signal is at a low level, and the third switching tube of the third switching unit is turned off.

In one possible implementation of the first aspect, when the first switching tube and the second switching tube of the first switching unit are turned on, the first node is at a high level, the second node is at a low level, and the fifth switching tube and the seventh switching tube are turned off, so that the fuse read path is turned off.

In a possible implementation of the first aspect, when the third switching tube of the third switching unit is turned off, the eighth switching tube and the ninth switching tube of the inverter transmission unit are turned off, so that the fourth node is disconnected from the fifth node.

In a possible implementation of the first aspect, the method further includes: the control fuse programming unit is used for controlling and programming the first fuse resistor, wherein the control fuse programming unit comprises a tenth switching tube and a first resistor, the input end of the tenth switching tube and the first fuse resistor are connected to a third node, and the first fuse resistor and the tenth switching tube form a fuse programming passage.

In one possible implementation of the first aspect, when the fuse writing signal is not applied to the gate of the tenth switching tube, the tenth switching tube is turned off, so that the fuse writing path is turned off, and when the fuse writing signal is applied to the gate of the tenth switching tube, the tenth switching tube is turned on, and the first fuse resistor is written.

In one possible implementation of the first aspect, the signal during the power-on process of the chip is at a low level, the first inverter, the second inverter and the third inverter of the signal adjustment unit adjust the first switching signal to be at a high level, the first switching tube of the first switching unit is turned off, the second switching signal is adjusted to be at a low level, the second switching tube of the second switching unit is turned off, the third switching signal is adjusted to be at a high level, and the third switching tube of the third switching unit is turned on.

In one possible implementation manner of the first aspect, when the first switching tube and the second switching tube of the first switching unit are turned off, the first node is at a low level, the second node is at a high level, and the first fuse resistor, the fifth switching tube and the seventh switch Guan Xingcheng are in a first path, so that logic signals of the third node and the fourth node are the same, and a first logic signal corresponding to the fourth node is obtained.

In a possible implementation manner of the first aspect, when the third switching tube of the third switching unit is turned on, the eighth switching tube and the ninth switching tube of the inverter transmission unit are turned on, so that the first logic signal is transmitted from the fourth node to the fifth node, and the latch unit stores the second logic signal corresponding to the fifth node, where the second logic signal is opposite to the logic value of the first logic signal.

In a possible implementation of the first aspect, the method further includes: and the bias current source comprises an eleventh switching tube, and the grid electrode of the eleventh switching tube, the grid electrodes of the sixth switching tube and the seventh switching tube are connected to the second node.

In a possible implementation of the first aspect, the method further includes: a reference resistance unit including: the first reference resistor, the second reference resistor and the twelfth switching tube are connected with the input end of the fourth switching tube.

In a possible implementation of the first aspect, in the test mode, when the first switching tube and the second switching tube of the first switching unit are turned off, the bias current source, the first fuse resistor, the fifth switching tube and the seventh switching Guan Xingcheng form a third path, the bias current source, the reference resistor unit, the fourth switching tube and the sixth switching tube form a fourth path, wherein the third path and the fourth path respectively flow through a first bias current and a second bias current, and the first bias current and the second bias current are the same.

In one possible implementation of the first aspect, when the voltage of the gate of the twelfth switching transistor is at a high level, the fusing threshold of the first fuse resistor is a sum of resistance values of the first reference resistor and the second reference resistor.

In one possible implementation of the first aspect, when the voltage of the gate of the twelfth switching transistor is at a low level, the fusing threshold of the first fuse resistor is the resistance value of the first reference resistor.

A second aspect of the application provides an electronic device comprising a chip as in the first aspect.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a schematic circuit diagram of a fuse trimming circuit in accordance with an embodiment of the present application;

FIG. 2 illustrates a circuit schematic of a fuse trimming circuit in accordance with an embodiment of the present application;

FIG. 3 illustrates a timing diagram of a fuse trimming circuit, according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an electronic device including a chip with fuse trimming circuit according to an embodiment of the present application;

fig. 5 shows a block schematic diagram of a SoC in accordance with an embodiment of the present application.

Detailed Description

Illustrative embodiments of the application include, but are not limited to, an electronic device and fuse trimming circuit therefor.

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and thoroughly described with reference to the accompanying drawings. Wherein, in the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; the text "and/or" is merely an association relation describing the associated object, and indicates that three relations may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone.

The terms "first," "second," and the like, are used below for descriptive purposes only and are not to be construed as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature, and in the description of embodiments of the application, unless otherwise indicated, the meaning of "a plurality" is two or more.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the described embodiments of the application may be combined with other embodiments.

In order to make the technical scheme and advantages of the present application more clear, the technical scheme in the embodiments of the present application will be clearly and thoroughly described below with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 illustrates an example of a fuse trimming circuit 100 according to an embodiment of the present application. As shown in fig. 1, the fuse trimming CIRCUIT 100 includes a power supply VDD (Voltage Drain Drain, drain power supply voltage), a first fuse CIRCUIT portion 101, a second fuse CIRCUIT portion 102, and a CONTROL CIRCUIT (CONTROL CIRCUIT). The first fuse circuit portion 101 includes: fuse resistor F1, switching tube MN0, switching tube MN3, switching tube MN4 and two-input NAND gate U4. The second fuse circuit portion 102 includes: fuse resistor F2, switching tube MN6, switching tube MN7, switching tube MN8 and two-input NAND gate U8.

Since the circuit structures of the first fuse circuit portion 101 and the second fuse circuit portion 102 are the same, the first fuse circuit portion 101 will be described below as an example. As shown in fig. 1, one end of the fuse resistor F1 is connected to a power supply VDD (Voltage Drain Drain, drain power supply voltage), the other end is connected to an NMOS (switching tube) MN0, the gate of the switching tube MN0 is controlled by a TRIM signal through inverters U1 and U2, the TRIM signal controls on and off of the MN0, and the other end of the MN0 is grounded. When the switching tube MN0 is turned on, the power supply VDD, the fuse resistor F1, the switching tube MN0 and the ground GND form a path, and a current flowing through the fuse resistor F1 is sufficient to blow the fuse resistor F1.

The switching transistor MN4 is a switching transistor which is turned on or off by the OUT signal, and is connected to the switching transistor MN3 for providing current bias. The drains of the fuse resistors F1 and MN0 and the drain of MN4 are commonly connected to a two-input nand gate U4, and the other end of the two-input nand gate U4 is a RESET signal RESET.

When the RESET signal RESET is low, the output signal OUT is high, the switch tube MN4 is turned on, and when the fuse resistor F1 is not blown, the power supply VDD, the fuse resistor F1, the switch tube MN4, the switch tube MN3 and the ground GND form a path, and when the fuse resistor F1 is not blown, the resistance is small, for example: since the voltage difference across the fuse resistor F1 is low, the voltage difference across the two-input nand gate U4 is high at one end I0. When the RESET signal RESET goes from low to high, the output signal OUT is determined by the I0 signal level. When the fuse is not blown, I0 is high level, the output signal OUT is low level, the switch tube MN4 is cut off, the passage of the fuse resistor F1 is closed, no current flows through the fuse resistor F1, and the circuit power consumption is reduced.

However, when the fuse resistor F1 is blown, the I0 signal is low, the output signal OUT is high, and since the fuse path formed by the power supply VDD, the fuse resistor F1, the switching tube MN0 and the ground GND is not closed, that is, the switching tube MN0 is not completely turned off, although the blown fuse resistor F1 has a resistance of several kiloohms, a leakage current exists in the fuse path formed by the fuse resistor F1, the switching tube MN4, the switching tube MN3 and the ground GND.

In the fuse trimming circuit 100 shown in fig. 1, when the fuse resistor F1 is not blown, the fuse path does not consume current, but after the fuse resistor F1 is blown, there is still leakage current in the fuse read path capable of reading the fuse resistor F1, that is, in the fuse trimming circuit 100 shown in fig. 1, the fuse read path is not completely closed, that is, the relevant path corresponding to the state of the read fuse resistor F1 is not closed. In the case where the fuse trimming circuit 100 includes a plurality of fuse resistances, or in the case where the integrated circuit includes a plurality of fuse trimming circuits 100, power consumption of the integrated circuit may increase.

In some embodiments, the fuse resistor F1 may be a resistor or a metal wire within the fuse trimming circuit 100, and may generally be a narrow wire, so that its capability of passing dc current is weak. Such a wire will be fused when a large current is passed through it. Illustratively, the blowing may be that the fuse resistance F1 is blown or that the resistance becomes larger due to electromigration, for example, a resistance value that is much greater than a particular reference resistance.

In some embodiments, the act of blowing the fuse resistor F1 by applying a voltage across the fuse resistor F1 is called programming or programming. The burning process of the fuse resistor F1 is not reversible. In some embodiments, whether the fuse resistor is blown or not may be determined according to the resistance value of the fuse resistor and the state of the fuse resistor, the low resistance state before the fuse resistor is not blown may be a logic state "0", and the high resistance state after the fuse resistor is blown may be a logic state "1".

In order to solve the problem of leakage current in the fuse path corresponding to the fuse resistor after the fuse resistor is blown as shown in fig. 1, an embodiment of the present application provides a fuse trimming circuit, in which a corresponding switching unit is provided for a fuse reading path formed through the fuse resistor, that is, a path corresponding to a state of the fuse resistor, and the switching unit is capable of implementing on and off of each fuse reading path. And setting a switch control unit for each switch unit, wherein the switch control unit is used for controlling the switch units to be turned on and turned off, and after the chip is powered on, the switch control unit controls each switch unit to be in an off state according to a signal after the chip is powered on, so that each fuse reading passage is turned off, namely, a passage corresponding to the state capable of reading the fuse resistance is turned off, and in the operation process of the integrated circuit, no current passes through the fuse reading passage, no power consumption is generated, and the power consumption of the whole integrated circuit can be reduced.

In some embodiments, during the power-up process of an integrated circuit (chip) including a fuse trimming circuit, the switch control unit can control each switch unit to be in a connection state according to a signal generated by the integrated circuit, so that the fuse reading path is turned on, and a logic signal corresponding to the fuse resistance is obtained through the fuse reading path or whether the fuse resistance is blown or not is judged.

Referring now to fig. 2, fig. 2 illustrates an example of a fuse trimming circuit 200 in accordance with an embodiment of the present application. The fuse trimming circuit 200 shown in fig. 2 includes: power supply VDD, ground VSS (Voltage Series Series, common ground voltage), fuse resistor 201, inverting delay unit 202, common gate amplifier unit 203, reference resistor unit 204, control fuse programming unit 205, first switch unit 206, second switch unit 207, third switch unit 208, inverter transfer unit 209, latch unit 210, and reference current source 211 and bias current source 212.

In the fuse trimming circuit 200 shown in fig. 2, after the fuse resistor 201 of the fuse trimming circuit 200 is blown, the inverting delay unit 202 can control the first switch unit 206, the second switch unit 207, and the third switch unit 208 to be turned off by switching the timing signals, so that the paths corresponding to the states of the fuse resistor 201 in the fuse trimming circuit 200 can be closed, and even after the fuse resistor 201 is blown, no current flows through the paths corresponding to the states of the fuse resistor 201 in the fuse trimming circuit 200.

Illustratively, a fuse resistance R _FUSE 201 has a resistance value R _FUSE For example: fuse resistor R _FUSE 201 may be tens of ohms when not fused and may be megaohm or kiloohm after fusing。

Illustratively, the control fuse burning unit 205 includes a switch tube PM4 (as a tenth switch tube) and a resistor R1 for controlling burning or blowing the fuse resistor 201. The fuse resistor 201 is connected to the control fuse programming unit 205, the fuse resistor 201 is connected to a node C (as a third node) at one end of the control fuse programming unit 205, and the other end of the fuse resistor 201 is connected to the power supply VDD. When the FUSE resistor 201 needs to be burned, a voltage is applied to the switch tube PM4 by setting the control signal fuse_en, and the power supply VDD, the FUSE resistor 201, the switch tube PM4 and the ground VSS form a path, so that the current flowing through the FUSE resistor 201 blows the FUSE resistor 201, and the resistance value of the FUSE resistor 201 becomes very large, that is, the FUSE resistor 201 is in an open circuit. When the FUSE resistor 201 is not required to be blown, the control signal fuse_en is set to be suspended, and the gate of the switch tube PM4 is grounded due to the resistor R1, so that the switch tube PM4 is turned off, that is, the power supply VDD, the FUSE resistor 201, the switch tube PM4 and the ground VSS do not form a path.

Illustratively, the inverse delay unit 202 includes: a delayer 2021, a delayer 2022, an inverter 2023, an inverter 2024, and an inverter 2025. For inverting and delaying the power-on reset signal RST corresponding to the integrated circuit including the fuse trimming circuit 200, the clock signal CLK and the enable READ signal read_en, and the signal en_bar for controlling the switching transistor NM3 are outputted. As shown in fig. 3, during the slow power-up of the integrated circuit including the fuse trimming circuit 200, the power-up reset signal RST is always low, the output clock signal CLK is low, read_en is high, and en_bar is low; when the power supply VDD of the integrated circuit rises to a stable value, the RST signal is high, after a delay, the CLK signal goes high, after a delay, the enable READ signal read_en goes low, and the en_bar goes high, and then the signal level is kept unchanged.

Illustratively, the reference resistance unit 204 includes: reference resistor R _REF Resistance R _MR And a switching tube PM0 (as a twelfth switching tube) for controlling the switching tube PM0 by the test signal EN_MR to adjust the reference resistance R _REF And resistance R _MR Obtain the corresponding fusing threshold values of different fuse resistances 201. When the test signal en_mr is 1, the switching tube PM0 is turned off, and the fusing threshold=the reference resistor R _REF +resistance R _MR The resistance of the fusing threshold after fusing is at least larger than the reference resistance R _REF +resistance R _MR It is determined that the fuse resistance 201 is blown. When the test signal EN_MR is 0, the switch tube PM0 is turned on, so that the switch tube PM0 shorts a portion of the resistor R _MR Fusing threshold = reference resistance R _REF 。

Illustratively, the common gate amplifier unit 203 includes a switching tube PM2, a switching tube PM3, a switching tube NM1, and a switching tube NM2. Bias current source 212.

Illustratively, the bias current source 212 includes a switching tube NM0 (as an eleventh switching tube). When the gate of the switching transistor NM0 and the gate-connected node B (as the second node) of the switching transistor PM2 (as the fourth switching transistor) and the switching transistor PM3 (as the fifth switching transistor) of the common-gate amplifier unit 203 form a path between the reference resistor unit 204, the switching transistor PM2, and the switching transistor NM1 (as the sixth switching transistor), and a path between the fuse resistor 201, the switching transistor PM3, and the switching transistor NM2 (as the seventh switching transistor), a bias current I is generated in the two paths _B1 Bias current I _B1 Obtained by mirroring the bias current IB.

The common gate amplifier unit 203 is used for controlling the reference resistor R in the reference resistor unit 204 _REF And resistance R _MR Corresponding resistance value (R _ref ) Bias current I _B1 Determining a blow threshold (R) corresponding to fuse resistance 201 _FUSE ). The common-gate amplifier unit 203 has input terminals S1 and S2, and the voltage difference between the input terminals Δv _IN ＝I _B1 (R _ref -R _FUSE ). The gain of the common gate amplifier unit 203 is:

for example, if the channel modulation factor lambda of the switching tube PM2 and the switching tube PM3 _p Is 0.01, V _GS -V _TH For overdrive voltages, for example: when the driving voltage is 0.2, V _GS -V _TH May be 0.2, thenThe gain of the resulting common-gate amplifier unit 203 is about 500.

Illustratively, the signal output of the common-gate amplifier unit 203 is ΔV _OUT ＝A _V ×ΔV _IN If the voltage at node D (as the fourth node) is 0.2V when the fuse resistor 201 is blown and 2.5V when the fuse resistor 201 is not blown, then the flip point is assumed to be in the middle, i.e Wherein the overdrive voltage is 0.2V, the power supply voltage vdd=2.75v, the bias current I _B1 10uA, reference resistance R _REF And resistance R _MR Corresponding resistance value (R _ref ) R is calculated to be 2 kiloohms _FUSE＝ 1.77kΩ. The fuse resistor 201 is blown by default as long as the resistance after the burning of the fuse resistor 201 is greater than 1.77kΩ.

It can be seen that the resistance value of the fuse resistor 201 burnt by the common gate amplifier unit 203 is reduced from megaohm level to kiloohm level, the requirement on the fusing degree of the fuse resistor 201 is reduced, and the reference resistor R can be adjusted _REF And resistance R _MR Corresponding resistance value (R _ref ) The corresponding blow threshold values of the different fuse resistances 201 are obtained. That is, the common gate amplifier unit 203 in the fuse trimming circuit 200 according to the embodiment of the present application can configure the fusing threshold of the fuse resistor 201, and change the fusing threshold of the fuse resistor 201 from the megaohm level to the kiloohm level, so that the fuse resistor 201 is easier to burn and has higher reliability.

Illustratively, the first switching unit 206 includes: the switching tube PM1 (as a first switching tube), the switching tube PM1 is controlled by the read signal en_buf, and during the slow power-up process of the integrated circuit including the fuse trimming circuit 200, the inverting delay unit 202 controls the read signal en_buf to be at a high level, the switching tube PM1 is turned off, that is, the switching tube PM1 is turned off when the resistance value of the fuse resistor 201 is read, the switching tube PM1 is turned on when the integrated circuit is in normal operation, and the node a (as a first node) is connected to the power supply VDD, so that the switching tube PM2 and the switching tube PM3 of the common gate amplifier unit 203 are turned off. Illustratively, the path formed by the reference resistor unit 204, the switching tube PM2, and the switching tube NM1, and the path formed by the fuse resistor 201, the switching tube PM3, and the switching tube NM2 are closed.

Illustratively, the second switching unit 207 includes: the switching tube NM3 (as a second switching tube), the switching tube NM3 is controlled by a signal en_bar, and during the slow power-up process of the integrated circuit including the fuse trimming circuit 200, the inverting delay unit 202 controls the read signal en_bar to be low level, the switching tube NM3 is turned off, i.e., turned off when the resistance value of the fuse resistor 201 is read, the switching tube NM3 is turned on when the integrated circuit is normally operated, the node B is connected to the ground VSS, i.e., the node B is grounded, and the switching tubes NM1 and NM2 of the common gate amplifier unit 203 are turned off.

Illustratively, the third switching unit 208 includes: the switching transistor NM5 (as a third switching transistor), the switching transistor NM5 is controlled by the signal read_en, and during the slow power-up of the integrated circuit including the fuse trimming circuit 200, the inverting delay unit 202 controls the READ signal read_en to be at a high level, the switching transistor NM5 is turned on, and the switching transistor NM5 is turned off when the integrated circuit is operating normally, and the path passing the node D to the node E (as a fifth node) is turned off.

Illustratively, the inverter transmission unit 209 includes: a switching tube NM4 (as a ninth switching tube) and a switching tube PM5 (as an eighth switching tube). For passing the node D logical value to point E. During slow power-up of the integrated circuit including the fuse trimming circuit 200, the read_en is at a high level, the switching transistor NM5 is turned on, and when the node D is at a high level, the signal is transferred to the node E at a low level, and the signal is transferred to the node E at a high level. When the integrated circuit is operating normally, i.e., the resistance value of the READ fuse resistor 201 is over, read_en is low, the switching transistor NM5 of the third switching unit 208 is turned off, the path through which the node D is transferred to the node E is closed, and the node D is pulled directly to high level by the power supply VDD.

Illustratively, the latch unit 210 is configured to latch the logic level of the node E when the rising edge of the clock signal CLK arrives, and output an OUT signal to other circuits.

Illustratively, the switching transistors NM0 to NM5 are NMOS transistors, and the switching transistors PM0 to PM4 are PMOS transistors.

In some embodiments, specifically, with continued reference to fig. 2, when the integrated circuit including the fuse trimming circuit 200 is powered on by the power supply VDD, that is, during power-up of the integrated circuit, the power-up reset signal RST is low, the output clock signal CLK is low, the enable READ signal read_en is high, and en_bar is low, at which time, if the resistance value of the fuse resistor 201 is greater than the fusing threshold value, that is, the fusing threshold value determined by the reference resistor unit 204 and the common gate amplifier unit 203, the default fuse resistor 201 has been fused, the node D is low, and the output node E is high through the inverter transmission unit 209; if the resistance value of the fuse resistor 201 is smaller than the blowing threshold, it is determined that the fuse resistor 201 is not blown, the node D is high, and the node E is low through the inverter transmission unit 209. The logic levels of node D and node E may be determined by whether fuse resistor 201 is blown, for example.

When the power-on reset signal RST is changed from the low level to the high level, the clock signal CLK is controlled to be changed to the high level by one of the delays 2021 of the inverting delay unit 202, and the latch unit 210 latches the logic level of the node E according to the rising edge of the clock signal CLK. The clock signal CLK goes through a delay 2022 and an inverter 2023 to enable the READ signal read_en to be low, the switching transistor NM5 of the third switching unit 208 is turned off, and the path of the node D to the node E is cut off, and at this time, the node E is pulled high by the reference current source 211 and remains high.

Illustratively, the enable READ signal read_en outputs en_bar to a high level through an inverter 2024, which controls the switching transistor NM3 of the second switching unit 207 to be turned on, grounds the node B, and turns off the switching transistors NM1 and NM2 of the common-gate amplifier unit 203. The signal en_bar is outputted to en_buf at a low level through one inverter 2025, and the switching tube PM1 of the first switching unit 206 is turned on, and the node a is connected to the power supply VDD, so that the switching tube PM2 and the switching tube PM3 of the common-gate amplifier unit 203 are turned off.

Illustratively, the path formed by power supply VDD, fuse resistor 201, switching tube PM4, and ground VSS is closed, and the path formed by power supply VDD, fuse resistor 201, switching tube PM3, switching tube NM2, and ground VSS is closed. By delaying the control signal READ_EN to the clock CLK signal and delaying the EN_BAR and EN_BUF to the READ_EN signals by the inverting delay unit 202, it is ensured that the latch unit 210 latches a logic value determined by the fuse resistor 201, and then sequentially closes the corresponding path of the state of the READ latch unit 210. Through the fuse trimming circuit 200 of the embodiment of the present application, after the power-on reset signal RST of the integrated circuit or the chip is changed from the low level to the high level signal and a period of time delay is passed, the paths of the fuse reading resistor 201 in the fuse trimming circuit 200 are all closed except the latch unit 210, no current passes through the fuse resistor 201, and the power consumption of the fuse trimming circuit 200, that is, the integrated circuit is reduced.

In some embodiments, when the integrated circuit including the fuse trimming circuit 200 shown in FIG. 2 is in a test mode, the enable signal EN_MR may be controlled to be 1 to adjust the reference resistance R of the reference resistance unit 204 _REF And resistance R _MR The resulting fuse resistance 201 corresponds to the fusing threshold=reference resistance R _REF +resistance R _MR Thus, the resistance of the fuse resistor 201 after burning is at least greater than the reference resistor R _REF +resistance R _MR Can be confirmed as fused. At the time of powering up the integrated circuit, if the resistance value of the fuse resistor 201 is smaller than the blowing threshold, that is, the node D is at a high level, the output node E is at a low level through the inverter transmission unit 209, at this time, it may be determined that the resistance value of the fuse resistor 201 burned in the fuse trimming circuit 200 does not satisfy the blowing threshold, and in the test mode, it may be determined that the fuse resistor 201 of the fuse trimming circuit 200 is failed.

It can be seen that when the existing circuit may be tested, the fuse logic is judged to be "blown", but the blown fuse may have a rollback phenomenon, or be affected by voltage and temperature, so that the fuse logic may be misjudged to be not "blown" in the customer's hand, and the reliability of the chip is reduced. The application discloses an electric fuse state detection circuit, which is used for judging whether an electric fuse is blown or not when the electric fuse is in a test mode, and judging whether the resistance is blown or not when the resistance is higher than the resistance in normal work.

Fig. 4 is a schematic structural diagram of an electronic device 10 according to an embodiment of the present application. As shown in fig. 4, an embodiment of the present application provides an electronic device 10, comprising: a chip 11, a fuse trimming circuit 12 and a base plate 13.

The fuse trimming circuit 12 is disposed in the chip 11, and the fuse trimming circuit 12 is used for recording the generated logic value of the chip 11. The chip 11 is illustratively arranged on a base 13 of the electronic device 10, where the base 13 may be a PCB (Printed Circuit Board ).

Fig. 5 shows a block diagram of a System on Chip (SoC) 500 in accordance with an embodiment of the present application. In fig. 5, similar parts have the same reference numerals. In addition, the dashed box is an optional feature of a more advanced SoC. In fig. 5, the SoC 500 includes: an interconnect unit 550 coupled to the application processor 510, where the application processor 510 may include fuse trimming circuitry of embodiments of the present application; a system agent unit 570; bus controller unit 580; an integrated memory controller unit 540; a set or one or more coprocessors 520 which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a Static Random Access Memory (SRAM) unit 530; a Direct Memory Access (DMA) unit 560. In one embodiment, coprocessor 520 includes a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

In the drawings, some structural or methodological features may be shown in a particular arrangement and/or order. However, it should be understood that such a particular arrangement and/or ordering may not be required. Rather, in some embodiments, these features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of structural or methodological features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, may not be included or may be combined with other features. Moreover, various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some figures may not depict all of the components of a given system, method, or apparatus. Like reference numerals may be used to denote like features throughout the specification and figures.

In embodiments of the present application, for purposes of description, "multiplexer," "multiplexing," and the like may include "diplexer," "duplex," and the like.

The units/modules mentioned in the embodiments of the present application are all logic units/modules, and in physical terms, one logic unit/module may be a physical unit/module, or may be a part of a physical unit/module, or may be implemented by a combination of multiple physical units/modules, where the physical implementation manner of these logic units/modules is not the most important, and the combination of functions implemented by these logic units/modules is the key to solve the technical problem posed by the present application. Furthermore, in order to highlight the innovative part of the present application, the above-described device embodiments of the present application do not introduce units/modules that are less closely related to solving the technical problems posed by the present application, which does not indicate that the above-described device embodiments do not have other units/modules.

In embodiments of the present application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims (20)

1. A chip comprising a fuse trimming circuit, wherein the fuse trimming circuit comprises a fuse read path, a fuse write path, and a switch control unit;

the fuse read path includes a first fuse resistor, a common gate amplifier unit, an inverter transmission unit, a latch unit, and at least one switch unit;

in the power-on process of the chip, the switch control unit conducts the fuse reading path and determines a first logic signal passing through the first fuse resistor; after the chip is powered on, the switch control unit closes the fuse reading passage;

when the chip works normally, the fuse burning passage is disconnected when the chip does not need to be burned;

when the chip works normally, the fuse burning passage is conducted to blow the first fuse resistor when the chip is burnt.

2. The chip of claim 1, comprising: the common gate amplifier unit is used for determining the first logic signal according to the fusing state of the first fuse resistor;

the inverter transmission unit is connected with the common gate amplifier unit and is used for inverting the first logic signal to obtain a second logic signal;

the latch unit is connected with the inverter transmission unit and is used for latching the second logic signal.

3. The chip of claim 2, wherein the switching unit comprises a first switching unit, a second switching unit, and a third switching unit, wherein the first switching unit comprises a first switching tube, the second switching unit comprises a second switching tube, and the third switching unit comprises a third switching tube.

4. The chip of claim 3, wherein the common-gate amplifier unit comprises a fourth switching tube, a fifth switching tube, a sixth switching tube, and a seventh switching tube, wherein gates of the fourth switching tube and the fifth switching tube are connected to a first node, gates of the sixth switching tube and the seventh switching tube are connected to a second node, an input terminal of the fifth switching tube and the first fuse resistor are connected to a third node, and an output terminal of the fifth switching tube and an input terminal of the seventh switching tube are connected to a fourth node.

5. The chip of claim 4, wherein the inverter transmission unit comprises an eighth switching tube and a ninth switching tube, wherein an output terminal of the eighth switching tube and an input terminal of the ninth switching tube are connected to a fifth node.

6. The chip of claim 5, further comprising: the switch control unit is used for generating a first switch signal, a second switch signal and a third switch signal according to signals in the power-on process of the chip.

7. The chip of claim 6, wherein when the first switching signal is at a low level, the first switching transistor of the first switching unit is turned on, the second switching signal is at a high level, the second switching transistor of the second switching unit is turned on, the third switching signal is at a low level, and the third switching transistor of the third switching unit is turned off.

8. The chip of claim 7, wherein when the first and second switching transistors of the first switching unit are turned on, the first node is high, the second node is low, and the fifth and seventh switching transistors are turned off, such that the fuse read path is closed.

9. The chip of claim 8, wherein when a third switching tube of the third switching unit is turned off, an eighth switching tube and a ninth switching tube of the inverter transmission unit are turned off such that the fourth node is disconnected from the fifth node.

10. The chip of claim 9, further comprising: the control fuse burning unit is used for controlling and burning the first fuse resistor, wherein the control fuse burning unit comprises a tenth switching tube and a first resistor, the input end of the tenth switching tube and the first fuse resistor are connected to the third node, and the first fuse resistor and the tenth switching tube form a fuse burning passage.

11. The chip of claim 10, wherein the tenth switching tube is turned off when a fuse burning signal is not applied to a gate of the tenth switching tube, such that the fuse burning path is turned off, and wherein the tenth switching tube is turned on when a fuse burning signal is applied to a gate of the tenth switching tube, and wherein the first fuse resistor is burned.

12. The chip of claim 6, wherein during power-up of the chip, the first, second and third inverters of the signal adjustment unit adjust the first switching signal to a high level, the first switching tube of the first switching unit is turned off, the second switching signal is adjusted to a low level, the second switching tube of the second switching unit is turned off, the third switching signal is adjusted to a high level, and the third switching tube of the third switching unit is turned on.

13. The chip of claim 12, wherein when the first switching tube and the second switching tube of the first switching unit are turned off, the first node is at a low level, the second node is at a high level, and the first fuse resistor, the fifth switching tube and the seventh switch Guan Xingcheng are in a first path, so that logic signals of the third node and the fourth node are the same, and the first logic signal corresponding to the fourth node is obtained.

14. The chip of claim 13, wherein when a third switching tube of the third switching unit is turned on, an eighth switching tube and a ninth switching tube of the inverter transmission unit are turned on, so that the first logic signal is transmitted from the fourth node to the fifth node, and a latch unit holds the second logic signal corresponding to the fifth node, wherein the second logic signal has a logic value opposite to that of the first logic signal.

15. The chip of claim 8, further comprising: and the bias current source comprises an eleventh switching tube, and the gates of the eleventh switching tube, the sixth switching tube and the seventh switching tube are connected with the second node.

16. The chip of claim 15, further comprising: a reference resistance unit, the reference resistance unit comprising: the switching device comprises a first reference resistor, a second reference resistor and a twelfth switching tube, wherein the second reference resistor is connected with the input end of the fourth switching tube.

17. The chip of claim 16, wherein in a test mode, when the first and second switching transistors of the first switching unit are turned off, the twelfth switching transistor is turned on, the bias current source, the first fuse resistor, the fifth switching transistor, and the seventh switching transistor Guan Xingcheng form a third path, the bias current source, the reference resistor unit, the fourth switching transistor, and the sixth switching transistor form a fourth path, wherein the third path and the fourth path flow a first bias current and a second bias current, respectively, the first bias current and the second bias current being the same.

18. The chip of claim 17, wherein when the voltage of the gate of the twelfth switching transistor is high, the blow threshold of the first fuse resistor is a sum of resistance values of the first reference resistor and the second reference resistor.

19. The chip of claim 18, wherein the first fuse resistance has a blow threshold value that is a resistance value of the first reference resistance when a voltage of a gate of the twelfth switching transistor is low.

20. An electronic device comprising the chip of any one of claims 1-19.