CN116741253A - Memory failure test method and device, storage medium and electronic equipment - Google Patents

Abstract

The disclosure relates to a memory failure testing method, a memory failure testing device, a computer readable storage medium and electronic equipment, and relates to the technical field of integrated circuits. The memory failure test method comprises the following steps: performing accelerated aging treatment on the memory, and writing second storage data into a storage array of the memory; reading the data in the storage array to obtain a reading result; comparing the second stored data with the read result to obtain a comparison result; and judging the memory according to the comparison result.

Description

Memory failure test method and device, storage medium and electronic equipment

Technical Field

The present disclosure relates to the technical field of integrated circuits, and in particular, to a memory failure test method, a memory failure test device, a computer readable storage medium, and an electronic apparatus.

Background

The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, and has been widely used in the computer field and the electronic industry due to its advantages of simple structure, high density, low power consumption, low price, etc.

In general, as processes advance, DRAM presents a number of problems. For example, by-product drop causes structural problems such as shorting, capacitor collapse, wire breakage, critical dimension failure, etc., which are required to be screened out during yield testing.

Therefore, in order to improve the yield in the DRAM process, it is important to develop an effective memory failure test method.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to provide a memory failure testing method, a memory failure testing device, a computer readable storage medium and an electronic device.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the application.

According to a first aspect of the present disclosure, there is provided a memory failure test method, including: performing accelerated aging processing on the memory, wherein the accelerated aging processing comprises: writing first storage data in a storage array of the memory; controlling the memory to enter an aging mode, and starting a multiple word line function; activating a preset word line of the memory according to the multi-word line function, exiting the aging mode after a preset acceleration test time, and closing the multi-word line function; repeating the accelerated aging process until all word lines are activated and ending the accelerated aging process; writing second storage data in a storage array of the memory; reading the data in the storage array to obtain a reading result; comparing the second stored data with the read result to obtain a comparison result; and judging the memory according to the comparison result.

In an exemplary embodiment of the present disclosure, the first stored data is leakage topology data.

In an exemplary embodiment of the present disclosure, the first stored data is wrap 0 topology data or wrap 1 topology data.

In an exemplary embodiment of the present disclosure, the second stored data includes: topology data of alternating high and low voltages.

In one exemplary embodiment of the present disclosure, when the multiple word line function is a full word line function, the preset word lines are all word lines; and performing the accelerated aging treatment once, and ending the accelerated aging treatment after all word lines are activated.

In one exemplary embodiment of the present disclosure, when the multiple word line function is a 1/2 word line function, the preset word line is a first group 1/2 word line or a second group 1/2 word line; and performing the accelerated aging treatment twice, and ending the accelerated aging treatment after all word lines are activated.

In one exemplary embodiment of the present disclosure, when the multiple word line function is a 1/4 word line function, the preset word line is a first group 1/4 word line, a second group 1/4 word line, a third group 1/4 word line, or a fourth group 1/4 word line; and performing the accelerated aging treatment four times, and ending the accelerated aging treatment after all word lines are activated.

In one exemplary embodiment of the present disclosure, when the multiple word line function is a 1/8 word line function, the preset word line is a first group 1/8 word line, a second group 1/8 word line, a third group 1/8 word line, a fourth group 1/8 word line, a fifth group 1/8 word line, a sixth group 1/8 word line, a seventh group 1/8 word line, or an eighth group 1/8 word line; and performing the accelerated aging treatment eight times, and ending the accelerated aging treatment after all word lines are activated.

In one exemplary embodiment of the present disclosure, when the multiple word line function is a 1/16 word line function, the preset word line is a first group 1/16 word line, a second group 1/16 word line, a third group 1/16 word line, a fourth group 1/16 word line, a fifth group 1/16 word line, a sixth group 1/16 word line, a seventh group 1/16 word line, an eighth group 1/16 word line, a ninth group 1/16 word line, a tenth group 1/16 word line, an eleventh group 1/16 word line, a twelfth group 1/16 word line, a thirteenth group 1/16 word line, a fourteenth group 1/16 word line, a fifteenth group 1/16 word line, or a sixteenth group 1/16 word line; and performing the accelerated aging treatment for sixteen times, and ending the accelerated aging treatment after all word lines are activated.

In one exemplary embodiment of the present disclosure, the preset acceleration test time is an activation-to-precharge time of the word line.

In an exemplary embodiment of the present disclosure, determining the memory according to the comparison result includes: when the comparison results are the same, judging that the operation is not invalid; and when the comparison results are different, judging that the device is invalid.

In an exemplary embodiment of the present disclosure, the type of failure includes: word line failure, bit line failure, word line to bit line intersection failure, bit line to word line contact hole shorting, or adjacent capacitance shorting.

In an exemplary embodiment of the present disclosure, further comprising: the memory is initialized prior to the accelerated aging process.

According to a second aspect of the present disclosure, there is provided a memory failure test apparatus comprising: the control module is used for performing accelerated aging treatment on the memory, and the accelerated aging treatment comprises the following steps: writing first storage data in a storage array of the memory; controlling the memory to enter an aging mode, and starting a multiple word line function; activating a preset word line of the memory according to the multi-word line function, exiting the aging mode after a preset acceleration test time, and closing the multi-word line function; repeating the accelerated aging process until all word lines are activated and ending the accelerated aging process; a second data writing module for writing second storage data in a storage array of the memory; the data reading module is used for reading the data in the storage array to obtain a reading result; the comparison module is used for comparing the second stored data with the read result to obtain a comparison result; and the judging module is used for judging the memory according to the comparison result.

In one exemplary embodiment of the present disclosure, the control module includes: a first data writing module for writing first storage data in a storage array of the memory; the control submodule is used for controlling the memory to enter an aging mode and starting a multiple word line function; activating a preset word line of the memory according to the multi-word line function, exiting the aging mode after a preset acceleration test time, and closing the multi-word line function; the accelerated aging process is repeated until the accelerated aging process is ended after all word lines are activated.

According to a third aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the above-described memory failure test method.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described memory failure test method via execution of the executable instructions.

The technical scheme provided by the disclosure can comprise the following beneficial effects:

in the exemplary embodiment of the disclosure, on one hand, by performing accelerated aging processing on a memory, the aging process of the memory can be accelerated, functional aging can occur in advance on a memory with problems, errors can occur in the later data writing and reading processes, and whether the memory fails can be determined through a comparison result, so that the memory is used in failure test of the memory; on the other hand, by writing the first storage data in the storage array of the memory and controlling the memory to enter the aging mode, the aging process of the memory can be accelerated, and the test cost is saved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort. In the drawings:

fig. 1 schematically illustrates a schematic structure of a memory cell in a DRAM according to an exemplary embodiment of the present disclosure;

FIG. 2 schematically illustrates a schematic structure of a memory array in a DRAM according to an exemplary embodiment of the present disclosure;

FIG. 3 schematically illustrates a flow chart of a method of memory failure testing according to an exemplary embodiment of the present disclosure;

FIG. 4 schematically illustrates a flowchart of a process for accelerated aging of memory according to an exemplary embodiment of the present disclosure;

FIG. 5 schematically illustrates a flow diagram of a memory failure test method according to an exemplary embodiment of the present disclosure;

FIG. 6 schematically illustrates a block diagram of a memory failure testing apparatus according to an exemplary embodiment of the present disclosure;

fig. 7 schematically illustrates a block diagram of an electronic device according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.

Semiconductor memories are used in computers, servers, hand-held devices such as mobile phones, printers, and many other electronic devices and applications. The semiconductor memory includes a plurality of memory cells in a memory array, each memory cell storing at least one bit of information. DRAM is an example of such a semiconductor memory. The scheme is preferably used in DRAM. Accordingly, the following description of the embodiments is made with reference to DRAM as a non-limiting example.

In DRAM integrated circuit devices, an array of memory cells is typically arranged in rows and columns such that a particular memory cell can be addressed by designating a row and column of its array. The word lines connect the rows to bit line sense amplifiers that detect the data in the cells. Then in a read operation, a subset of the data in the sense amplifier is selected or "column selected" for output.

Referring to fig. 1, each memory cell 100 in a dram generally includes a capacitor 110, a transistor 120, a Word Line (WL) 130, and a Bit Line (BL) 140, a gate of the transistor 120 is connected to the Word Line 130, a drain of the transistor 120 is connected to the Bit Line 140, a source of the transistor 120 is connected to the capacitor 110, and a voltage signal on the Word Line 130 can control the transistor 120 to be turned on or off, thereby reading data information stored in the capacitor 110 through the Bit Line 140, or writing data information into the capacitor 110 through the Bit Line 140 for storage.

For a memory array, it is generally composed of a plurality of memory cells, and a plurality of word lines WL in the memory array are arranged at intervals. Referring to fig. 2, the DRAM may generate a voltage difference between word lines WL during long-term use. For example, the voltage of the word line WL is H, and the voltage of the word line WL is L. Since the voltage difference causes leakage between word lines WL, a data read/write error occurs, resulting in a memory failure.

Therefore, the failure test is performed on the memory, and the accelerated test is performed on the memory at the initial stage of the memory to detect the memory which is possibly failed, so that the product yield can be improved.

The memory failure test method provided by the exemplary embodiment of the present disclosure, referring to fig. 3, may include the steps of:

step S310, performing accelerated aging processing on the memory, wherein the accelerated aging processing comprises: writing first storage data in a storage array of a memory; controlling the memory to enter an aging mode, and starting a multiple word line function; activating a preset word line of the memory according to the multiple word line function, exiting the aging mode after a preset acceleration test time, and closing the multiple word line function;

step S320, repeating the accelerated aging process until all word lines are activated, and ending the accelerated aging process;

step S330, writing second storage data into a storage array of the memory;

step S340, reading data in the storage array to obtain a reading result;

step S350, comparing the second stored data with the read result to obtain a comparison result;

step S360, judging the memory according to the comparison result.

In the method for testing the failure of the memory provided by the exemplary embodiment of the disclosure, on one hand, the aging process of the memory can be accelerated by performing the accelerated aging process on the memory, the functional aging can occur in advance for the memory with problems, errors can occur in the later data writing and reading processes, and whether the memory fails or not can be determined by comparing the results, so that the method is used in the failure test of the memory; on the other hand, by writing the first storage data in the storage array of the memory and controlling the memory to enter the aging mode, the aging process of the memory can be accelerated, and the test cost is saved.

In an exemplary embodiment of the present disclosure, referring to fig. 4, in the process of performing accelerated aging processing on a memory, the method may specifically include the following steps:

step S410, writing first storage data in a storage array of a memory;

step S420, controlling the memory to enter an aging mode and starting a multiple word line function;

step S430, according to the multiple word line function, activating the preset word line of the memory, exiting the burn-in mode after the preset acceleration test time, and turning off the multiple word line function.

In step S410, the first stored data written in the memory array of the memory may be a type of leakage topology data, for example, around 0 topology data SUR0 as shown in tables 1-1 to 1-4 or around 1 topology data SUR1 as shown in tables 2-1 to 2-4.

TABLE 1-1

SUR0_0	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	1	0	1	0	1	0	1	0
BL1	0	0	0	0	0	0	0	0
									BL2	1	0	1	0	1	0	1	0
BL3	0	0	0	0	0	0	0	0
									BL4	1	0	1	0	1	0	1	0
BL5	0	0	0	0	0	0	0	0
									BL6	1	0	1	0	1	0	1	0
BL7	0	0	0	0	0	0	0	0

TABLE 1-2

Tables 1 to 3

SUR0_2	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	1	0	1	0	1	0	1
BL1	0	0	0	0	0	0	0	0
									BL2	0	1	0	1	0	1	0	1
BL3	0	0	0	0	0	0	0	0
									BL4	0	1	0	1	0	1	0	1
BL5	0	0	0	0	0	0	0	0
									BL6	0	1	0	1	0	1	0	1
BL7	0	0	0	0	0	0	0	0

Tables 1 to 4

SUR0_3	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	0	0	0	0	0	0
BL1	0	1	0	1	0	1	0	1
									BL2	0	0	0	0	0	0	0	0
BL3	0	1	0	1	0	1	0	1
									BL4	0	0	0	0	0	0	0	0
BL5	0	1	0	1	0	1	0	1
									BL6	0	0	0	0	0	0	0	0
BL7	0	1	0	1	0	1	0	1

TABLE 2-1

TABLE 2-2

SUR1_1	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	1	1	1	1	1	1	1	1
BL1	0	1	0	1	0	1	0	1
									BL2	1	1	1	1	1	1	1	1
BL3	0	1	0	1	0	1	0	1
									BL4	1	1	1	1	1	1	1	1
BL5	0	1	0	1	0	1	0	1
									BL6	1	1	1	1	1	1	1	1
BL7	0	1	0	1	0	1	0	1

Tables 2 to 3

SUR1_2	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	1	0	1	0	1	0	1	0
BL1	1	1	1	1	1	1	1	1
									BL2	1	0	1	0	1	0	1	0
BL3	1	1	1	1	1	1	1	1
									BL4	1	0	1	0	1	0	1	0
BL5	1	1	1	1	1	1	1	1
									BL6	1	0	1	0	1	0	1	0
BL7	1	1	1	1	1	1	1	1

Tables 2 to 4

As can be seen from tables 1-1 through 1-4, each data 1 is surrounded by data 0, so that a high level and a low level can be formed between the word lines WL, and the leakage opportunity can be provided for the aging of the memory, and the aging process of the memory can be accelerated. Similarly, in tables 2-1 to 2-4, data 1 surrounds each data 0, and high and low levels can be formed between word lines WL, so that the aging process of the memory can be accelerated.

In exemplary embodiments of the present disclosure, after writing first stored data in a memory array of a memory, the memory may be controlled to enter an burn-in mode. Specifically, controlling the memory to enter the burn-in mode may include: raising the power supply voltage VDD, for example, raising the power supply voltage VDD from 1.1V to 1.5V; the word line voltage VWLP is raised, for example, from 3.0V to 3.7V. By increasing the power supply voltage, the word line voltage, or the like, the aging speed in the memory can be increased, and the memory can be brought into an aged state as soon as possible.

It should be noted that, in practical applications, the method for controlling the memory to enter the aging mode includes, but is not limited to, the above-described method, and the exemplary embodiment of the present disclosure is not limited thereto.

In the exemplary embodiments of the present disclosure, in addition to controlling the memory to enter the burn-in mode, it is necessary to turn on the multiple word line function, which is a function of a multiple word line turn-on mode. According to different requirements, ALL Word lines, namely an ALL Word Line function (ALL MWL, ALL Multi-Word Line), a 1/2 Word Line function (1/2 MWL), a 1/4 Word Line function (1/4 MWL), a 1/8 Word Line function (1/8 MWL), a 1/16 Word Line function (1/16 MWL) and the like can be selected to be opened, wherein the ALL Word Line function, the 1/2 Word Line function, the 1/4 Word Line function, the 1/8 Word Line function and the 1/16 Word Line function belong to the multiple Word Line function.

The preset word line of the memory to be selected for activation is different according to the multiple word line function. The number of times of the accelerated aging process to be repeated is also different according to the difference of the preset word lines until the accelerated aging process is finished after all the word lines are activated.

That is, when the multiple word line function is the full word line function, the predetermined word lines are all word lines; and performing one time of accelerated aging treatment, and ending the accelerated aging treatment after all word lines are activated. Namely, under the full word line function, the aging treatment is only accelerated once.

When the multi-word line function is a 1/2 word line function, the preset word lines are a first group of 1/2 word lines or a second group of 1/2 word lines; after the first group of 1/2 word lines wait for a preset accelerated test time to finish one accelerated aging process, the second group of 1/2 word lines also need to finish one accelerated aging process, and the accelerated aging process is performed twice in total until all word lines are activated and then the accelerated aging process is finished.

Corresponding to the case where the multiple word line function is the 1/2 word line function, first, the accelerated aging process is performed on the first group of 1/2 word lines: namely writing first storage data in a storage array of the memory; controlling the memory to enter an aging mode, and starting a multiple word line function; activating a first group of 1/2 word lines of the memory according to the multiple word line function, exiting the aging mode after a preset acceleration test time, and closing the multiple word line function; then, performing an accelerated aging process on the second group of 1/2 word lines, i.e., writing the first stored data in the memory array of the memory; controlling the memory to enter an aging mode, and starting a multiple word line function; according to the multiple word line function, a second group of 1/2 word lines of the memory are activated, the burn-in mode is exited after a preset acceleration test time, and the multiple word line function is turned off.

When the multiple word line function is a 1/4 word line function, the preset word lines may be a first group of 1/4 word lines, a second group of 1/4 word lines, a third group of 1/4 word lines, or a fourth group of 1/4 word lines; after the first group of 1/4 word lines wait for a preset accelerated test time to finish one accelerated aging process, the second group of 1/4 word lines also need to finish one accelerated aging process, then the third group of 1/4 word lines and the fourth group of 1/4 word lines finish the accelerated aging process sequentially, and the accelerated aging process is performed four times in total until all word lines are activated and then the accelerated aging process is finished.

When the multiple word line function is a 1/8 word line function, the preset word lines may be a first group 1/8 word line, a second group 1/8 word line, a third group 1/8 word line, a fourth group 1/8 word line, a fifth group 1/8 word line, a sixth group 1/8 word line, a seventh group 1/8 word line, or an eighth group 1/8 word line; after the first group of 1/8 word lines wait for the preset accelerated test time to finish one accelerated aging process, the second group of 1/8 word lines also need to finish one accelerated aging process, then the third group of 1/8 word lines, the fourth group of 1/8 word lines, the fifth group of 1/8 word lines, the sixth group of 1/8 word lines, the seventh group of 1/8 word lines and the eighth group of 1/8 word lines finish the accelerated aging process sequentially, and the accelerated aging process is finished after all word lines are activated for eight times.

When the multiple word line function is a 1/16 word line function, the preset word lines may be a first group 1/16 word line, a second group 1/16 word line, a third group 1/16 word line, a fourth group 1/16 word line, a fifth group 1/16 word line, a sixth group 1/16 word line, a seventh group 1/16 word line, an eighth group 1/16 word line, a ninth group 1/16 word line, a tenth group 1/16 word line, an eleventh group 1/16 word line, a twelfth group 1/16 word line, a thirteenth group 1/16 word line, a fourteenth group 1/16 word line, a fifteenth group 1/16 word line, or a sixteenth group 1/16 word line; after the first group of 1/16 word lines waits for the preset accelerated test time to complete the accelerated aging process once, the second group of 1/16 word lines also needs to complete the accelerated aging process once, then the third group of 1/16 word lines, the fourth group of 1/16 word lines, the fifth group of 1/16 word lines, the sixth group of 1/16 word lines, the seventh group of 1/16 word lines, the eighth group of 1/16 word lines, the ninth group of 1/16 word lines, the tenth group of 1/16 word lines, the eleventh group of 1/16 word lines, the twelfth group of 1/16 word lines, the thirteenth group of 1/16 word lines, the fourteenth group of 1/16 word lines, the fifteenth group of 1/16 word lines and the sixteenth group of 1/16 word lines complete the accelerated aging process sequentially, and the accelerated aging process is performed for sixteenth times in total until all word lines are activated.

By activating the preset word line, memory aging can be accelerated within a preset acceleration test time. After exiting the burn-in mode, the multiple word line function needs to be turned off to complete the accelerated burn-in process.

In practical applications, the above-mentioned preset acceleration test time may be determined according to practical situations, for example, the preset acceleration test time may be an Active to Precharge time of the word line, that is, a time from on to off of the word line.

In exemplary embodiments of the present disclosure, after the accelerated aging process is completed on the memory, write and read operations may be performed on the memory to determine whether there is a failure of the memory.

In particular, the second storage data may be written in a storage array of the memory, where the second storage data may be determined according to the actual situation. In an exemplary embodiment of the disclosure, the second storage data may be topology data with alternately distributed high and low voltages, and after the second storage data is written, the data written between adjacent storage units of the storage array are different, so that it is ensured that a potential difference exists between the adjacent storage units, and it is beneficial to determine whether a leakage risk exists between the storage units.

Topology data of a high-low voltage alternate distribution is shown with reference to tables 3-1 to 3-2:

TABLE 3-1

TABLE 3-2

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	1	0	1	0	1	0	1
BL1	1	0	1	0	1	0	1	0
									BL2	0	1	0	1	0	1	0	1
BL3	1	0	1	0	1	0	1	0
									BL4	0	1	0	1	0	1	0	1
BL5	1	0	1	0	1	0	1	0
									BL6	0	1	0	1	0	1	0	1
BL7	1	0	1	0	1	0	1	0

The data between adjacent memory cells are different in either the table 3-1 or the table 3-2, so that a layout form with alternately distributed high and low voltages is generated, and if a failure cell or a failure part exists in the memory, the risk of electric leakage is necessarily existed, so that the failure can be conveniently detected.

In an exemplary embodiment of the disclosure, after writing the second storage data in the storage array, the data in the storage array may be read, to obtain a read result. The writing and reading are performed in the same order, for example, writing of data or reading of data in the column direction.

After the reading result is obtained, the second stored data and the reading result can be compared to obtain a comparison result, and the memory is judged according to the comparison result to determine whether the memory has failure or not. When the comparison results are the same, the memory can be judged to be not invalid; when the comparison result is different, the memory can be judged to be invalid.

In practice, the types of memory failures may be varied, such as word line failure, bit line failure, word line to bit line intersection failure, bit line to word line contact hole short, or adjacent capacitor short, etc. And the types of failures may be determined based on the chip map layout of the memory. Specifically, according to the failure condition of the capacitor arrangement, the failure condition is reflected in the array arrangement, and then a specific physical failure mechanism and failure type can be presumed by combining the knowledge or principle of an electrical scheme, and the failure type can be verified by a Scanning Electron Microscope (SEM) or a projection electron microscope (TEM).

It should be further noted that, in the memory failure test method provided in the embodiment of the present disclosure, before the memory is subjected to the accelerated aging process, the memory needs to be further subjected to an initialization process, where the initialization process includes preparation of some instructions before the test, for example, preparation of clearing some residual instructions and testing voltage steps.

Referring to fig. 5, a flow schematic block diagram of a memory failure testing method of an embodiment of the present disclosure is shown. Firstly, initializing a memory before starting; then, an accelerated aging treatment stage is entered: writing first stored data, entering an aging mode, starting a multi-word line function, activating a preset word line and waiting for a preset acceleration test time, exiting the aging mode, and closing the multi-word line function; repeating the accelerated aging process according to the multiple word line function; secondly, writing second storage data in the storage array; further, reading the data; finally, a comparison result is obtained, and failure judgment is carried out.

In summary, according to the memory failure testing method provided by the exemplary embodiment of the present disclosure, by performing accelerated aging processing on the memory, the memory can be accelerated to an aging failure stage in advance, and then the second storage data is written in and read and compared, so that the failure condition of the memory can be determined, and a basis is provided for failure determination of the memory, thereby improving the yield of products.

It should be noted that although the steps of the method of the present application are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

In addition, in the present exemplary embodiment, a memory failure test apparatus is also provided. Referring to fig. 6, the memory failure test apparatus 600 may include: a control module 610, a second data writing module 620, a data reading module 630, a comparing module 640, and a determining module 650, wherein:

the control module 610 may be configured to perform an accelerated aging process on the memory, where the accelerated aging process includes: writing first storage data in a storage array of a memory; controlling the memory to enter an aging mode, and starting a multiple word line function; activating a preset word line of the memory according to the multiple word line function, exiting the aging mode after a preset acceleration test time, and closing the multiple word line function; repeating the accelerated aging process until all word lines are activated and ending the accelerated aging process;

a second data writing module 620, which may be used to write second storage data in the storage array of the memory;

the data reading module 630 may be configured to read data in the storage array to obtain a reading result;

the comparison module 640 may be configured to compare the second stored data with the read result to obtain a comparison result;

the determining module 650 may be configured to determine the memory according to the comparison result.

In an exemplary embodiment of the present disclosure, the control module 610 may include:

a first data writing module 611, which may be used to write first storage data in a storage array of the memory;

a control sub-module 612, which may be used to control the memory to enter an aging mode and turn on the multiple word line function; activating a preset word line of the memory according to the multiple word line function, exiting the aging mode after a preset acceleration test time, and closing the multiple word line function; the accelerated aging process is repeated until all word lines are activated, and the accelerated aging process is ended.

The control submodule 612 may be further configured to initialize the memory before performing the accelerated aging process on the memory.

The specific details of the virtual module of each memory failure testing apparatus are described in detail in the corresponding memory failure testing method, and therefore, will not be described herein.

It should be noted that although several modules or units of the memory failure testing apparatus are mentioned in the above detailed description, this division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

Those skilled in the art will appreciate that the various aspects of the application may be implemented as a system, method, or program product. Accordingly, aspects of the application may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.

An electronic device 700 according to this embodiment of the application is described below with reference to fig. 7. The electronic device 700 shown in fig. 7 is merely an example, and should not be construed as limiting the functionality and scope of use of embodiments of the present application.

As shown in fig. 7, the electronic device 700 is embodied in the form of a general purpose computing device. Components of electronic device 700 may include, but are not limited to: the at least one processing unit 710, the at least one storage unit 720, a bus 730 connecting the different system components (including the storage unit 720 and the processing unit 710), and a display unit 740.

Wherein the storage unit 720 stores program code that is executable by the processing unit 710 such that the processing unit 710 performs the steps according to various exemplary embodiments of the present application described in the above section of the "exemplary method" of the present specification. For example, the processing unit 710 may perform the steps as shown in fig. 3 and 4.

The memory unit 720 may include readable media in the form of volatile memory units, such as Random Access Memory (RAM) 7201 and/or cache memory 7202, and may further include Read Only Memory (ROM) 7203.

The storage unit 720 may also include a program/utility 7204 having a set (at least one) of program modules 7205, such program modules 7205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.

Bus 730 may be a bus representing one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 700 may also communicate with one or more external devices 770 (e.g., keyboard, pointing device, bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 700, and/or any device (e.g., router, modem, etc.) that enables the electronic device 700 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 750. Also, electronic device 700 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through network adapter 760. As shown, network adapter 760 communicates with other modules of electronic device 700 over bus 730. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 700, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, a computer-readable storage medium having stored thereon a program product capable of implementing the method described above in the present specification is also provided. In some possible embodiments, the various aspects of the application may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the application as described in the "exemplary methods" section of this specification, when said program product is run on the terminal device.

A program product for implementing the above-described method according to an embodiment of the present application may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The computer readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

Furthermore, the above-described drawings are only schematic illustrations of processes included in the method according to the exemplary embodiment of the present application, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (16)

1. A method for testing memory failure, comprising:

performing accelerated aging processing on the memory, wherein the accelerated aging processing comprises: writing first storage data in a storage array of the memory; controlling the memory to enter an aging mode, and starting a multiple word line function; activating a preset word line of the memory according to the multi-word line function, exiting the aging mode after a preset acceleration test time, and closing the multi-word line function;

repeating the accelerated aging process until all word lines are activated and ending the accelerated aging process;

writing second storage data in a storage array of the memory;

reading the data in the storage array to obtain a reading result;

comparing the second stored data with the read result to obtain a comparison result;

and judging the memory according to the comparison result.

2. The method of claim 1, wherein the first stored data is leakage topology data.

3. The memory failure test method of claim 2, wherein the first stored data is wrap-0 topology data or wrap-1 topology data.

4. The memory failure test method according to claim 1, wherein the second stored data includes: topology data of alternating high and low voltages.

5. The method of claim 1, wherein when the multiple word line function is a full word line function, the predetermined word lines are all word lines; and performing the accelerated aging treatment once, and ending the accelerated aging treatment after all word lines are activated.

6. The method of claim 1, wherein the predetermined word line is a first group of 1/2 word lines or a second group of 1/2 word lines when the multiple word line function is a 1/2 word line function; and performing the accelerated aging treatment twice, and ending the accelerated aging treatment after all word lines are activated.

7. The method of claim 1, wherein when the multiple word line function is a 1/4 word line function, the predetermined word line is a first group 1/4 word line, a second group 1/4 word line, a third group 1/4 word line, or a fourth group 1/4 word line; and performing the accelerated aging treatment four times, and ending the accelerated aging treatment after all word lines are activated.

8. The method of claim 1, wherein when the multiple word line function is a 1/8 word line function, the predetermined word line is a first group 1/8 word line, a second group 1/8 word line, a third group 1/8 word line, a fourth group 1/8 word line, a fifth group 1/8 word line, a sixth group 1/8 word line, a seventh group 1/8 word line, or an eighth group 1/8 word line; and performing the accelerated aging treatment eight times, and ending the accelerated aging treatment after all word lines are activated.

9. The memory failure test method according to claim 1, wherein when the multiple word line function is a 1/16 word line function, the preset word line is a first group 1/16 word line, a second group 1/16 word line, a third group 1/16 word line, a fourth group 1/16 word line, a fifth group 1/16 word line, a sixth group 1/16 word line, a seventh group 1/16 word line, an eighth group 1/16 word line, a ninth group 1/16 word line, a tenth group 1/16 word line, an eleventh group 1/16 word line, a twelfth group 1/16 word line, a thirteenth group 1/16 word line, a fourteenth group 1/16 word line, a fifteenth group 1/16 word line, or a sixteenth group 1/16 word line; and performing the accelerated aging treatment for sixteen times, and ending the accelerated aging treatment after all word lines are activated.

10. The method of claim 1, wherein the predetermined acceleration test time is an activation-to-precharge time of the word line.

11. The memory failure test method according to any one of claims 1 to 10, wherein determining the memory based on the comparison result includes:

when the comparison results are the same, judging that the operation is not invalid; and when the comparison results are different, judging that the device is invalid.

12. The memory failure test method of claim 11, wherein the type of failure comprises: word line failure, bit line failure, word line to bit line intersection failure, bit line to word line contact hole shorting, or adjacent capacitance shorting.

13. A memory failure testing apparatus, comprising:

the control module is used for performing accelerated aging treatment on the memory, and the accelerated aging treatment comprises the following steps: writing first storage data in a storage array of the memory; controlling the memory to enter an aging mode, and starting a multiple word line function; activating a preset word line of the memory according to the multi-word line function, exiting the aging mode after a preset acceleration test time, and closing the multi-word line function; repeating the accelerated aging process until all word lines are activated and ending the accelerated aging process;

a second data writing module for writing second storage data in a storage array of the memory;

the data reading module is used for reading the data in the storage array to obtain a reading result;

the comparison module is used for comparing the second stored data with the read result to obtain a comparison result;

and the judging module is used for judging the memory according to the comparison result.

14. The memory failure testing device of claim 13, wherein the control module comprises:

a first data writing module for writing first storage data in a storage array of the memory;

the control submodule is used for controlling the memory to enter an aging mode and starting a multiple word line function; activating a preset word line of the memory according to the multi-word line function, exiting the aging mode after a preset acceleration test time, and closing the multi-word line function; the accelerated aging process is repeated until the accelerated aging process is ended after all word lines are activated.

15. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the memory failure testing method of any of claims 1-12.

16. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the memory failure test method of any of claims 1-12 via execution of the executable instructions.