CN117012255A

CN117012255A - Memory testing method and testing system

Info

Publication number: CN117012255A
Application number: CN202210472928.4A
Authority: CN
Inventors: 第五天昊; 楚西坤; 刘�东
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2023-11-07
Also published as: WO2023206752A1

Abstract

The embodiment of the disclosure discloses a method and a system for testing a memory, wherein the method comprises the following steps: providing a memory, wherein the memory at least comprises a plurality of first storage units and a plurality of second storage units; reading data in a plurality of first storage units and updating the data in the plurality of first storage units into first data; reading data in a plurality of second storage units, and processing the read data to obtain first test data; and judging whether the second storage unit passes the first test or not according to the first test data. By the method, whether the memory unit and the peripheral circuit thereof are abnormal or not can be accurately judged.

Description

Memory testing method and testing system

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing technology, and relate to, but are not limited to, a method and a system for testing a memory.

Background

In the development and manufacturing of memories, a lot of testing of the memories is often required to determine whether anomalies are present that occur during the manufacturing process. For example, leakage or abnormal reading and writing due to short circuit, poor contact and the like of the circuit generated in the manufacturing process of the product. Because of the precise and complex structure of memory products, anomalies need to be identified through a series of electrical tests. However, the electrical testing of the memory is performed based on the read/write of the signal, so that some anomalies due to special reasons cannot be detected due to the testing method. Thus, there is a need for more reliable testing methods to accurately identify various types of anomalies.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a method and a system for testing a memory.

In a first aspect, an embodiment of the present disclosure provides a method for testing a memory, including:

providing a memory, wherein the memory at least comprises a plurality of first storage units and a plurality of second storage units;

reading data in a plurality of first storage units and updating the data in the plurality of first storage units into first data;

reading data in a plurality of second storage units, and processing the read data to obtain first test data;

and judging whether the second storage unit passes the first test or not according to the first test data.

In a second aspect, embodiments of the present disclosure further provide a test system for a memory, including:

a data reading unit for reading the data in the first storage unit and the second storage unit;

a data updating unit, configured to update data in the first storage unit to first data after reading the data in the first storage unit;

and the data testing unit is used for processing the read data to obtain test data, and judging whether the second storage unit passes the test or not through the test data.

According to the technical scheme, the storage units in the memory are divided into the first storage unit and the second storage unit, data in the first storage unit are read in the detection process, the data are updated after the data are read, and then the data of the second storage unit are read. Thus, whether the second memory cell is affected by the update data of the first memory cell can be effectively detected by the read data, so that whether the second memory cell passes the test can be judged, and problems such as leakage between the memory cells or between peripheral circuits can be further identified.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1A is a schematic diagram of a system according to an embodiment of the present disclosure;

FIG. 1B is a schematic diagram of a memory card according to an embodiment of the disclosure;

FIG. 1C is a schematic diagram of a Solid State Drive (SSD) according to an embodiment of the present disclosure;

FIGS. 1D and 1E are schematic diagrams illustrating a memory device including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

FIG. 2A is a flowchart showing a method for testing a memory according to an embodiment of the disclosure;

FIG. 2B is a schematic diagram of leakage between word lines and connected memory cells in a memory according to an embodiment of the disclosure;

FIG. 3A is a second flowchart of a method for testing a memory according to an embodiment of the disclosure;

fig. 3B to 3D are schematic diagrams of data change of each memory cell in the test method according to the embodiments of the present disclosure;

fig. 4A and fig. 4B are schematic diagrams illustrating a data processing of second stored data in the test method according to the embodiments of the present disclosure;

FIG. 5 is a third flowchart of a method for testing a memory according to an embodiment of the disclosure;

FIG. 6A is a schematic diagram illustrating data changes of other memory cells when a portion of the first memory cell data is maintained in the test method according to the embodiment of the present disclosure;

FIG. 6B is a schematic diagram of data processing in the test method provided in the embodiment of the disclosure in the case of FIG. 6A;

FIG. 6C is a schematic diagram illustrating the data change of each other memory cell while maintaining the data of the odd number of first memory cells unchanged in the test method according to the embodiment of the present disclosure;

FIG. 6D is a schematic diagram of data processing in the test method provided in the embodiment of the disclosure in the case of FIG. 6C;

Fig. 6E is a schematic diagram of data change of other memory cells in the case of maintaining constant first memory cell interval arrangement in the test method according to the embodiment of the present disclosure;

FIG. 7A is a schematic diagram illustrating data changes of other memory cells when a portion of the second memory cell data is maintained in the test method according to the embodiment of the present disclosure;

FIG. 7B is a schematic diagram of data processing in the test method provided in the embodiment of the disclosure in the case of FIG. 7A;

FIG. 7C is a schematic diagram illustrating the data change of each other memory cell while maintaining the data of the odd number of second memory cells unchanged in the test method according to the embodiment of the present disclosure;

FIG. 7D is a schematic diagram of data processing in the test method provided in the embodiment of the disclosure in the case of FIG. 7C;

fig. 7E is a schematic diagram of data change of other memory cells in the case of maintaining constant interval arrangement of the second memory cells in the test method according to the embodiment of the present disclosure;

FIG. 8A is a schematic diagram of writing initial data in the form of a "checkerboard" into a memory array in a test method provided by an embodiment of the present disclosure;

FIG. 8B is a schematic diagram of data change when an electrical leakage abnormality exists in the test method according to the embodiment of the present disclosure in the case of FIG. 8A;

FIG. 8C is a schematic diagram of data processing in the test method provided in the embodiment of the disclosure in the case of FIG. 8B;

FIG. 8D is a schematic diagram of data change when no leakage anomaly is present in the test method provided in the embodiment of the present disclosure in the case of FIG. 8A;

FIG. 8E is a schematic diagram of data processing in the test method provided in the embodiment of the disclosure in the case of FIG. 8D;

FIG. 9 is a schematic diagram of a memory test system according to an embodiment of the disclosure;

fig. 10 is a schematic structural diagram of a memory according to an embodiment of the disclosure.

Specific embodiments of the present disclosure have been shown by way of the above drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims. The technical scheme of the present disclosure is further elaborated below with reference to the drawings and examples.

As shown in fig. 1A, an exemplary electronic device system 10 is shown in an embodiment of the present disclosure, and the system 10 may include a host 20 and a storage system 30. Wherein system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having memory 34 therein; the host 20 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device.

In embodiments of the present disclosure, host 20 may be configured to send data to storage system 30 or receive data from storage system 30. Here, the storage system 30 may include a controller 32 and one or more memories 34. The Memory 34 may include, but is not limited to, NAND Flash Memory (NAND Flash Memory), vertical NAND Flash Memory (Vertical NAND Flash Memory), NOR Flash Memory (NOR Flash Memory), dynamic random access Memory (Dynamic Random Access Memory, DRAM), ferroelectric random access Memory (Ferroelectric Random Access Memory, FRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), phase change random access Memory (Phase Change Random Access Memory, PCRAM), resistive random access Memory (Resistive Random Access Memory, RRAM), nano random access Memory (Nano Random Access Memory, NRAM), and the like.

On the other hand, the controller 32 may be coupled to the memory 34 and the host 20 and used to control the memory 34. By way of example, the controller 32 may be designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium for use in an electronic device such as a personal computer, digital camera, mobile phone, or the like. In some embodiments, the controller may also be designed to operate in a high duty cycle environment, SSD, or embedded multimedia card (eMMC), which serves as a data storage and enterprise storage array for mobile devices such as smartphones, tablet computers, laptop computers, and the like. Further, the controller may manage data in the memory and communicate with the host. The controller may be configured to control memory read, erase, and program operations; may also be configured to manage various functions with respect to data stored or to be stored in memory, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and may also be configured to process Error Correction Codes (ECC) with respect to data read from or written to the memory. In addition, the controller may perform any other suitable function, such as formatting the memory, or communicating with an external device (e.g., host 20 in FIG. 1A) according to a particular communication protocol. Illustratively, the controller may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

In the disclosed embodiments, the controller and the one or more memories may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system may be implemented and packaged into different types of terminal electronics. As shown in fig. 1B, the controller 32 and the single memory 34 may be integrated into a memory card 40. The memory card 40 may include a PC card (PCMCIA, personal computer memory card international association), CF card, smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, mmcmmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 may also include a memory card connector 42 that couples the memory card 40 with a host (e.g., the host 20 in fig. 1A). In another embodiment as shown in fig. 1C, the controller 32 and the plurality of memories 34 may be integrated into the SSD 50. SSD 50 may also include SSD connector 52 that couples SSD 50 with a host (e.g., host 20 in FIG. 1A). In some embodiments, the storage capacity and/or operating speed of SSD 50 is greater than the storage capacity and/or operating speed of memory card 40.

It should be noted that, the memory according to the embodiments of the present disclosure may be a semiconductor memory, which is a solid-state electronic device that is manufactured by using a semiconductor integrated circuit process and stores data information. Illustratively, FIG. 1D is a schematic diagram of an alternative memory 60 in an embodiment of the present disclosure. The memory 60 may be the memory 34 of fig. 1A to 1C. As shown in fig. 1D, the memory 60 may be composed of a memory cell array 62, a peripheral circuit 64 coupled to the memory cell array 62, and the like. The memory cell array 62 may be a NAND flash memory cell array, a DRAM memory cell array including word lines and bit lines, MOS devices, and storage capacitors, or the like.

In the embodiment of the present disclosure, the peripheral circuit 64 may be coupled to the memory cell array 62 through Bit Lines (BL), word Lines (WL), and Source lines (Source Line). Here, the peripheral circuitry 64 may include any suitable analog, digital, and mixed signal circuitry for facilitating operation of the memory cell array by applying and sensing voltage signals and/or current signals to and from each target memory cell via bit lines, word lines, and the like. Furthermore, it is possible to provide a device for the treatment of a disease. The peripheral circuits may also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. Illustratively, as shown in fig. 1E. The peripheral circuit 70 includes a Page Buffer/sense amplifier 71, a column decoder/bit line driver 72, a row decoder/word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. It should be appreciated that the peripheral circuitry 70 described above may be identical to the peripheral circuitry 64 in fig. 1D, and in other embodiments, the peripheral circuitry 70 may also include additional peripheral circuitry not shown in fig. 1E.

In the production process of semiconductor memories, it is often necessary to perform tests at various stages, and to find various anomalies in the production process in time, so as to facilitate various on-line processes such as reworking (Rework), repair (Repair), and determination of product grades.

The embodiment of the disclosure provides a method for testing a memory, which may be implemented by a peripheral circuit in the memory, a controller in the memory system, or a processor in an externally connected host system, or a device dedicated to testing for probe testing (circuit probe test).

The embodiment of the present disclosure is described by taking a DRAM as an example, but practical application is not limited thereto, and it is understood that the test method in the embodiment of the present disclosure may be applied to any kind of test of a memory.

As shown in fig. 2A, an embodiment of the present disclosure provides a method for testing a memory, including:

step S101, providing a memory, which at least comprises a plurality of first memory units and a plurality of second memory units;

step S102, reading data in a plurality of first storage units and updating the data in the plurality of first storage units into first data;

Step S103, reading data in a plurality of second storage units, and processing the read data to obtain first test data;

step S104, judging whether the second storage unit passes the first test or not according to the first test data.

The memory may be a semiconductor memory, which is a solid-state electronic device fabricated using semiconductor integrated circuit technology that stores data information. The memory may include a plurality of memory planes, and each memory plane may further include a plurality of memory blocks, each memory block being formed by a plurality of memory cells arranged in an array. Each memory cell may be connected to a peripheral circuit through a word line and a bit line, and perform operations of reading, writing, and sensing based on signal control of the peripheral circuit.

In the embodiment of the disclosure, the first memory cells and the second memory cells are respectively plural, and the plural first memory cells may be memory cells located on the same word line. The plurality of second memory cells may be memory cells on the same word line. In practical application, the memory cells on two groups of word lines which are easy to leak can be divided into a first memory cell and a second memory cell according to the design structure of the product. For example, in one memory area, 8 word lines WL0 to WL7 and 8 word lines WL8 to WL15 may be shorted due to the common control element, and thus leakage may occur, as shown in fig. 2B (the memory cell and its wiring structure are only schematic and do not represent the actual connection structure). Then, each memory cell to which WL0 to WL7 are connected respectively may be taken as a first memory cell, that is, eight first memory cells, and each memory cell to which WL8 to WL15 are connected respectively may be taken as a second memory cell, that is, eight second memory cells.

Therefore, the memory cells in the memory are divided into the above-described two types of the first memory cell and the second memory cell. The first memory cell is not structurally or functionally different from the second memory cell, but rather is intended to employ different operations in the testing process of the disclosed embodiments. Of course, in some embodiments, the memory may also include a third memory location and a fourth memory location.

In the detection process, the data in the first storage unit can be read, and the data in the first storage unit is updated to be the first data after the data are read. The first data may be different from the initial data in the first memory cell. For example, the first memory cell is read with data "1", and then updated to data "0" after reading, and the first memory cell is read with data "0", and then updated to data "1" after reading.

Note that, if there is a leakage or the like between the first storage unit and the second storage unit, the data stored in the second storage unit and the first storage unit may always coincide. If it is judged whether or not the data is consistent with the pre-stored data by only reading the data of the first storage unit and the second storage unit, there may be a case of missed detection. For example, if the pre-stored data is all "1", the read data is also all "1", and at this time, the problem of leakage between the first memory cell and the second memory cell cannot be determined.

Therefore, the purpose of the data update of the first memory cell is to reflect the leakage effect of the first memory cell when the data of the second memory cell is read later.

It will be appreciated that the reading step of the second memory cell requires that after the first memory cell reads and updates the data, the effect of the data after updating the first memory cell on the second memory cell can be detected.

For the second memory cell, only the data may be read without data update, and then the first test data is obtained from the read data to determine whether the second memory cell passes the first test.

For example, the data pre-stored in the first storage unit and the second storage unit are both "0", after the first storage unit is read, the data in the first storage unit is updated to "1", at this time, if there is leakage current between the second storage unit and the first storage unit, so that the data after the first storage unit is rewritten is also written into the second storage unit, the result obtained by reading the second storage unit is also "1". Thus, the presence of an abnormality can be identified.

According to the technical scheme, the storage units in the memory are divided into the first storage unit and the second storage unit, data in the first storage unit are read in the detection process, the data are updated after the data are read, and then the data of the second storage unit are read. Thus, whether the second memory cell is affected by the update data of the first memory cell can be effectively detected by the read data, whether the second memory cell can pass the first test can be further judged, and problems such as leakage between the memory cells or between peripheral circuits can be identified.

In some embodiments, as shown in fig. 3A, in step S104, the step of passing the first test data to determine whether the second memory cell passes the first test includes:

step S201, according to the first test data, determining whether the read data simultaneously comprises the first data and the initial data in the second storage unit;

step S202, if yes, the first test is not passed;

step S203, if not, means that the first test is passed, and the second test is continued.

In the embodiment of the disclosure, if the data in the read second storage unit are all initial data, it is indicated that the second storage unit is not affected in the process of updating the data in the first storage unit; if the read data includes the first data, it is indicated that the initial data in the second memory cell is synchronously rewritten into the first data due to the leakage.

In the embodiment of the disclosure, whether the read data includes the first data and the initial data at the same time can be detected through the first test, and because the initial data and the updated first data have different rules or characteristics, after the data is processed through the first test, whether the read data accords with the rules or characteristics of the initial data can be judged according to the obtained first test data. For example, the initial data are all the same data, such as all "0" or all "1" data, and after the data processing (such as the exclusive or operation and other processing) of the first test, a result reflecting whether the read data are all the same can be obtained, for example, if the first test data are logic "1", it is indicated that the read data include different data, so that the rule of the initial data is not met, and thus it can be determined that the read data include the initial data and the first data at the same time. Therefore, the second memory cell and the peripheral circuit connected thereto have problems such as leakage.

For example, as shown in fig. 3B to 3D, it is assumed that 16 memory cells to be tested are distributed on adjacent different word lines WL0 to WL 15. Here, each memory cell to which WL0 to WL7 are respectively coupled is taken as a first memory cell, i.e., eight first memory cells are included, and each memory cell to which WL8 to WL15 are respectively coupled is taken as a second memory cell, i.e., eight second memory cells are included. Initial data is written first, illustratively, the initial data is all "0" data. For the read data of WL0-WL7, it is assumed that the memory cell has no other write or read anomalies, so the read data is the initial data: all "0". Note that in the embodiment of the present disclosure, each first memory cell needs to be rewritten after being read, as shown in fig. 3B and 3C, data "0" is rewritten to data "1".

If the data in the second memory cell is read to include both the first data and the initial data: as in the case shown in fig. 3B, the data of WL10 is updated to "1" due to the presence of leakage with WL2, and the data of WL13 is updated to "1" due to the presence of leakage with WL5, and the data of WL8, WL9, WL11, WL12, WL14, and WL15 are still the initial data "0". At this time, the first test data outputted after the data processing (such as exclusive or operation) of the first test indicates that the read data contains different data (such as logic "1"). Therefore, the external detection device can determine that the second memory cell does not pass the first test according to the first test data, and the leakage abnormality exists. Therefore, it is not necessary for the external detecting device or apparatus to check the read data one by one, and it is possible to determine that there is an abnormality from the output first test data.

If the data in the second memory cell is the same data, the first test data is logic "0", which indicates that the data may be all "0" or all "1". In this case, the case where there is no abnormality is included, and the case where all abnormalities are included. A further second test is therefore required to determine if all anomalies are present.

As shown in fig. 3C, if there is a leakage abnormality between WL0-WL7 and WL8-WL15 (such as leakage between WL0 and WL8, leakage between WL1 and WL9, leakage between WL6 and WL14, leakage between WL7 and WL 15), the data of the second memory cell corresponding to WL8-WL15 is updated synchronously during the process of WL0-WL7 updating, the data of the read second memory cell will be consistent with the rewritten data. As shown in FIG. 3C, the read data corresponding to WL8-WL15 is all "1". Therefore, the data of the second memory cell is read as the first data instead of the initial data.

As shown in fig. 3D, if no leakage abnormality exists between WL0-WL7 and WL8-WL15, the data of the second memory cell corresponding to WL8-WL15 will not be rewritten synchronously, and thus the read data should be all "0", i.e. all initial data.

For the two cases that the data read by the second memory cell is all "0" (no anomaly) or all "1" (all anomaly), the result obtained after the first test is performed may be the same, for example: the output first test data is logic "0". Therefore, the first test described above can only determine the abnormality as shown in fig. 3B, that is, if the second memory cell passes the first test, there may still be an abnormality caused by the leakage as shown in fig. 3C, that is, the first test cannot be distinguished for both cases as shown in fig. 3C and 3D, so that the second test can be further performed to identify the abnormality as shown in fig. 3C.

In the embodiment of the disclosure, the second test may be a test with higher accuracy, for example, a test method for identifying each read data, or may be other test methods.

In some embodiments, the step of processing the read data to obtain the first test data includes:

performing first processing on two adjacent first data to obtain a plurality of first intermediate data;

and performing second processing on the plurality of first intermediate data to obtain the first test data.

In the embodiment of the present disclosure, the data processing performed on each data read in the first test may include two data processes. First, a plurality of first intermediate data are obtained by first processing the two adjacent data, and then, final first test data can be further obtained by performing second processing based on the first intermediate data. For example, if the first processing uses an exclusive or operation, the obtained first intermediate data is "1", which indicates that the data of the two adjacent second storage units are different data, and the obtained first intermediate data is "0", which indicates that the data of the two adjacent second storage units are the same data. The plurality of first intermediate data is further processed for a second time, for example, an or operation is performed, and if the data "1" is output, it is indicated that the plurality of first intermediate data includes "1", that is, includes at least two adjacent data that are different data, and at this time, it may be determined that the data read in the plurality of second storage units have different data, and at this time, if the initial data are all the same data, it may be determined that the read data includes second data that is different from the initial data, that is, includes abnormal data generated due to leakage. It can thus be determined that the second memory cell participating in the above-described process fails the first test. If the first intermediate data are all "0", it means that the data in each adjacent memory cell are the same, and then the second processing is performed, and the obtained test data are "0", and it can be considered that the data stored in the second memory cell are all the same data.

In this way, it is possible to determine whether the second memory cell passes the first test based on the test data obtained by the two processes as an output.

The first processing is performed on the read data for WL8-WL15 in fig. 3C or 3D, and may be, for example, an exclusive or operation processing of two by two, to obtain four sets of first test data. And then performing a second process, such as OR operation, to obtain final test data. If the test data in fig. 3C are 1, the results of the two treatments are shown in fig. 4A; if the test data in fig. 3D are all 0, the results of performing the two processes are shown in fig. 4B.

It should be noted that the above initial data are all the same data, which is merely an example, and in practical application, various other data with specific rules may be adopted as the initial data according to practical requirements, for example, any adjacent data is different "checkerboard" data. In addition, the above processing methods including the exclusive or operation and the or operation are also merely exemplary processing methods, and in practical applications, other various processing methods may be adopted according to the rule of the initial data, the design of the actual circuit, and the like, for example, the exclusive or operation or the combination of various logic operations, and the like.

In some embodiments, the determining whether the second memory cell passes the first test according to the first test data includes:

if the first test data represents a high level, the first test data does not pass the first test;

if the first test data indicates a low level, the first test data indicates that the first test is passed.

In the embodiment of the present disclosure, the first test data may be a binary output signal including a "high level" signal and a "low level" signal. If the output signal is a high level signal, it may represent that the output test data is a logic "1", and further represent that the data of the read second memory cell does not conform to the rule of the initial data, for example, the initial data are all the same data, and different data exist in the read data, so it may be determined that the second memory cell fails the test.

If the output signal is a low level signal, it may represent that the output test data is logic "0", and thus the data representing the read second memory cell conforms to the rule of the initial data, for example, the initial data are all the same data, and the read data are all the same data, so that it may represent that the second memory cell passes the test.

It will be appreciated that to improve the efficiency of the test, the memory may be tested using a compressed mode, and for the scenario of fig. 4A and 4B described above, the output test data is logic "0", i.e., the output signal is a low level signal representing the passing test. But in reality the corresponding scenario in fig. 4A is as in fig. 3C, which has the problem of full shorting. Therefore, the above method may cause erroneous judgment in this case, and the test result that the short circuit abnormality exists in practice but is output is the test passing.

Accordingly, the presently disclosed embodiments also provide a test method that employs the second test as the test of the above-described embodiments followed by the supplemental test. Of course, the second test may also be used alone for testing.

Specifically, in some embodiments, as shown in fig. 5, the performing a second test includes:

step S301, updating data in the plurality of first storage units and the plurality of second storage units to initial data;

step S302, reading data in a plurality of first storage units, maintaining the initial data in at least one first storage unit, and updating the remaining data in the first storage units to the first data;

Step S303, reading data in a plurality of second storage units, and processing the read data to obtain second test data;

and step S304, judging whether the second storage unit passes the second test according to the second test data.

It should be noted that, the steps S301 to S304 may be executed when the second memory unit passes the first test after the first test is completed, or may be executed independently, independent of the test result of the first test.

Similar to the first test, initial data may be written to the first memory cell and the second memory cell, and then the data in the plurality of first memory cells may be sequentially read and updated. However, unlike the first test in the above embodiment, the second test does not update data of all the first memory cells, but needs to keep the data in at least one first memory cell unchanged. The first memory cells that keep the data unchanged may be located on the same word line or may be distributed among a plurality of word lines. That is, the first memory cells on at least one word line keep the data unchanged after the data is read, and the data of the other first memory cells are updated after the data is read.

In the embodiment of the disclosure, the initial data in at least one memory cell may be maintained by locking the memory block or locking part of the memory cells by a preset circuit. That is, after the first storage unit is locked, the locked first storage unit is not rewritten in the process of rewriting the data of the other storage units. For example, the memory block may be locked by disconnecting the read/write path of the corresponding memory block or memory cell by a preset circuit so that the charge of the read/write data does not flow into the memory block or memory cell. Thus, when the first data is written into each first memory cell after the read operation, the locked first memory cell is maintained as the initial data and the first data is not written, and the data of the other first memory cells is updated as the first data after the read operation.

And then, continuously reading the data in the second storage unit, and performing data processing similar to the first test to obtain second test data. It may then be determined whether the second memory cell passes the second test based on the second test data.

It can be understood that, since the data of the first storage unit is partially updated and partially kept unchanged, if there is a one-to-one leakage condition between the first storage unit and the second storage unit, the data in the second storage unit is also changed synchronously to be partially consistent with the updated data of the first storage unit, and the other part keeps the initial data. That is, if there is an abnormality, it can be recognized by this way of the second detection that the data rule of the second memory cell is different from the initial data, thereby facilitating detection of the leakage. Compared with the situation that the first storage unit updates data completely, the method can effectively identify the situation of all short circuits and reduce the occurrence of missed detection.

In some embodiments, the processing the read data to obtain second test data includes:

performing first processing on two adjacent data to obtain a plurality of second intermediate data;

and performing second processing on a plurality of second intermediate data to obtain second test data.

In the embodiment of the present disclosure, similarly to the first test, the data processing performed on each data read in the above-described second test may include two data processing. First, performing first processing on two adjacent data to obtain a plurality of second intermediate data, and then performing second processing based on the second intermediate data, so that final second test data can be further obtained. For example, if the first processing uses an exclusive or operation, the obtained second intermediate data is "1", which indicates that the data of the two adjacent second storage units are different data, and the obtained second intermediate data is "0", which indicates that the data of the two adjacent second storage units are the same data. The second intermediate data are further processed, for example, an or operation is performed, where if the data "1" is output, it is indicated that the second intermediate data include "1", that is, include at least two adjacent data as different data, and at this time, it may be determined that the data read in the second storage units have different data, and at this time, if the initial data are all the same data, it may be determined that the read data include first data different from the initial data, that is, include abnormal data generated due to leakage. It can be determined that the second memory cell participating in the above-described process fails the second test. If the second intermediate data is "0", it means that the data in each adjacent memory cell is the same, and then the second processing is performed, and the obtained test data is "0", and it can be considered that the data stored in the second memory cell are all the same data.

In the case where the initial data are the same data, a part of the initial data and a part of the first data exist in the first memory cell, because a part of the first memory cell is maintained to be not updated during the reading and the data updating of the first memory cell. Therefore, if there is leakage between the first memory cell and the second memory cell, there is a difference in the data read in the second memory cell, and the data result is "1". That is, if the output result is "1" at this time, it is indicated that the second memory cell has an abnormality, and the test is not passed. Accordingly, if there is no leakage, the second memory cell is always maintained as the initial data, and the output result is "0".

As shown in fig. 6A, similar to the case in fig. 3C, the data of the first memory cell on WL0 is maintained unchanged, i.e., still "0" when the data is rewritten. Since there is a one-to-one correspondence short circuit between WL0-WL7 and WL8-WL15, respectively, as mentioned in the above embodiments, the data on WL9-WL15 will be rewritten to data "1" simultaneously when WL1-WL7 rewrites the data; WL8 is identical to WL0 and is not rewritten.

Therefore, when data processing is performed for this case, there are the results shown in fig. 6B: in the first processing, WL8 is different from WL9, so that the first intermediate data obtained by the exclusive or operation is "1", and the other sets of first intermediate data are "0". And performing the second processing, wherein the first intermediate data has one '1', so that the second test data obtained by performing OR operation is '1', namely the second memory cell fails the second test.

Thus, the second test data obtained by the two processes can be used as an output result, and whether the second storage unit passes the test can be judged according to the output result. In addition, in the process of rewriting the first storage unit, the data in part of the first storage unit is maintained unchanged, so that the first storage unit has different data. In this way, the problem that the data of the second storage unit is abnormal and cannot be detected because the data of the first storage unit and the data of the second storage unit are all identical due to short circuit and leakage of all the first storage unit and the second storage unit can be improved.

In some embodiments, among the initial data held in the at least one first storage unit, data in an odd number of the first storage units may be held as the initial data.

It is understood that the number of the first memory cells herein refers to each memory cell participating in the same test. The detection needs to be performed for a plurality of memory cells on the same word line. In one embodiment, it is understood that the memory cells to be detected are memory cells on a plurality of word lines, and the first memory cell holding the initial data is each memory cell connected on an odd number of word lines.

In an exemplary embodiment, the first memory cells connected to the odd word lines may be read and rewritten while the first memory cells are kept unchanged from the initial data, and the first memory cells connected to the odd word lines may be rewritten to the first data. Thus, if there is leakage between the first memory cell and the second memory cell, when the second memory cell is read, taking the memory cell connected to one bit line as an example (i.e. only one memory cell on each word line participates in detection), the read data also has an odd number of initial data and an odd number of first data. Therefore, different data can be identified more easily after the data is processed, and the abnormal leakage of the second storage unit can be detected.

Illustratively, the first storage units and the second storage units are respectively 8, the data of 3 first storage units is kept unchanged as initial data, and the data of the other 5 storage units is updated as first data. As shown in fig. 6C, the data "0" of the memory cells coupled to WL0, WL1 and WL2 is maintained unchanged, and the data in the other first memory cells is updated to the first data "1".

If there is leakage between the first memory cell and the second memory cell in a one-to-one correspondence, 3 initial data and 5 first data will also exist in the data of the second memory cell read. As shown in fig. 6C, the data in the memory cells coupled to WL8, WL9 and WL10 is the initial data "0", and the data in the other second memory cells is the first data "1". Thus, when these data are processed by exclusive or operation, at least one second intermediate data "1" is obtained, and as shown in fig. 6D, after the first processing, wl8xorwl9=0, wl10xorwl11=1, wl12xorwl13=0, and wl14xorwl15=0 are obtained. And then performing OR operation for the second time to obtain second test data of 1. This leakage can be identified and it is determined that the second memory cell does not pass the second test. It will be appreciated that if the number of memory cells remaining unchanged is even, there may be two adjacent memory cells that remain unchanged, e.g., the data in the memory cell that maintains WL0 coupled to WL1 is "0" and the data in the other first memory cell is updated to "1". Then, the data read by the corresponding second memory cell is the first data "1" in the memory cells coupled to WL8 and WL9, and the result obtained by performing the exclusive or operation is also 0, so that the data in the memory cells coupled to WL8 and WL9 cannot be identified to be consistent with WL0 and WL1, and thus the abnormality of the data cannot be detected. That is, the method is adopted to maintain the data in the odd number of first storage units unchanged and update the data of other first storage units, so that when all abnormal situations of electric leakage exist, at least one second intermediate data can be obtained to be 1 through the exclusive OR operation.

In addition, in addition to the method of setting the odd number of first memory cells to remain unchanged and updating other first memory cells, the first memory cells with intervals can be set to remain unchanged, so that the data of each first memory cell is alternately distributed with the first data and the initial data, as shown in fig. 6E, and thus, the condition that the exclusive or result is unchanged and cannot be detected because the adjacent two memory cells are synchronously updated can be avoided.

It will be appreciated that if there is no leakage between the first memory cell and the second memory cell, it is indicated that the data of the second memory cell is not changed synchronously due to the data update of the first memory cell, so the same initial data is always maintained, and therefore, when the output second test data is "0", it can be determined that the second test passes.

In some embodiments, the determining whether the second memory cell passes the second test according to the second test data includes:

if the second test data represents high level, the second memory cell fails the second test;

and if the second test data represents a low level, the second memory cell passes the second test.

In the embodiment of the present disclosure, the second test data may be a binary output signal including a "high level" signal and a "low level" signal. If the output signal is a high level signal, it may represent that the output second test data is "1", and further represent that the data of the read second memory cell does not conform to the rule of the initial data, for example, the initial data are all the same data, and different data exist in the read data, so it may be determined that the second memory cell fails the second test.

If the output signal is a low level signal, it may represent that the output second test data is "0", and thus the data representing the read second memory cell conforms to the rule of the initial data, for example, the initial data are all the same data, and the read data are all the same data, so that it may be represented that the second test data pass.

In some embodiments, the method further comprises: and judging whether the first storage unit passes a third test.

Through the first test and the second test in the above embodiments, the data in the second memory cell is read to determine whether the second memory cell is interfered by the data in the first memory cell, which results in an exception. In addition, the first memory cell and the second memory cell may be exchanged for performing a reverse test to determine whether the first memory cell passes the third test. The third test here may be a test procedure similar to the second test or the first test, but the test object is the first memory cell. Thus, on one hand, the detection can be more comprehensively carried out, the possibility of missed detection is reduced, and on the other hand, data can be obtained from multiple angles so as to analyze the reasons of abnormality and facilitate the subsequent reworking or improvement processing. And meanwhile, whether abnormal connection exists between the first storage unit and the second storage unit can be further confirmed.

The step of determining whether the first memory cell passes the test may be performed after determining whether the second memory cell passes the test, or may be performed before performing the test of the second memory cell, which is not limited herein.

In some embodiments, the step of determining whether the first memory cell passes the test comprises:

updating the data in the first storage units and the second storage units to initial data;

reading initial data in the plurality of second storage units, maintaining the initial data in at least one second storage unit, and updating the initial data in the rest second storage units into the first data;

reading the data in the plurality of first storage units, and processing the read data to obtain third test data;

and judging whether the first storage unit passes a third test according to the third test data.

When the first memory cell is tested, the initial data may be rewritten in the first memory cell and the second memory cell. Of course, the initial data may be the same as or different from the initial data used in the second storage unit test, but the initial data needs to be known preset data, so as to facilitate the subsequent judgment.

The detection process is similar to the detection process of the second storage unit, and the second storage unit is read and partial data in the second storage unit is rewritten. And then reading the data of the first storage unit, and carrying out data processing and judgment according to the read data.

It will be appreciated that the data of a portion of the second memory cells is updated after the second memory cell data is read, and the portion of the data is kept unchanged, thereby causing the portion of the data in the second memory cells to be different from the initial data. If the first memory cell is rewritten synchronously due to the influence of the leakage of the second memory cell, the first memory cell also has partial data different from the initial data, so that the purpose of data detection of the first memory cell can be achieved.

As shown in fig. 7A, after the second memory cells are read in the order of WL8 to WL15, the data of the second memory cells are updated, but the data of the second memory cells on WL15 is maintained unchanged, i.e., still "0". The data in the first memory cell is then read continuously in the order WL0 to WL 7. Because there is a short between WL0-WL7 and WL8-WL15, respectively, the data on WL0-WL6 will be updated to data "1" synchronously when WL8-WL14 data is updated; whereas WL7 is identical to WL15 and will not be updated.

Therefore, when data processing is performed for this case, there are the results shown in fig. 7B: in the first processing, WL6 is different from WL7, so the exclusive or operation results in "1" for data and "0" for other sets of data. The second processing is performed, and since there is one "1" in the data obtained by the first processing, the data obtained by performing the or operation is "1", that is, it means that the first memory cell fails the test.

In some embodiments, the step of processing the read data includes:

performing first processing on two adjacent data to obtain a plurality of third intermediate data;

and performing second processing on a plurality of third intermediate data to obtain third test data.

In the embodiment of the present disclosure, similarly to the first test and the second test described above, the data processing performed on each data read in the third test may include two data processing. First, performing first processing on two adjacent data to obtain a plurality of third intermediate data, and then performing second processing based on the third intermediate data, so that final third test data can be further obtained. For example, if the first processing uses an exclusive or operation, the obtained third intermediate data is "1", which indicates that the data of the two adjacent first storage units are different data, and the obtained third intermediate data is "0", which indicates that the data of the two adjacent first storage units are the same data. The plurality of third intermediate data is further processed, for example, an or operation is performed, where if the data "1" is output, it is indicated that the plurality of third intermediate data includes "1", that is, includes at least two adjacent data that are different data, and it may be determined that the data read in the plurality of first storage units have different data, and if the initial data are all the same data, it may be determined that the read data includes first data different from the initial data, that is, includes abnormal data generated due to leakage. It can be determined that the first memory cell participating in the above-described process fails the third test. If the third intermediate data is "0", it means that the data in each adjacent memory cell is the same, and then the second processing is performed, and if the obtained third test data is "0", it can be considered that the data stored in the first memory cell are all the same data.

In the case where the initial data are the same data, the first storage unit has a portion of the initial data and a portion of the first data, because the data in a portion of the second storage unit is maintained to be not updated during the reading and the data updating of the second storage unit. Therefore, if there is leakage between the first memory cell and the second memory cell, there is a difference in the data read in the first memory cell, and the data result is "1". That is, if the output result is "1" at this time, it is indicated that there is an abnormality in the first memory cell, and the third test is not passed. Accordingly, if there is no leakage, the first memory cell is always maintained as the initial data, and the output result is "0".

Thus, the test data obtained by the two processes can be used as an output result, and whether the first storage unit passes the test or not can be judged according to the output result. In addition, in the process of rewriting the second storage unit, the data in part of the second storage unit is maintained unchanged, so that the second storage unit has different data. Thus, the problem that the data of the first storage unit is abnormal and cannot be detected due to the fact that the data of the first storage unit and the second storage unit are all identical due to short circuit and leakage can be avoided.

In some embodiments, among the initial data held in the at least one first storage unit, data held in an odd number of the first storage units is the initial data.

The initial data may be written into the first memory cell and the second memory cell before the test is performed, and the initial data may be all the same data, or may be data having a specific rule, for example, data of "checkerboard", that is, data in any two adjacent memory cells are different.

If the data in the first storage unit read in the detection process is different from the initial data, the data is indicated to have electric leakage with the second storage unit. Therefore, detection of leakage can be achieved by reading the data of the first memory cell.

In the embodiment of the disclosure, the data in the second memory cells connected to the odd word lines can be kept unchanged as the initial data in the process of reading and updating the second memory cells, and in addition, the data in the second memory cells on the odd word lines are rewritten as the first data. In this way, if there is a leakage between the first memory cell and the second memory cell, when the first memory cell is read, for example, the memory cell connected to one bit line, there are also an odd number of initial data and an odd number of rewritten first data in the read data. Therefore, different data can be identified more easily after the data is processed, and the leakage abnormality of the first storage unit can be detected.

Illustratively, the first storage unit and the second storage unit have 8 storage units respectively, the data of 3 second storage units is kept unchanged as initial data, and the data of the other 5 second storage units is updated as first data. As shown in fig. 7C, the data "0" of the memory cells coupled to WL13, WL14 and WL15 is maintained unchanged, and the other second memory cells are updated with the first data "1".

If there is leakage between the first memory cell and the second memory cell in a one-to-one correspondence, 3 initial data and 5 first data will also exist in the data of the first memory cell read. As shown in fig. 7C, the data in the memory cells coupled to WL5, WL6 and WL7 is the initial data "0", and the data in the other first memory cells are the first data "1". Thus, when these data are processed by exclusive or operation, at least one third intermediate data is "1", and as shown in fig. 7D, after the first processing, wl0 xorwl1=0, wl2 xorwl3=0, wl4xorwl5=1, and wl6xorwl7=0 are obtained. And then performing OR operation to obtain third test data of 1. This leakage can be identified and it is determined that the first memory cell does not pass. It will be appreciated that if the number of memory cells remaining unchanged is even, there may be two adjacent memory cells that remain unchanged, e.g., the data in the memory cell that maintains WL14 coupled to WL15 is "0" and the other second memory cells are updated to "1". Then, the data read by the corresponding first memory cell is the first data "1" in the memory cells coupled to WL6 and WL7, and the result obtained by performing the exclusive or operation is also 0, so that the data in the memory cells coupled to WL6 and WL7 cannot be identified to be consistent with WL14 and WL15, and thus the abnormality of the data cannot be detected. That is, the method is adopted to maintain the data in the odd number of second storage units unchanged and update the data of other second storage units, so that when all abnormal situations of electric leakage exist, at least one third intermediate data can be obtained to be 1 through the exclusive OR operation.

In addition, in addition to the method of setting the odd number of second memory cells to remain unchanged and updating other second memory cells, the second memory cells with intervals can be set to remain unchanged, so that the data of each second memory cell is alternately distributed with the first data and the initial data, as shown in fig. 7E, and thus, the condition that the exclusive or result is unchanged and cannot be detected because the adjacent two memory cells are synchronously updated can be avoided.

It will be understood that if there is no leakage between the first memory cell and the second memory cell, it is indicated that the data of the first memory cell is not changed synchronously due to the data update of the second memory cell, so the same initial data is always maintained, and therefore, when the output third test data is "0", it can be determined that the third test passes.

In some embodiments, the determining whether the first memory cell passes the third test according to the third test data includes:

if the test data represents a high level, the first storage unit fails the third test;

and if the test data represents a low level, the first storage unit passes the third test.

In the embodiment of the present disclosure, the third test data may be a binary output signal including a "high level" signal and a "low level" signal. If the output signal is a high level signal, it may represent that the output third test data is "1", and further represent that the data of the read first memory cell does not conform to the rule of the initial data, for example, the initial data are all the same data, and different data exist in the read data, so it may be determined that the first memory cell fails the third test.

If the output signal is a low level signal, it may represent that the output third test data is "0", and further represent that the data of the read first memory cell meets the rule of the initial data, for example, the initial data are all the same data, and the read data are all the same data, so that it may be represented that the data pass the third test.

In some embodiments, the method further comprises:

and if the second storage unit fails the second test and the first storage unit fails the third test, determining that the first storage unit and the second storage unit are abnormally connected.

By the method in the above embodiment, it may be respectively determined whether the first memory cell and the second memory cell are abnormal, and if both the first memory cell and the second memory cell are abnormal, it is indicated that there is a connection abnormality between the first memory cell and the second memory cell, for example, there is a short-circuit between the first memory cell and the second memory cell, or there is a short-circuit between corresponding word lines of both, or there is a short-circuit between peripheral circuits connected to both, etc. When the second storage unit fails the second test, the data in the second storage unit can be judged to be influenced by the data in the first storage unit; when the first storage unit fails the third test, it can be determined that the data in the first storage unit is affected by the data in the second storage unit, so when the second storage unit fails the second test, it can be determined that the connection between the first storage unit and the second storage unit is abnormal.

In some embodiments, the first memory cell includes a memory cell coupled to a first word line and the second memory cell includes a memory cell coupled to a second word line.

Here, the first word line may include one or more, and the second word line may also include one or more.

It is understood that the first word line is coupled with a plurality of memory cells and the second word line is coupled with a plurality of memory cells. In performing the data processing referred to in the embodiments of the present disclosure, data that substantially participates in one operation processing comes from one first memory cell on each word line. For example, data of each of the first memory cell and the second memory cell coupled on the same bit line is processed. If a plurality of bit lines exist, the bit lines are respectively processed, so that a plurality of test data can be obtained, and further the leakage position can be conveniently determined.

In some embodiments, the first memory cell and the second memory cell connection anomaly indicates that the first word line and the second word line are shorted.

Here, the short-circuit connection between the first word line and the second word line may include a direct short-circuit between the first word line and the second word line, or may include a short-circuit connection between peripheral circuits to which the first word line and the second word line are connected.

In some embodiments, a common signal control structure may be provided between the first and second word lines for synchronizing the supply of a common signal, such as a main word line drive signal, to the plurality of word lines. And the main word line driving signal is connected to each word line through each control switch connected respectively, i.e. controlled by the sub driving signal for each word line.

Illustratively, one set of 8 first word lines (WL 0 to WL 7) is controlled by the same main word line drive signal, and the other set of 8 second word lines (WL 8 to WL 15) is controlled by another word line drive signal. In the design of the memory structure, the driving switch wires of the driving signals corresponding to the two groups of word lines are located at adjacent positions, specifically, the control switch corresponding to each sub-word line driving signal in the 8 first word lines is adjacent to the control switch corresponding to each sub-word line driving signal in the 8 second word lines, so that short circuit is easy to occur. For example: a short circuit occurs between the first word line WL0 controlled by the first main control signal and the second word line WL8 controlled by the second main control signal; a short circuit occurs between the first word line WL1 controlled by the first main control signal and the second word line WL9 controlled by the second main control signal; … … a short circuit occurs between the first word line WL7 controlled by the first main control signal and the second word line WL15 controlled by the second main control signal.

Therefore, based on similar memory structure designs, the first word line and second word line shorting conditions as in the above embodiments are easily presented, which is described herein by way of example only. Of course, based on other structural designs where short circuit connection may occur, similar detection methods may be used for detection, which is not limited herein.

In some embodiments, the first processing includes an exclusive-or operation and the second processing includes an or operation. In other embodiments, the first processing includes an exclusive-or operation, the second processing may also include an and operation, and so on.

Embodiments of the present disclosure also provide examples of:

in the production process of Dynamic Random Access Memory (DRAM), etc., testing at each stage is required to determine whether there is an abnormality, so that operations such as reworking, repairing or scrapping at a later stage are facilitated, and further, production efficiency and product yield are improved.

In the wafer test process, a compression mode with a high compression ratio is generally adopted for testing, namely, comprehensive testing is carried out by taking a plurality of storage units such as a storage block, a storage surface or a storage page as a unit, and region judgment is carried out according to the output test result. Compared with read-write test of memory cells one by one, the method has the characteristics of high speed and high efficiency, and is suitable for testing in a CP (Circuit Probe) stage in the mass production process. However, since this method cannot realize the individual detection of each memory cell, there is a case of missing detection.

Illustratively, the compression mode may include inputting data obtained after the read operation to the logic circuit to obtain an output signal, and determining characteristics of the read data based on the output signal. For example, exclusive or processing is performed on each read data, and if there are different data, a logical "1" is output, and if all the data are the same, a logical "0" is output. Thus, it is not necessary to say that each of the data read is output, but judgment can be made by only one output signal.

The embodiment of the disclosure provides a test method based on a compression mode, which can reduce the occurrence of missed detection while rapidly detecting.

In the embodiment of the present disclosure, a plurality of word lines to which memory cells to be detected are connected may be divided into two groups, and the two groups of word lines may be word lines that are liable to generate short-circuit connection on a product structure, for example, have a common control element or are disposed at adjacent positions in a physical structure, or the like.

The following procedure can be adopted in the detection process:

1. initial data (which may be the same data) is written into the memory cell units connected to the two groups of word lines, respectively;

2. and sequentially reading the memory cells connected with the first group of word lines, and after each reading operation on one word line is completed, rewriting the data of the memory cells connected with the word line. It will be appreciated that each data obtained from the first set of word lines read at this time should be initial data, and if not, it is indicative of a problem of write anomalies in the first set of word lines.

3. And continuing to sequentially read the data of each memory cell connected with the second group of word lines.

If there is different data in the read data. The data existence part in the memory cells connected with the second group of word lines is described, and the data are rewritten in the process of rewriting the data by the memory cells on the first group of word lines, so that the abnormal leakage of the word lines and related circuits can be determined, and the result that the test is not passed is obtained.

If the output indicates that the data in the memory cells connected on the second set of word lines are all the same, e.g., the output signal indicates a logic "0", then it indicates that it is possible that the memory cells connected on the second set of word lines are still all the original data, not rewritten, and thus pass the test.

It will be appreciated that there is a miss-detection condition in the above-described pass test condition, i.e. the output signal indicates that the data in the memory cells connected on the second set of word lines are all the same, but in fact all the data in the memory cells are rewritten due to the leakage effect with the first set of word lines.

Thus, in embodiments of the present disclosure, the following tests may also be performed:

1. respectively writing initial data into the memory unit cells connected with the two groups of word lines;

2. Sequentially reading all the memory cells connected with the first group of word lines, and after each reading operation on one word line is completed, rewriting the data of all the memory cells connected with the word line; in addition, a memory cell in which at least one word line is connected is selected not to be rewritten. That is, after reading each memory cell connected to the first group of word lines, the partial data is rewritten and the partial data is maintained so that the data stored in the memory cells connected to at least two word lines in the first group of word lines are different.

At this time, if the data of each memory cell connected to the second group of word lines is still the same data, for example, the output signal indicates a logic "0", it means that the second group of word lines is not affected by leakage and is still the initial data. If the output signal indicates a logical "1", i.e. there is a difference in the data of each memory cell to which the second group of word lines is connected, it is indicated that there is a different data in the second group of word lines, i.e. the data in the second group of word lines is also rewritten to be part of the data differently, subject to the influence of the data rewrite in the first group of word lines. Therefore, it can be determined that there is a leakage abnormality in the second group of word lines at this time.

It will be appreciated that if the initial data is a different data, such as "checkerboard data", the corresponding output results will also need to be adjusted accordingly.

Assuming 16 word lines WL0-WL15 are to be detected, WL0-WL7 may be grouped into a first group and WL8-WL15 may be grouped into a second group. The initial data as shown in fig. 8A may be written to the memory cells to which the respective word lines are connected. And reading data in each storage unit connected with WL0-WL7, and after each reading of data on one WL, rewriting the data into different data, and maintaining the data on at least one WL unchanged. It should be noted that maintaining the number of word lines unchanged as an odd number is more convenient for data processing.

For example, the data of WL0 is maintained unchanged. The data of each memory cell on WL8-WL15 is then read. If there is no anomaly, all data is as shown in FIG. 8B.

Only WL0 data changes. The data read to WL8-WL15 is unchanged.

In the above-mentioned test method of the compression mode, the read data need not be all outputted, but a detection result can be obtained through logic operation.

For example, each of the data on WL8 to WL15 is logically operated to obtain an output result, and if the output result is at the high level, the pass is detected. Here, as shown in fig. 8C, the process of the logic operation may include: first data processing: the data of adjacent WL are exclusive-ored two by two, that is, WL8 xor WL9, WL10 xor WL11, WL12 xor WL13, WL14 xor WL15. It will be appreciated that if the initial data is used, there is no leakage between the memory cells coupled between WL8 to WL15 and WL0 to WL7, the exclusive or result should be a logic "1", that is, the data in the memory cells coupled between any two adjacent WLs in WL8 to WL15 are different. These logical operation results are then subjected to a second data processing, where an and operation (or operation may be employed here if the initial data is the same data of all 0 s or all 1 s) may be employed according to the characteristics of the initial data described above. In the above scenario, the 4 sets of logic results obtained by the first data processing are all logic "1", and the final output result of the second data processing is logic "1".

In the actual detection process, according to the final result logic '1', it can be determined that the logic '0' does not exist in the results of the multiple groups of first data processing, and then it can be determined that the data on two adjacent WLs are identical, and the basic rule of the 'checkerboard' data is met, so that no abnormality exists, namely the test passes.

In contrast, if there is an anomaly, the data of the second set of WL will remain the same as the data of the first set of WL due to leakage, i.e. WL8 remains unchanged after overwriting the data on WL1-WL7, and WL8-WL15 is also overwritten, as shown in FIG. 8D:

in this case, as shown in fig. 8E, the procedure of the data processing is performed, for example: WL8 xor WL9, WL10 xor WL11, WL12 xor WL13, WL14 xor WL15. Wl8 xorwl9=0 can be obtained, while wl10 xorwl11=1, wl12 xorwl13=1, wl14 xorwl15=1. Thus, one logical "0" and three logical "1" are included in the result of the first data processing. And continuing the AND operation of the second data processing, and obtaining a result of 0. In this case, it can be determined from the output result that the second group of word lines is affected by the leakage of the data written on the first group of word lines, and thus, there is an abnormality.

As shown in fig. 9, an embodiment of the present disclosure further provides a test system 400 for a memory, including:

a data reading unit 401 for reading data in the first storage unit and the second storage unit;

a data updating unit 402, configured to update the data in the first storage unit to first data after reading the data in the first storage unit;

and the data testing unit 403 is configured to process the read data to obtain test data, and determine whether the second storage unit passes the test according to the test data.

Here, each component of the test system may be configured in the control logic in the memory, or may be configured in the external test device, and the functions thereof may be used to perform the method steps in any of the foregoing embodiments, and details of the specific details of the foregoing method embodiments are described in the foregoing embodiments, which are not repeated herein.

The disclosed embodiments also provide a memory, as shown in fig. 10, the memory 500 includes:

a memory array 510 including a plurality of memory cells; each memory cell is connected with a word line WL and a bit line BL; wherein each memory may have a plurality of memory planes, each memory plane may contain one or more memory arrays;

And a peripheral circuit 520 connected to the memory array for applying voltages required for performing read/write operations and sensing operations on each memory cell in the memory array to the corresponding word line and/or bit line, and for transferring output signals from the memory array.

Here, the peripheral circuit may be configured to perform the test method of the memory described above.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.

The foregoing is merely an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about the changes or substitutions within the technical scope of the present disclosure, and should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for testing a memory, comprising:

2. The method of testing of claim 1, wherein said passing said first test data to determine whether said second memory cell passes a first test comprises:

determining whether the read data simultaneously comprises the first data and the initial data in the second storage unit according to the first test data;

if yes, the first test is not passed;

if not, the first test is passed, and the second test is continued.

3. The method of testing according to claim 2, wherein processing the read data to obtain first test data comprises:

4. The method of testing according to claim 2, wherein determining whether the second memory cell passes a first test based on the first test data comprises:

5. The method of testing according to claim 2, wherein the performing a second test comprises:

reading data in a plurality of first storage units, maintaining the initial data in at least one first storage unit, and updating the data in the rest first storage units into the first data;

reading the data in the plurality of second storage units, and processing the read data to obtain second test data;

and judging whether the second storage unit passes the second test according to the second test data.

6. The method according to claim 5, wherein the processing the read data to obtain second test data includes:

7. The test method according to claim 5, wherein among the initial data held in the at least one first memory cell, data held in an odd number of the first memory cells is the initial data.

8. The method of testing as claimed in claim 6, wherein said determining whether said second memory cell passes said second test based on said second test data comprises:

9. The method of testing according to claim 5, further comprising:

and judging whether the first storage unit passes a third test.

10. The method of testing of claim 9, wherein said determining whether the first memory cell passes the test comprises:

11. The method of testing of claim 10, wherein the step of processing the read data comprises:

12. The test method according to claim 10, wherein among the initial data held in the at least one first memory cell, data held in an odd number of the first memory cells is the initial data.

13. The method of testing of claim 11, wherein determining whether the first memory cell passes the third test based on the third test data comprises:

14. The method of testing according to claim 9, wherein the method further comprises:

15. The method of testing of claim 14, wherein the first memory cell comprises a memory cell coupled to a first word line and the second memory cell comprises a memory cell coupled to a second word line.

16. The test method of claim 15, wherein the first memory cell and the second memory cell connection anomaly indicates that the first word line and the second word line are shorted.

17. The test method according to claim 6 or 11, wherein the first processing comprises an exclusive-or operation and the second processing comprises an or operation.

18. A memory testing system, comprising: