CN116741228A - 14T radiation-resistant SRAM memory unit and circuit modules, structures and chips based on it - Google Patents

Abstract

The invention relates to a 14T radiation-resistant SRAM memory cell, and a circuit module, a structure and a chip based on the same. The SRAM memory cell includes 6 NMOS transistors N1 to N6 and 8 PMOS transistors P1 to P8. P1, P2, P5 and P6 are used as pull-up tubes, P3 and P4 are used as pull-down tubes, and their states are controlled by storage nodes Q and QN, respectively. Q and QN are electrically connected to bit line BL and bit line BLB through N5 and N6, respectively. The redundant storage nodes S0 and S1 are electrically connected to the bit line BL and the bit line BLB through P7 and P8, respectively. The invention adopts the polarity reinforcing principle to design, ensures the stability of redundant storage nodes S0 and S1, and improves the stability of the storage node Q, QB by utilizing the source isolation technology. In the process of writing data, the bit lines write data into the internal nodes Q\QB and S0\S1 through N5, N6, P7 and P8, so that the data writing speed and the noise margin of the SRAM memory cell are greatly improved, and the power consumption of the memory cell is reduced.

Description

14T radiation-resistant SRAM memory unit and circuit modules, structures and chips based on it

Technical field

The invention relates to an SRAM memory unit, in particular to a 14T radiation-resistant SRAM memory unit, a circuit module based on a 14T radiation-resistant SRAM memory unit, and a circuit module based on a 14T radiation-resistant SRAM memory unit. Circuit structure, a circuit chip based on 14T radiation-resistant SRAM memory unit.

Background technique

The radiation effect in space will cause a Single Event Effect (SEE) to the working Static Random Access Memory (SRAM). Single event effects can cause both hard and soft errors in electronic devices. The occurrence of hard errors will cause damage to the physical level of the device, leading to catastrophic consequences; while soft errors mainly affect the working status of the device, making it unable to transmit correct information. Since the energy of space radiation particles is limited, the probability of causing soft errors in the device is much greater than the probability of causing hard errors in the device. Among soft errors, the probability of a Single Event Upset (SEU) is much greater than the probability of other types of errors. In order to improve the unit's ability to resist SEU, the existing technology mainly includes the following solutions:

1) Figure 1 shows the structural diagram of a DICE12T circuit that resists single particle flipping proposed by T.Calin, M.Nicolaidis and R.Velazco in 1996. It has 4 storage nodes and 4 transmission pipes. When an SEU occurs on each single storage node, the node will eventually be recovered by the remaining nodes. However, when SEU occurs on any two storage nodes, the storage information of the circuit node will be flipped and unable to self-recovery, resulting in erroneous data.

2) Figure 2 shows the structural diagram of a Soft Error Tolerant 10T SRAM Bit-Cell (QUATRO10T) circuit proposed by Shah M. Jahinuzzaman and David J. Rennie in 2009. Compared with the traditional six-tube unit structure, it has better SEU resistance, but the unit's writing ability is poor, and its holding noise margin (Hold Static Noise Margin, abbreviated as HSNM) is different from the read static noise margin (HSNM). Read Static NoiseMargin, abbreviated as RSNM) is poor.

3) Figure 3 is a schematic structural diagram of the SAR14T circuit proposed by Soumitra Pal in 2021. This circuit uses 4 NMOS transistors to write data inside the unit, but uses 2 NMOS transistors to read through external nodes. This causes the unit to have a large read latency.

4) Figure 4 is a schematic structural diagram of the RSP14T circuit proposed by Chunyu Peng in 2019. This circuit uses source isolation technology. When the unit stores "1", the stacked PMOS structure connects the transistor P2 to the weak signal "1" , so the amount of charge collected by the drain of transistor P2 will be reduced, the resistance of node QB to SEU is improved, and the unit becomes more stable.

5) Figure 5 shows the structural diagram of the Radiation Hardened ByDesign SRAM bit-cell (RHBD14T) circuit proposed by Naga Raghuram CH in 2021. This circuit uses polarity reinforcement technology, which reduces the number of sensitive nodes, but results in larger read and write delays and lower noise margin (SNM) values.

To sum up, it is difficult for existing SRAM memory cells to improve their read and write efficiency while maintaining good SEU resistance, resulting in high power consumption of SRAM memory cells.

Contents of the invention

Based on this, it is necessary to provide a 14T radiation-resistant SRAM memory unit and a circuit module, structure and chip based on it to solve the problem that existing SRAM memory cells are difficult to balance SEU resistance and low power consumption performance.

The present invention is realized through the following technical solution: a 14T radiation-resistant SRAM memory unit includes 6 NMOS transistors N1 to N6 and 8 PMOS transistors P1 to P8.

The drain of P1 is electrically connected to the sources of P3 and P6, the drain of P7, and the gates of P2, P6, and N4 respectively, forming storage node S0. The gate of P1 is electrically connected to the drains of P2 and P8, the sources of P4 and P5, and the gates of P5 and N3 respectively, forming storage node S1. The sources of P1 and P2 are electrically connected to the power supply VDD. The sources of N1, N2, N3, and N4 are electrically grounded. The drain of N1 is electrically connected to the gates of P3 and N2, and the drains of P5 and N5 respectively, forming a storage node Q. The gate of N1 is electrically connected to the drains of N2, P6, N6 and the gate of P4 respectively to form storage node QB. The gates of N5 and N6 are electrically connected to the word line WL. The gates of P7 and P8 are electrically connected to the word line WLB. The sources of N5 and N7 are electrically connected to the bit line BL. The sources of N6 and N8 are electrically connected to the bit line BLB. The drain of P3 is electrically connected to the drain of N3. The drain of P4 is electrically connected to the drain of N4.

The above-mentioned RHDS-14T radiation-resistant SRAM memory unit is designed using the polarity reinforcement principle of different types of transistors with single flip characteristics under space heavy ion bombardment, ensuring the stability of redundant storage nodes S0 and S1, thereby strengthening the circuit Anti-flip capability of internal nodes. Secondly, by multiplexing pull-up PMOS tubes and using source isolation technology, the stability of storage nodes Q and QB is improved. During the process of writing data, the bit lines simultaneously write data to the internal nodes Q\QB and S0\S1 through the transmission transistors N5, N6, P7, and P8, making it easier for the storage nodes to be written with data, which greatly improves the unit's Data writing speed and noise tolerance reduce the power consumption of the storage unit.

In one embodiment, when the SRAM memory cell is in the retention phase, the bit line BL and the bit line BLB are both precharged to a high level, the word line WL is a low level, and the word line WLB is a high level. level.

In one embodiment, during the reading phase of the SRAM memory cell, the bit line BL and the bit line BLB are both precharged to a high level, the word line WL is a high level, and the word line WLB is Low level, N5, N6, P7 and P8 are turned on.

In one embodiment, when the data stored in the SRAM memory cell is '0', then "Q=S0=0, QB=S1=1"; the bit line BL passes through the discharge path 1 and the discharge path 2 Discharge to the ground, causing a voltage difference in the bit line, and then read the data through the sensitive amplifier; the discharge path 1 is to discharge to the ground through P7, P3 and N3: the discharge path 2 is to discharge to the ground through N5 and N1; when When the data stored in the SRAM memory cell is '1', then "Q=S0=1, QB=S1=0"; the bit line BLB discharges to the ground through the discharge path 3 and the discharge path 4, causing the bit line to generate The voltage difference is then read out through a sense amplifier; the discharge path 3 discharges to the ground through P8, P4 and N4; the discharge path 4 discharges to the ground through N6 and N2.

In one embodiment, during the writing phase of the SRAM memory cell, the word line WL is high level and the word line WLB is low level. When the bit line BL is high level and BLB is low level, N5 and P7 respectively write '1' to the storage node Q point and S0 point; when the bit line BL is low level and the bit line BLB is high level, write '1' to the storage node QB point and S1 point respectively through N6 and P8 Write '0'.

In one embodiment, the lengths of the NMOS transistors N1 to N6 and the PMOS transistors P1 to P8 are all 65 nm; among them, the widths of P1, P2, P5, and P6 are all 80 nm, and the widths of P3, P4, N1, N2, N3, and N4 are 280nm wide; all other transistors are 140nm wide.

The present invention also provides a circuit module based on a 14T radiation-resistant SRAM memory unit. The circuit module adopts the circuit layout of the above-mentioned 14T radiation-resistant SRAM memory unit.

The present invention also provides a circuit structure based on 14T radiation-resistant SRAM memory cells. The circuit structure includes a plurality of the above-mentioned 14T radiation-resistant SRAM memory cells, and a plurality of the SRAM memory cells are arranged in an array.

In one embodiment, in the circuit structure, in the SRAM memory cells located in the same row, the gates of all N5 and N6 are electrically connected to the word line WL; the gates of all P7 and P8 are electrically connected to the word line. WLB; all the sources of P1 and P2 are electrically connected to the power supply VDD; all the sources of N1, N2, N3, and N4 are electrically connected to ground;

In the SRAM memory cells located in the same column, the sources of all N5 and N7 are electrically connected to the bit line BL; the sources of all N6 and N8 are electrically connected to the bit line BLB.

The present invention also provides a circuit chip based on a 14T radiation-resistant SRAM memory unit. The circuit chip is packaged using the above-mentioned circuit structure based on a 14T radiation-resistant SRAM memory unit.

Compared with the prior art, the present invention has the following beneficial effects:

The invention adopts the polarity reinforcement principle in which different types of transistors have a single flipping characteristic under space heavy ion bombardment for design, ensuring the stability of redundant storage nodes S0 and S1, thereby enhancing the anti-flip ability of the internal nodes of the circuit. Secondly, by multiplexing pull-up PMOS tubes and using source isolation technology, the stability of storage nodes Q and QB is improved. During the process of writing data, the bit lines simultaneously write data to the internal nodes Q\QB and S0\S1 through the transmission transistors N5, N6, P7, and P8, making it easier for the storage nodes to be written with data, which greatly improves the unit's Data writing speed and noise tolerance reduce the power consumption of the storage unit.

Description of drawings

Figure 1 is a schematic structural diagram of a DICE circuit in the background technology of the present invention;

Figure 2 is a schematic structural diagram of the QUATRO 10T circuit in the background technology of the present invention;

Figure 3 is a schematic structural diagram of the SAR14T circuit in the background technology of the present invention;

Figure 4 is a schematic structural diagram of the RSP14T circuit in the background technology of the present invention;

Figure 5 is a schematic structural diagram of the RHBD14T circuit in the background technology of the present invention;

Figure 6 is a schematic structural diagram of a 14T radiation-resistant SRAM memory unit in Embodiment 1 of the present invention;

Figure 7 is a timing waveform diagram of the 14T radiation-resistant SRAM memory unit circuit in Embodiment 1 of the present invention;

Figure 8 is a transient waveform simulation diagram of the 14T radiation-resistant SRAM memory unit circuit in Embodiment 1 of the present invention, where different nodes are injected with double-exponential current source pulses at different times;

Figure 9 is a comparison diagram of HSNM, RSNM, and WSNM of the SRAM memory unit in the prior art in Embodiment 1 of the present invention and the 14T radiation-resistant SRAM memory unit in this embodiment;

Figure 10 is a schematic structural diagram of a circuit module based on a 14T radiation-resistant SRAM memory unit according to Embodiment 2 of the present invention;

FIG. 11 is a schematic structural diagram of a circuit structure based on a 14T radiation-resistant SRAM memory unit according to Embodiment 3 of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

It should be noted that when a component is said to be "mounted on" another component, it can be directly on the other component or there can also be an intermediate component. When a component is said to be "set on" another component, it can be directly set on the other component or there may be a centered component at the same time. When a component is said to be "anchored" to another component, it can be directly anchored to the other component or there may be an intermediate component present as well.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the invention belongs. The terminology used herein in the description of the invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. As used herein, the term "or/and" includes any and all combinations of one or more of the associated listed items.

Example 1

Please refer to FIG. 6 , which is a schematic structural diagram of a 14T radiation-resistant SRAM memory unit in this embodiment. The 14T radiation-resistant SRAM memory unit includes 6 NMOS transistors N1~N6 and 8 PMOS transistors P1~P8.

Among them, PMOS transistors P1 and P2 are cross-coupled. PMOS transistors P1, P2, P5 and P6 serve as pull-up transistors, PMOS transistors P3 and P4 serve as pull-down transistors, and their states are controlled by storage nodes Q and QN respectively. Transistors P1 and N3, P2 and N4 respectively constitute inverters, and PMOS transistors P3 and P4 are respectively inserted between the two inverters. The two main storage nodes Q and QN are electrically connected to the bit line BL and the bit line BLB respectively through two NMOS transistors N5 and N6, and the two redundant storage nodes S0 and S1 are respectively connected to the bit line BL through two PMOS transistors P7 and P8. Electrically connected to bit line BLB. Among them, the two NMOS transistors N5 and N6 are controlled by the word line WL, and the two PMOS transistors P7 and P8 are controlled by the word line WLB.

The connection relationship between the transistors of the SRAM memory unit is as follows:

The drain of P1 is electrically connected to the sources of P3 and P6, the drain of P7, and the gates of P2, P6, and N4 respectively, forming storage node S0. The gate of P1 is electrically connected to the drains of P2 and P8, the sources of P4 and P5, and the gates of P5 and N3 respectively, forming storage node S1. The sources of P1 and P2 are electrically connected to the power supply VDD. The sources of N1, N2, N3, and N4 are electrically grounded. The drain of N1 is electrically connected to the gates of P3 and N2, and the drains of P5 and N5 respectively, forming a storage node Q. The gate of N1 is electrically connected to the drains of N2, P6, N6 and the gate of P4 respectively to form storage node QB. The gates of N5 and N6 are electrically connected to the word line WL. The gates of P7 and P8 are electrically connected to the word line WLB. The sources of N5 and N7 are electrically connected to the bit line BL. The sources of N6 and N8 are electrically connected to the bit line BLB. The drain of P3 is electrically connected to the drain of N3. The drain of P4 is electrically connected to the drain of N4.

Specifically, in this embodiment, the circuit connection relationship of the 14T radiation-resistant SRAM unit can be summarized as:

The bit line BL is electrically connected to the sources of the transmission transistors N5 and P7. Bit line BLB is electrically connected to the sources of transistors N6 and P8. Word line WL is electrically connected to the gates of pass transistors N5 and N6. Word line WLB is electrically connected to the gates of pass transistors P7 and P8. The power supply VDD is electrically connected to the sources of the PMOS transistors P1 and P2. The sources of the NMOS transistors N1, N2, N3, and N4 are electrically grounded.

The drain of PMOS transistor P1 is electrically connected to the sources of PMOS transistors P3 and P6, the gates of PMOS transistors P2 and P6, and the gate of NMOS transistor N4, and the gate of PMOS transistor P1 is electrically connected to the drain of PMOS transistor P2, PMOS The sources of the transistors P4 and P5, the gates of the PMOS transistors P5, and the gates of the NMOS transistors N3 are electrically connected.

The drain of PMOS transistor P2 is electrically connected to the sources of PMOS transistors P4 and P5, the gates of PMOS transistors P1 and P5, and the gate of NMOS transistor N3, and the gate of PMOS transistor P2 is connected to the drain of PMOS transistor P1, PMOS The source of the transistor P3 and P6, the gate of the PMOS transistor P6, and the gate of the NMOS transistor N4 are electrically connected.

The drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N3, and the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N2, the drain of the NMOS transistor N1, and the drain of the PMOS transistor P5.

The drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N4, and the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N1, the drain of the NMOS transistor N2, and the drain of the PMOS transistor P6.

The source of PMOS transistor P5 is electrically connected to the drain of PMOS transistor P2, the source of PMOS transistor P4, the gates of PMOS transistors P1 and P5, and the gate of NMOS transistor N3. The gate of PMOS transistor P5 is connected to the gate of PMOS transistor P4. The source of P5, the gate of PMOS transistor P1, and the gate of NMOS transistor N3 are electrically connected, and the drain of PMOS transistor P5 is connected to the gate of NMOS transistor N2, the drain of NMOS transistor N1, and the gate of PMOS transistor P3. Electrical connection.

The source of PMOS transistor P6 is electrically connected to the source of PMOS transistor P3, the drain of PMOS transistor P1, the gates of PMOS transistors P2 and P6, and the gate of NMOS transistor N4. The gate of PMOS transistor P6 is connected to the gate of PMOS transistor P3. The source of P6, the drain of PMOS transistor P1, the gate of PMOS transistor P2, and the gate of NMOS transistor N4 are electrically connected, and the drain of PMOS transistor P6 is connected to the gate of NMOS transistor N1, the drain of NMOS transistor N2, The gate of PMOS transistor P4 is electrically connected.

The drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P5, the gate of the PMOS transistor P3, and the gate of the NMOS transistor N2, and the gate of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N2 and the drain of the PMOS transistor P6. pole and the gate of PMOS transistor P4 are electrically connected.

The drain of the NMOS transistor N2 is electrically connected to the gate of the NMOS transistor N1, the gate of the PMOS transistor P4, and the drain of the PMOS transistor P6, and the gate of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N1 and the drain of the PMOS transistor P5. pole and the gate of PMOS transistor P3 are electrically connected.

The drain of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P3, and the gate of the NMOS transistor N3 is electrically connected to the sources of the PMOS transistors P4 and P5, the gates of the PMOS transistors P1 and P5, and the drain of the PMOS transistor P2. .

The drain of NMOS transistor N4 is electrically connected to the drain of PMOS transistor P4, and the gate of PMOS transistor P3 is electrically connected to the source of P6, the gates of PMOS transistors P2 and P6, and the drain of PMOS transistor P1.

The drain of the transfer transistor N5 is electrically connected to the drain of the NMOS transistor N1. The drain of the transfer transistor N6 is electrically connected to the drain of the NMOS transistor N2. The drain of the transfer transistor P7 is electrically connected to the drain of the PMOS transistor P1. The drain of the transfer transistor P8 is electrically connected to the drain of the PMOS transistor P2.

Please refer to FIG. 7 , which is a timing waveform diagram of the 14T radiation-resistant SRAM memory unit circuit of this embodiment. Among them, the simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 1.2V. The principle of the RHDS-14T radiation-resistant SRAM memory unit in this embodiment is as follows:

In the holding phase, both bit line BL and bit line BLB are precharged to high level, word line WL is low level, word line WLB is high level, the circuit interior maintains the initial state, and the circuit does not work.

When in the data reading phase, both bit line BL and bit line BLB are precharged to high level, word line WL is high level, word line WLB is low level, and transfer transistors N5, N6, P7 and P8 are turned on. If the data stored in the SRAM memory cell is '0', then "Q=S0=0, QB=S1=1", then BL discharges to the ground through discharge path 1 and discharge path 2, causing a voltage difference in the bit line, and then through The sense amplifier reads the data. Among them, the discharge path 1 is: discharging to the ground through the transistors P7, P3 and N3. The discharge path 2 is to discharge to the ground through the transistors N5 and N1. If the data stored in the SRAM memory unit is ‘1’, then “Q=S0=1, QB=S1=0”. Then the BLB discharges to the ground through the discharge path 3 and the discharge path 4, causing a voltage difference in the bit line, and then the data is read out through the sense amplifier. Among them, the discharge path 3 is: discharging to the ground through the transistors P8, P4 and N4. The discharge path 4 is to discharge to the ground through the transistors N6 and N2.

In the data writing phase, word line WL is high level and word line WLB is low level. If the bit line BL is high level and the bit line BLB is low level, then '1' is written to the storage node Q point and S0 point respectively through the transmission transistor N5 and P7. If bit line BL is low level and bit line BLB is high level, then '1' is written to storage nodes QB point and S1 point respectively through transfer transistors N6 and P8. During the writing process, data is written to the internal nodes Q\S0 and QB\S1 simultaneously through the transmission transistors N5 and P7 and N6 and P8, making it easier for the storage node to write data, so the writing speed will be greatly improved. At the same time, the power consumption of the circuit is reduced due to the large increase in writing speed.

As shown in Figure 7, even if the voltages of bit line BL and bit line BLB are bombarded by single particles, the 14T radiation-resistant SRAM memory cell of this embodiment can still perform normal reading and writing operations, and even if the storage nodes S0 and S1 If a flip occurs, it can still be restored to the initial state by nodes Q and QB.

Please refer to FIG. 8 , which is a transient waveform simulation diagram of the 14T radiation-resistant SRAM memory unit circuit of this embodiment when different nodes are injected with dual-exponential current source pulses at different times. Among them, the simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 1.2V.

When only considering the improvement of the anti-irradiation performance of the circuit structure, if the storage node of the circuit is bombarded by particles, since the storage nodes S0 and S1 are surrounded by PMOS transistors, according to the polarity reinforcement principle, the space particles bombard the sensitive node PMOS transistor, at the node Only a "0-1" voltage pulse is generated, and this pulse cannot affect the state of other transistors due to the existence of the gate capacitance, which effectively prevents external nodes S0 and S1 from flipping. At the same time, the stability of the S0 and S1 node data ensures that the internal storage nodes Q and QB can be restored to the initial state after flipping, thereby improving the circuit's ability to resist SEU. Storage nodes Q and QB are reinforced with source isolation technology, which improves the circuit's ability to withstand SEU. If other non-critical nodes are bombarded by particles, the storage unit is less susceptible to impact.

Simulation

1. Simulation conditions

The simulation conditions are: Comer: TT; Temperature: 27℃; VDD: 1.2V.

2. Simulation objects

Control group: DICE circuit, QUATRO 10T circuit, SAR14T circuit, RSP14T circuit, RHBD14T circuit.

Experimental group: RHDS-14T radiation-resistant SRAM memory unit (RHDS-14T circuit) of this embodiment.

3. Simulation process and simulation results

Connect the five circuits in the control group and the circuits in the experimental group to 1.2V VDD respectively, and then perform read and write operations respectively, and record the corresponding delay time, power consumption and critical charge. The simulation results are as shown in Table 1 and As shown in Table 2, Table 1 is a comparison table of the circuit area, read and write time and power consumption simulation of the SRAM memory unit in the prior art and the 14T radiation-resistant SRAM memory unit of this embodiment. Comparison table of critical charges between SRAM memory cells and the 14T radiation-resistant SRAM memory cell of this embodiment.

Table 1

unit Area (μm ² ) Read latency (ps) Write latency (ps) Power consumption (μW) DICE 8.97 24.97 31.4 8 Quatro 7.48 252.4 48.48 7.664 SAR14T 11.03 19.5 30.97 7.968 RSP14T 10.96 21.1 32 7.928 RHBD14T 9.85 61.4 36.3 7.84 RHDS-14T 10.44 31.56 twenty four 6.8

Table 2

It can be seen from Table 1 that the write delay of the RHDS→14T radiation-resistant SRAM memory unit of this embodiment is significantly lower than that of the other five circuits, and the power consumption is also lower than the other five circuits. As can be seen from Table 2, the critical charge of the RHDS-14T radiation-resistant SRAM memory unit of this embodiment and the critical charges of the DICE circuit, SAR14T circuit, and RHBD14T circuit are all higher than 50fC, that is, the RHDS-14T radiation-resistant SRAM The memory unit can prevent single-particle flipping in an environment below 50fC and has strong SEU resistance.

Please refer to FIG. 9 , which is a comparison chart of HSNM, RSNM, and WSNM of the SRAM memory unit in the prior art in Embodiment 1 of the present invention and the 14T radiation-resistant SRAM memory unit in this embodiment. It can be seen from Figure 9 that compared with existing SRAM memory cells, the 14T radiation-resistant SRAM memory unit of this embodiment has a higher noise margin (SNM).

It can be seen that the RHDS-14T anti-radiation SRAM memory unit provided in this embodiment can improve the anti-SEU capability of the SRAM memory unit circuit, greatly increase the speed of the unit at the expense of a smaller unit area, and reduce the Power consumption of SRAM memory cells.

Example 2

In order to implement the application of the 14T radiation-resistant SRAM memory unit as in Embodiment 1, this embodiment provides a circuit module based on the 14T radiation-resistant SRAM memory unit. Please refer to FIG. 10 , which is a schematic structural diagram of a circuit module based on a 14T radiation-resistant SRAM memory unit in this embodiment. This circuit module adopts the circuit layout of the 14T radiation-resistant SRAM memory unit in Embodiment 1. Specifically, the circuit module includes 6 connection terminals.

Among them, the first connection terminal 1 is electrically connected to the word line WL through the gates of N5 and N6. The second connection terminal 2 is electrically connected to the word line WLB through the gates of P7 and P8. The third connection terminal 3 is electrically connected to the power supply VDD through the sources of P1 and P2. The fourth connection terminal 4 is electrically grounded through the sources of N1, N2, N3 and N4. The fifth connection terminal 5 is electrically connected to the bit line BL through the sources of N5 and N7. The sixth connection terminal 6 is electrically connected to the bit line BLB through the sources of N6 and N8.

Example 3

This embodiment provides a circuit structure based on a 14T radiation-resistant SRAM memory unit. Please refer to FIG. 11 , which is a schematic structural diagram of the circuit structure based on the 14T radiation-resistant SRAM memory unit in this embodiment. In Figure 11, the RHDS-14T unit is a 14T radiation-resistant SRAM memory unit. The circuit structure includes a plurality of 14T radiation-resistant SRAM memory cells as provided in Embodiment 1, and a plurality of SRAM memory cell arrays are arranged to realize the integrated application of SRAM memory cells.

In the circuit structure of this embodiment, in the SRAM memory cells located in the same row, the gates of all N5 and N6 are electrically connected to the word line WL. The gates of all P7 and P8 are electrically connected to the word line WLB. The sources of all P1 and P2 are electrically connected to the power supply VDD. The sources of all N1, N2, N3, and N4 are electrically grounded. That is, the SRAM memory cells in the same row are controlled by the same word line WL and the same word line WLB.

In the SRAM memory cells located in the same column, the sources of all N5 and N7 are electrically connected to the bit line BL. The sources of all N6 and N8 are electrically connected to the bit line BLB. That is, SRAM memory cells in the same column are controlled by the same bit line BL and the same bit line BLB.

Example 4

This embodiment provides a circuit chip based on a 14T radiation-resistant SRAM memory unit. The circuit chip is packaged using the circuit structure based on the 14T radiation-resistant SRAM memory unit of Embodiment 3. The mode of packaging into chips makes it easier to promote and apply 14T radiation-resistant SRAM memory cells.

In the circuit chip of this embodiment, the gates of all N5 and N6 of the SRAM memory cells located in the same row are electrically connected to the word line WL, thereby leading to the first pin. The gates of all P7 and P8 are electrically connected to the word line WLB, thereby leading to the second pin. The sources of all P1 and P2 are electrically connected to the power supply VDD, which leads to the third pin. The sources of all N1, N2, N3, and N4 are electrically grounded, which leads to the fourth pin.

For SRAM memory cells located in the same column, the sources of all N5 and N7 are electrically connected to the bit line BL, which leads to the fifth pin. The sources of all N6 and N8 are electrically connected to the bit line BLB, thereby leading to the sixth pin.

The technical features of the above-described embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, All should be considered to be within the scope of this manual.

The above-mentioned embodiments only express several implementation modes of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims (10)

1. A 14T radiation-resistant SRAM memory unit, characterized in that it includes 6 NMOS transistors N1~N6 and 8 PMOS transistors P1~P8; The drain of P1 is electrically connected to the sources of P3 and P6, the drain of P7, and the gates of P2, P6, and N4 to form storage node S0; The gate of P1 is electrically connected to the drains of P2 and P8, the sources of P4 and P5, and the gates of P5 and N3 respectively, forming storage node S1; The sources of P1 and P2 are electrically connected to the power supply VDD; The sources of N1, N2, N3, and N4 are electrically grounded; The drain of N1 is electrically connected to the gates of P3 and N2, and the drains of P5 and N5 respectively, forming storage node Q; The gate of N1 is electrically connected to the drains of N2, P6, N6, and the gate of P4 respectively to form storage node QB; The gates of N5 and N6 are electrically connected to the word line WL; The gates of P7 and P8 are electrically connected to the word line WLB; The sources of N5 and N7 are electrically connected to the bit line BL; The sources of N6 and N8 are electrically connected to the bit line BLB; The drain of P3 is electrically connected to the drain of N3; the drain of P4 is electrically connected to the drain of N4. 2. The 14T radiation-resistant SRAM memory unit according to claim 1, characterized in that, in the retention phase of the SRAM memory unit, both the bit line BL and the bit line BLB are precharged to a high level, The word line WL is at a low level, and the word line WLB is at a high level. 3. The 14T radiation-resistant SRAM memory unit according to claim 1, characterized in that, in the reading phase of the SRAM memory unit, both the bit line BL and the bit line BLB are precharged to a high level. , the word line WL is at a high level, the word line WLB is at a low level, and N5, N6, P7 and P8 are turned on. 4. The 14T radiation-resistant SRAM memory unit according to claim 3, characterized in that when the data stored in the SRAM memory unit is '0', then "Q=S0=0, QB=S1=1 "; The bit line BL is discharged to the ground through the discharge path 1 and the discharge path 2, causing a voltage difference in the bit line, and then the data is read out through the sensitive amplifier; the discharge path 1 is discharged to the ground through P7, P3 and N3: The discharge path 2 discharges to the ground through N5 and N1; when the data stored in the SRAM memory unit is '1', then "Q=S0=1, QB=S1=0"; the bit line BLB passes through The discharge path 3 and the discharge path 4 discharge to the ground, causing a voltage difference in the bit line, and then the data is read out through the sensitive amplifier; wherein the discharge path 3 discharges to the ground through P8, P4 and N4; the discharge path 4 is Discharge to ground through N6 and N2. 5. The 14T radiation-resistant SRAM memory unit according to claim 1, characterized in that, in the writing phase of the SRAM memory unit, the word line WL is high level and the word line WLB is low level. When the bit line BL is high level and BLB is low level, write '1' to the storage node Q point and S0 point respectively through N5 and P7; when the bit line BL is low level and the bit line BLB is When the level is high, '0' is written to the storage node QB point and S1 point through N6 and P8 respectively. 6. The 14T radiation-resistant SRAM memory unit according to claim 1, characterized in that the lengths of the NMOS transistors N1~N6 and the PMOS transistors P1~P8 are all 65nm; wherein, the widths of P1, P2, P5, and P6 They are all 80nm, and the widths of P3, P4, N1, N2, N3 and N4 are all 280nm; the widths of all other transistors are 140nm. 7. A circuit module based on a 14T radiation-resistant SRAM memory unit, characterized in that it adopts the circuit layout of the 14T radiation-resistant SRAM memory unit according to any one of claims 1 to 6. 8. A circuit structure based on a 14T radiation-resistant SRAM memory unit, characterized in that it includes a plurality of 14T radiation-resistant SRAM memory cells as claimed in any one of claims 1 to 6, and a plurality of the Describe the SRAM memory cell array setup. 9. The circuit structure based on the 14T radiation-resistant SRAM memory unit according to claim 8, characterized in that in the circuit structure, in the SRAM memory cells located in the same row, the gates of all N5 and N6 are equal. The gates of all P7 and P8 are electrically connected to the word line WLB; the sources of all P1 and P2 are electrically connected to the power supply VDD; the sources of all N1, N2, N3, and N4 are electrically connected. ground; In the SRAM memory cells located in the same column, the sources of all N5 and N7 are electrically connected to the bit line BL; the sources of all N6 and N8 are electrically connected to the bit line BLB. 10. A circuit chip based on a 14T radiation-resistant SRAM memory unit, characterized in that it is packaged using the circuit structure based on a 14T radiation-resistant SRAM memory unit as claimed in any one of claims 8 to 9. become.