CN108492843B - 14T radiation-resistant static storage unit - Google Patents
14T radiation-resistant static storage unit Download PDFInfo
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- CN108492843B CN108492843B CN201810300515.1A CN201810300515A CN108492843B CN 108492843 B CN108492843 B CN 108492843B CN 201810300515 A CN201810300515 A CN 201810300515A CN 108492843 B CN108492843 B CN 108492843B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
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Abstract
本发明公开了一种14T抗辐照静态存储单元，能够提高抗SEU能力，可以在牺牲较小单元面积的情况下大幅度提高单元的速度，并且降低了功耗。在读写阶段，WL信号为高电平。当电路处于写阶段时，如果BL为高电平，BLB为低电平，那么通过差分输入晶体管N4和N5向存储节点Q点写‘1’；如果BL为低电平，BLB为高电平，那么通过差分输入晶体管N4和N5向存储节点Q点写‘0’。当电路处于读阶段时，BL和BLB都为高电平，如果该单元电路存储的数据为‘1’，那么BLB通过晶体管N4和N0向地放电，使得位线产生电压差，然后通过灵敏放大器读出数据；如果该单元电路存储的数据为‘0’，那么BL通过晶体管N5和N1向地放电，使得产生位线电压差，然后通过灵敏放大器读出数据。
The invention discloses a 14T anti-radiation static memory cell, which can improve the anti-SEU capability, can greatly improve the speed of the cell under the condition of sacrificing a small cell area, and reduce the power consumption. In the read and write phase, the WL signal is high. When the circuit is in the writing stage, if BL is high and BLB is low, then write '1' to the storage node Q through differential input transistors N4 and N5; if BL is low, BLB is high , then write '0' to the storage node Q point through the differential input transistors N4 and N5. When the circuit is in the read phase, both BL and BLB are high. If the data stored in the unit circuit is '1', then BLB is discharged to ground through transistors N4 and N0, so that the bit line generates a voltage difference, and then passes through the sense amplifier. Read data; if the data stored in the unit circuit is '0', then BL is discharged to ground through transistors N5 and N1, so that a bit line voltage difference is generated, and then the data is read out through the sense amplifier.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a unit circuit structure capable of improving the writing speed of a storage unit, reducing the power consumption of the unit and improving the Single Event Upset (SEU) resistance of the unit, and belongs to a 14T radiation-resistant static storage unit.
Background
With the reduction of the characteristic size and the power supply voltage, the circuit is more and more sensitive to irradiation, and a Single Event Effect (SEE for short) becomes an inevitable problem, so that the development of the SEE irradiation resistance reinforcement technology in the combined circuit is very urgent. SEU is a form of SEE, which is soft error, non-destructive. When heavy ion particles are incident on the semiconductor material, excess charges will be ionized and these excess charges will be collected by the electrodes of the device, resulting in errors in the data of the memory cells or abnormal changes in the logic state of the circuit nodes, resulting in soft errors in the integrated circuit system. Static Random Access Memory (SRAM) is more susceptible to soft errors due to its higher sensitivity per bit and lower node capacitance. In addition, the Soft Error rate (Soft Error Rat, abbreviated as SER) in SRAM increases with the development of nanotechnology. In order to improve the SEU resistance of the unit, the prior art mainly comprises the following schemes:
1) fig. 1 shows a Soft Error Tolerant 10T SRAM BitCell (Quatro 10T) circuit proposed in 2009 by Shah m, jahinuzzaman and David j, rennie, which is composed of four PMOS transistors and six NMOS transistors, of which two NOMS transistors are differential input transistors. Compared with a traditional six-pipe unit and a Dual Interlocked Storage Cell (DICE) structure, the six-pipe unit has better SEU resistance, but the unit has poor write margin and large power consumption.
2) Fig. 2 and 3 show two new Sort of Error Hardened 10T SRAM Cells circuits proposed In 2012 by In-Seok Jung and Yong-Bin Kim, which are respectively two circuit structures of Hardened NMOS stacked 10T SRAM cell (NS10T) and Hardened PMOS stacked 10T SRAM cell (PS10T), wherein the NS10T circuit can only recover the flip from 0 to 1, the PS10T can only recover the flip from 1 to 0, and both the circuits can solve the multi-node disturbance problem caused by charge sharing, but the two circuits have slow writing speed and large power consumption.
3) FIG. 4 shows a Novel Low-Power and high-level Reliable Radiation secured Memory Cell (RHM12T) circuit proposed by Jung Guo and Liyi Xiao in 2014, which has the advantages of Low Power consumption, small sensitive area and the like, can solve the problem of multi-node disturbance caused by charge sharing, and improves the SEU resistance of the circuit. But this circuit has slow writing speed and poor reading capability.
4) Fig. 5 shows a high valid Memory Cell (RHD12T) circuit proposed by Chunhua Qi and Liyi Xiao in 2016, which greatly enhances the anti-SEU capability of the circuit by using a source isolation technique, and not only improves the anti-SEU capability of a single node but also improves the anti-multi-node flip capability, but also has slow writing speed and large power consumption.
Disclosure of Invention
The invention aims to provide a 14T radiation-resistant static memory cell, which can improve the writing speed of the memory cell, reduce the power consumption of the cell and improve the single-event upset resistance of the cell.
The purpose of the invention is realized by the following technical scheme:
a 14T radiation-resistant static memory cell, comprising: six NMOS transistors and eight PMOS transistors; the six NMOS transistors are sequentially marked as N0-N5, and the eight PMOS transistors are sequentially marked as P0-P7; the PMOS transistor P1 and the NMOS transistor N1 form an inverter, the PMOS transistor P0 and the NMOS transistor N0 form another inverter, the two inverters form a cross-coupling structure, and the differential input transistors N4 and N5 form a standard six-transistor unit; PMOS transistors P2 and P3 isolate the standard six-transistor cell from VDD, and PMOS transistors P6 and P7 correspondingly isolate PMOS transistors P4 and P5 from VDD; wherein:
the bit line BL is electrically connected to the sources of the differential input transistors N5; bit line BLB is electrically connected to the sources of differential input transistors N4; the word line WL is electrically connected to the gates of the differential input transistors N4 and N5; the drain of the differential input transistor N4 is electrically connected to the drain of the PMOS transistor P0; the drain of the differential input transistor N5 is electrically connected to the drain of the PMOS transistor P1; VDD is electrically connected with the sources of PMOS transistors P2, P3, P6 and P7;
the drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P1, and the gate of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N3;
the drain of the PMOS transistor P3 is electrically connected to the source of the PMOS transistor P0, and the gate of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N2;
the drain of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P4, and the gate of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N3;
the drain of the PMOS transistor P7 is electrically connected to the source of the PMOS transistor P5, and the gate of the PMOS transistor P7 is electrically connected to the gate of the NMOS transistor N2;
the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N3, and the gate of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2;
the drain of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N3;
the drain of the PMOS transistor P1 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1;
the drain of the PMOS transistor P0 is electrically connected to the drain of the NMOS transistor N0, and the gate of the PMOS transistor P0 is electrically connected to the gate of the NMOS transistor N0;
the gate of the NMOS transistor N2 is electrically connected with the drain of the NMOS transistor N0; the gate of the NMOS transistor N3 is electrically connected with the drain of the NMOS transistor N1; the sources of the NMOS transistors N0, N1, N2, and N3 are electrically connected to GND.
The technical scheme provided by the invention can improve the SEU resistance of the unit, greatly improve the writing speed of the unit under the condition of sacrificing smaller unit area and reduce the power consumption of the unit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a prior art Quatro 10T circuit provided in the background of the present invention;
FIG. 2 is a schematic diagram of a prior art NS10T circuit according to the background of the invention;
FIG. 3 is a schematic diagram of a prior art PS10T circuit according to the background of the invention;
FIG. 4 is a schematic diagram of a prior art RHM12T circuit according to the background of the present invention;
FIG. 5 is a schematic diagram of a prior art RHD12T circuit according to the background of the invention;
FIG. 6 is a schematic structural diagram of a 14T radiation-resistant static memory cell according to an embodiment of the present invention;
FIG. 7 is a timing waveform diagram of a prior art RHD12T circuit and a 14T radiation-resistant static memory cell circuit provided by an embodiment of the invention, a graph of the time required for writing data '0' to the cell versus the simulation (simulation conditions: Corner: TT; Temperature: 25 ℃; VDD: 1.2V).
FIG. 8 is a comparison graph showing simulation comparison of read/write margin, circuit area and power consumption of a prior art RHD12T circuit and a 14T radiation-resistant static memory cell circuit provided by an embodiment of the invention (simulation conditions: Corner: TT; Temperature: 25 ℃; VDD: 1.2V).
Fig. 9 is a schematic top view of the placement positions of the critical transistors in the TCAD simulation software of the 14T radiation-resistant static memory cell circuit according to the embodiment of the present invention.
FIG. 10 is a simulation diagram of waveforms when the 14T radiation-resistant static memory cell circuit provided by the embodiment of the invention bombards the critical node when the incident particle angle is 0 ° (the simulation condition is VDD: 1.2V).
FIG. 11 is a simulation diagram of waveforms of particle bombardment at key nodes of the 14T radiation-resistant static memory cell circuit provided by the embodiment of the invention when the incident particle angles are different at different positions (simulation condition: VDD: 1.2V).
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a 14T radiation-resistant static memory cell, as shown in fig. 6, which mainly includes: six NMOS transistors and eight PMOS transistors; the six NMOS transistors are sequentially marked as N0-N5, and the eight PMOS transistors are sequentially marked as P0-P7; the PMOS transistor P1 and the NMOS transistor N1 form an inverter, the PMOS transistor P0 and the NMOS transistor N0 form another inverter, the two inverters form a cross-coupling structure, and the differential input transistors N4 and N5 form a standard six-transistor unit; PMOS transistors P2 and P3 isolate the standard six-transistor cell from VDD, and PMOS transistors P6 and P7 correspondingly isolate PMOS transistors P4 and P5 from VDD; wherein:
the bit line BL is electrically connected to the sources of the differential input transistors N5; bit line BLB is electrically connected to the sources of differential input transistors N4; the word line WL is electrically connected to the gates of the differential input transistors N4 and N5; the drain of the differential input transistor N4 is electrically connected to the drain of the PMOS transistor P0; the drain of the differential input transistor N5 is electrically connected to the drain of the PMOS transistor P1; VDD is electrically connected with the sources of PMOS transistors P2, P3, P6 and P7;
the drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P1, and the gate of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N3;
the drain of the PMOS transistor P3 is electrically connected to the source of the PMOS transistor P0, and the gate of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N2;
the drain of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P4, and the gate of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N3;
the drain of the PMOS transistor P7 is electrically connected to the source of the PMOS transistor P5, and the gate of the PMOS transistor P7 is electrically connected to the gate of the NMOS transistor N2;
the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N3, and the gate of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2;
the drain of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N3;
the drain of the PMOS transistor P1 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1;
the drain of the PMOS transistor P0 is electrically connected to the drain of the NMOS transistor N0, and the gate of the PMOS transistor P0 is electrically connected to the gate of the NMOS transistor N0;
the gate of the NMOS transistor N2 is electrically connected with the drain of the NMOS transistor N0; the gate of the NMOS transistor N3 is electrically connected with the drain of the NMOS transistor N1; the sources of the NMOS transistors N0, N1, N2, and N3 are electrically connected to GND.
In the embodiment of the invention, the gate of the PMOS transistor P6 is further connected to the storage node Q, and the gate of the PMOS transistor P7 is further connected to the storage node QB, which is favorable for greatly improving the writing speed of the circuit without affecting the read-write margin of the circuit.
In addition, the drains of the PMOS transistors P2 and P3 are connected to the sources of the PMOS transistors P1 and P0, respectively, so that the sources of the PMOS transistors P1 and P0 are isolated from VDD, which helps to improve the capability of the 14T radiation-resistant static memory cell circuit to resist SEU. The drains of the PMOS transistors P6 and P7 are respectively connected with the sources of the PMOS transistors P4 and P5, so that the sources of the PMOS transistors P4 and P5 are isolated from VDD, and the SEU resistance of the 14T radiation-resistant static memory cell circuit is improved.
The principle of the 14T radiation-resistant static storage unit provided by the embodiment of the invention is as follows: in the holding stage, the bit lines BL and BLB are precharged to high level, the word lines are precharged to low level, the circuit is maintained in an initial state, and the circuit is not operated. When in the read data phase, the bit lines BL and BLB are both precharged to high, the word line WL is high, and the differential input transistors N4 and N5 are turned on; if the cell circuit stores data of '1', the BLB is discharged to the ground through the transistors N4 and N0, so that the bit lines generate a voltage difference, and then the data is read out through the sense amplifier; if the cell circuit stores data of '0', BL is discharged to ground through transistors N5 and N1, so that a bit line voltage difference is generated, and then the data is read out through a sense amplifier. In the data writing phase, the word line WL is high, and if BL is high and BLB is low, '1' is written to the storage node Q point through the differential input transistors N4 and N5; if BL is low and BLB is high, '0' is written to the storage node Q through the differential input transistors N4 and N5. When in the writing process, because the transistors P6 and P7 are directly controlled to be turned off or turned on through the point Q and the point QB (namely, indirectly controlled through the bit line), the redundant nodes (S0 and S1) of the circuit are easier to write data, and the storage nodes are easier to write data, so that the writing speed is greatly improved, and meanwhile, the power consumption of the circuit is reduced due to the greatly improved writing speed.
When only the improvement of the radiation resistance of the circuit structure is considered, if the storage node of the circuit is bombarded by particles, the SEU resistance of the circuit is improved due to the fact that the source isolation technology is achieved through the transistors P2 and P3, and due to the fact that the redundant node exists in the circuit, even if the storage node is overturned when the key node is bombarded, the storage node can be recovered through the redundant node, and the SEU resistance is greatly improved; in addition, the capacitance of the PMOS transistor is improved by adding the transistors P6 and P7, and a source isolation technology is realized, so that the influence of irradiation on the redundant node is greatly reduced, and the irradiation resistance of the circuit is further improved. If other non-critical nodes are bombarded by particles, the memory cell is less susceptible.
Therefore, the 14T radiation-resistant static memory cell provided by the embodiment of the invention can improve the SEU resistance of the cell circuit, can greatly improve the speed of the cell under the condition of sacrificing smaller cell area, and reduces the power consumption of the cell.
In order to more clearly show the technical solutions and the technical effects provided by the present invention, the performance of the 14T irradiation-resistant static memory cell circuit provided by the embodiment of the present invention is compared with that of the RHD12T circuit in the prior art with reference to fig. 7 to 11; the concrete content is as follows:
(1) FIG. 7 is a timing waveform diagram of RHD12T circuit in the prior art and a 14T radiation-resistant static memory cell circuit provided by an embodiment of the present invention, comparing the time required for writing data '0' into the cell with a simulation diagram. As can be seen from fig. 7: under the simulation conditions of 1.2V power supply voltage, TT process angle and 25 ℃, the result of transient simulation shows that the speed of writing data into the RHD12T circuit is very slow; the 14T radiation-resistant static memory cell circuit writes data quickly.
(2) As shown in fig. 8, a comparison graph of read-write margin, circuit area and power consumption simulation of a 14T radiation-resistant static memory cell circuit provided by an embodiment of the invention and a prior art RHD12T circuit is shown. As can be seen from fig. 8: under the simulation conditions of 1.2V power supply voltage, TT process angle and 25 ℃, the simulation result shows that the read-write margins of the RHD12T circuit and the 14T radiation-resistant static memory cell circuit are equal, but the power consumption of the RHD12T circuit is larger than that of the 14T radiation-resistant static memory cell circuit.
(3) Fig. 9 is a schematic top view of the placement positions of the critical transistors in the TCAD software of the 14T radiation-resistant static memory cell circuit according to the embodiment of the present invention. Under the assumption that QB is '1', Q is '0', WL is '0', S0 is '1' and S1 is '0', all the turned-off transistors except for the differential input transistors N4 and N5 are built into the model of TCAD simulation software at the positions shown in fig. 9, with the x-z plane parallel to the cell surface and the y-axis perpendicular to the cell surface. As shown in fig. 9, we well designed the layout, and in order to avoid charge sharing between the transistor NMOS0 and other off transistors, we kept N0 away from the off transistors P7, P5, P2, P1, and N3. When a particle bombards P1 or P2, charge sharing between transistors can cause P1 and P2 to be turned on simultaneously so that the Q point is turned to '1', to avoid the situation, P1 and P2 are separated, and P5 and P7 are also separated, which helps to improve the SEU resistance of the circuit.
(4) As shown in fig. 10, it is a waveform simulation diagram of the 14T radiation-resistant static memory cell circuit provided by the embodiment of the present invention when the incident particle angle is 0 ° and the key node is bombarded by particles; the abscissa thereof represents the Time (i.e. Time,in ns) whose ordinate represents Voltage (i.e. Voltage in V). As can be seen from fig. 10: under the simulation condition that VDD is equal to 1.2V, the simulation result shows that the 14T radiation-resistant static memory cell circuit provided by the embodiment of the invention has better SEU resistance when the incident particle angle is 0 DEG, and when LET is 80MeV-cm2Mg, the data of the memory cell does not flip.
(5) As shown in fig. 11, a graph showing simulation waveforms of the key node bombarded at different positions and different incident particle angles of the 14T radiation-resistant static memory cell circuit provided by the embodiment of the present invention is shown, in which the abscissa represents Time (i.e., Time in ns), and the ordinate represents Voltage (i.e., Voltage in V). As can be seen from fig. 11: under the simulation condition that the VDD is 1.2V, the simulation result shows that the 14T radiation-resistant static memory cell circuit provided by the embodiment of the invention has better anti-SEU capability under the bombardment of high-energy particles at the key node at different positions and different angles, and when LET is 78MeV-cm2Mg, no memory cell flip occurred. As can be seen from fig. 7: under the simulation conditions of 1.2V power supply voltage, TT process angle and 25 ℃, the result of transient simulation shows that the write time of the 14T radiation-resistant static memory cell circuit provided by the embodiment of the invention is 298ps, the write time of the RHD12T circuit is 830ps, and the write speed is improved 532 ps. As can be seen from fig. 8: under simulation conditions of TT process angle and 25 ℃, simulation results show that the read-write margin of the proposed 14T radiation-resistant static memory cell circuit is equal to that of the RHD12T circuit, but the power consumption is improved by about 50%.
In summary, the invention provides a 14T radiation-resistant static memory cell circuit, which can improve the SEU resistance of a cell, can greatly improve the speed of the cell at the expense of a smaller cell area, and can reduce the power consumption of the cell.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (1)
1. A 14T radiation-resistant static memory cell, comprising: six NMOS transistors and eight PMOS transistors; the six NMOS transistors are sequentially marked as N0-N5, and the eight PMOS transistors are sequentially marked as P0-P7; the PMOS transistor P1 and the NMOS transistor N1 form an inverter, the PMOS transistor P0 and the NMOS transistor N0 form another inverter, the two inverters form a cross-coupling structure, and the differential input transistors N4 and N5 form a standard six-transistor unit; PMOS transistors P2 and P3 isolate the standard six-transistor cell from VDD, and PMOS transistors P6 and P7 correspondingly isolate PMOS transistors P4 and P5 from VDD; wherein:
the bit line BL is electrically connected to the sources of the differential input transistors N5; bit line BLB is electrically connected to the sources of differential input transistors N4; the word line WL is electrically connected to the gates of the differential input transistors N4 and N5; the drain of the differential input transistor N4 is electrically connected to the drain of the PMOS transistor P0; the drain of the differential input transistor N5 is electrically connected to the drain of the PMOS transistor P1; VDD is electrically connected with the sources of PMOS transistors P2, P3, P6 and P7;
the drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P1, and the gate of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N3;
the drain of the PMOS transistor P3 is electrically connected to the source of the PMOS transistor P0, and the gate of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N2;
the drain of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P4, and the gate of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N3;
the drain of the PMOS transistor P7 is electrically connected to the source of the PMOS transistor P5, and the gate of the PMOS transistor P7 is electrically connected to the gate of the NMOS transistor N2;
the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N3, and the gate of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2;
the drain of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N3;
the drain of the PMOS transistor P1 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1;
the drain of the PMOS transistor P0 is electrically connected to the drain of the NMOS transistor N0, and the gate of the PMOS transistor P0 is electrically connected to the gate of the NMOS transistor N0;
the gate of the NMOS transistor N2 is electrically connected with the drain of the NMOS transistor N0; the gate of the NMOS transistor N3 is electrically connected with the drain of the NMOS transistor N1; the sources of the NMOS transistors N0, N1, N2 and N3 are electrically connected with GND;
the gate of the PMOS transistor P6 is also connected to the storage node Q, and the gate of the PMOS transistor P7 is also connected to the storage node QB, and the PMOS transistors P6 and P7 are directly controlled to be turned off or on by the Q point and the QB point.
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| CN109547006B (en) * | 2018-11-26 | 2022-03-22 | 中北大学 | Anti-radiation D latch |
| CN112259143B (en) * | 2020-10-30 | 2023-02-03 | 安徽大学 | A 14T anti-radiation SRAM memory unit circuit structure with read and write separation |
| CN112562756B (en) * | 2020-12-15 | 2024-03-08 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant sram cell and memory |
| CN113160864B (en) * | 2021-02-26 | 2022-09-09 | 西安电子科技大学 | A Ruggedized Circuit Against Single Event Flip Based on Static Memory |
| CN113764009B (en) * | 2021-08-31 | 2023-06-09 | 安徽大学 | 14T anti-irradiation SRAM memory cell circuit |
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| CN114446349B (en) * | 2022-01-24 | 2025-05-27 | 安徽大学 | A 14T radiation-resistant SRAM storage circuit based on polarity reinforcement technology |
| CN114694709B (en) * | 2022-03-31 | 2025-02-11 | 安徽大学 | A storage unit resistant to power consumption attacks based on digital mechanism |
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| US6510076B1 (en) * | 2002-02-12 | 2003-01-21 | Pmc-Sierra, Inc. | Variable read/write margin high-performance soft-error tolerant SRAM bit cell |
| CN204102573U (en) * | 2014-10-24 | 2015-01-14 | 安徽大学 | A kind of novel 12 pipe sram cell circuit improving read noise tolerance limit simultaneously and write nargin |
| CN105448327A (en) * | 2015-11-16 | 2016-03-30 | 哈尔滨工业大学 | Memory cells resistant to multi-node rollover |
| CN105336362A (en) * | 2015-12-10 | 2016-02-17 | 中北大学 | Radiation hardened static random access memory |
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