CN116718602A - Failure positioning and failure analysis method - Google Patents
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- 238000004458 analytical method Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 55
- 238000001514 detection method Methods 0.000 claims abstract description 54
- 238000000227 grinding Methods 0.000 claims abstract description 8
- 239000000523 sample Substances 0.000 claims description 90
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- 239000004065 semiconductor Substances 0.000 description 10
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- 238000010894 electron beam technology Methods 0.000 description 3
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- 238000010884 ion-beam technique Methods 0.000 description 3
- 238000003698 laser cutting Methods 0.000 description 3
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- 238000012986 modification Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
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- G—PHYSICS
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N25/00—Investigating or analyzing materials by the use of thermal means
- G01N25/72—Investigating presence of flaws
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention provides a failure positioning and failure analysis method, wherein the failure positioning method comprises the following steps: providing a chip sample with multiple film layers, wherein one film layer of the chip sample is a failure layer with failure positions, and the failure positions form detection hot spots; forming a first laser mark and a second laser mark which vertically penetrate through the chip sample, wherein the first laser mark and the second laser mark are respectively positioned in a first direction and a second direction of a failure position; detecting the position of a detection hot spot on the top layer or the bottom layer of the chip sample, and measuring a first distance and a second distance between the first laser mark and the detection hot spot and the second laser mark respectively; and grinding the chip samples layer by layer to the failure layer, and positioning the position of the detection hot spot on the failure layer according to the first distance and the second distance. According to the method, the first laser mark and the second laser mark are used as reference points to locate the hot spot of the failure layer, so that the problem that the locating accuracy of the hot spot in the failure layer is affected due to the fact that the structural size of the top layer or the bottom layer is different from that of the failure layer is effectively avoided.
Description
Technical Field
The invention relates to the technical field of semiconductor failure analysis, in particular to a failure positioning and failure analysis method.
Background
Failure analysis of integrated circuits is an important means to increase product yield, and in the product development stage, various test structures (testkeys) are usually involved, simulating the real environment in the integrated circuit, and finding defects in design or production processes. When the test structure fails, the failure position needs to be found out, the failure mechanism is found out aiming at the failure position, the failure reason is accurately judged, and a scientific basis is provided for improving the reliability of the product.
The existing semiconductor failure positioning method comprises the steps of adopting positioning tools such as EMMI (light emission microscope), OBIRCH (light induced impedance change microscope), thermal (Thermal emission microscope) and the like, and measuring the distance between the edge of the top layer or the bottom layer of the test structure and the hot spot after acquiring the hot spot at the failure position through a high-magnification lens of the positioning tools as shown in figure 1 so as to acquire the position relation of the hot spot relative to the edge of the top layer or the bottom layer of the test structure; the same positioning mode is still adopted for positioning the hot spot at the failure layer which needs to be detected by the probe, namely, the position of the hot spot at the failure layer is confirmed from the edge of the failure layer according to the position relation of the hot spot relative to the edge of the top layer or the bottom layer.
However, due to the different structures of the layers of the test structure, the positions of the frame of the top layer or the bottom layer and the frame of the failure layer deviate, as shown in fig. 1, due to the difference between the structure sizes of the top layer or the bottom layer 1 'and the failure layer 2' actually required to be detected by the probe, which is observed by the positioning tool, an error exists when the failure layer 2 'positions the hot spot 21' according to the positional relationship between the edge of the top layer or the bottom layer 1 'and the hot spot 21', d1 in fig. 1 is an error in the first direction when the failure layer 2 'positions the hot spot 21', and d2 is an error in the second direction when the failure layer 2 'positions the hot spot 21'.
Disclosure of Invention
The invention aims to provide a failure positioning and failure analysis method for solving the problem of low accuracy of hot spot positioning at a failure layer.
In order to solve the technical problems, the invention provides a failure positioning and failure analysis method, wherein the failure positioning method comprises the following steps: providing a chip sample with multiple film layers, wherein one film layer of the chip sample is a failure layer, the failure layer is provided with a failure position, and the failure position forms a detection hot spot; forming a first laser mark and a second laser mark which vertically penetrate through each film layer of the chip sample on the chip sample, wherein the first laser mark is positioned in a first direction of the failure position, the second laser mark is positioned in a second direction of the failure position, and the first direction and the second direction are vertical; detecting the position of the detection hot spot on the top layer or the bottom layer of the chip sample, and measuring a first distance between the first laser mark and the detection hot spot and a second distance between the second laser mark and the detection hot spot on the top layer or the bottom layer of the chip sample; and grinding the chip sample layer by layer to the failure layer, and positioning the position of the detection hot spot on the failure layer according to the first distance and the second distance.
Preferably, in the failure positioning method, the method for positioning the position of the detection hot spot on the failure layer includes: forming a first straight line along the first direction by taking the position point of the first laser mark as a base point and forming a second straight line along the second direction by taking the position point of the second laser mark as a base point on the failure layer; and taking the intersection point position of the first straight line and the second straight line as the position of the detection hot spot.
Preferably, in the failure positioning method, the method for positioning the position of the detection hot spot on the failure layer includes: forming a first target point on the failure layer by taking a position point where the first laser mark is located as a base point, and forming the first target point along the first direction from the position where the first laser mark is located as the first distance, wherein the first target point is taken as the detection hot spot; or, forming a second target point on the failure layer by taking the position point of the second laser mark as a base point, and taking the second target point as the detection hot spot along the second direction from the position of the second laser mark as the second distance.
Preferably, in the failure positioning method, the first distance is 1 μm to 50 μm, and the second distance is 1 μm to 50 μm.
Preferably, in the failure positioning method, the diameter of the first laser mark is 330 nm-820 nm, and the diameter of the second laser mark is 330 nm-820 nm.
Preferably, in the failure positioning method, the positioning machine includes a laser coordinate device, and the method for forming the first laser mark and the second laser mark on the chip sample includes: emitting a first laser beam in a direction perpendicular to the chip sample to form the first laser mark; and emitting a second laser beam in a direction perpendicular to the chip sample to form the second laser mark.
Preferably, in the failure positioning method, the method of forming the first laser mark and the second laser mark includes: and adjusting the power of the laser source to be 10 mW-100 mW, and bombarding corresponding positions on the chip sample for forming the first laser mark and the second laser mark for 15 min-30 min.
Preferably, in the failure positioning method, the first laser mark and the second laser mark are formed using a laser coordinate apparatus.
Preferably, in the failure positioning method, the position of the detection hot spot is detected by using a light emission microscope positioning machine or a thermal emission microscope positioning machine.
The invention also provides a failure analysis method, which comprises the following steps: providing a chip sample; positioning the failure position of the chip sample at the failure layer by using the failure positioning method; and performing electrical analysis on the failure position by utilizing the nano probe so as to analyze and obtain a failure mechanism.
In summary, the present invention provides a failure positioning and failure analysis method, where the failure positioning method includes: providing a chip sample with multiple film layers, wherein one film layer of the chip sample is a failure layer, the failure layer is provided with a failure position, and the failure position forms a detection hot spot; forming a first laser mark and a second laser mark which vertically penetrate through each film layer of the chip sample on the chip sample, wherein the first laser mark is positioned in a first direction of the failure position, the second laser mark is positioned in a second direction of the failure position, and the first direction and the second direction are vertical; detecting the position of the detection hot spot on the top layer or the bottom layer of the chip sample, and measuring a first distance between the first laser mark and the detection hot spot and a second distance between the second laser mark and the detection hot spot on the top layer or the bottom layer of the chip sample; and grinding the chip sample layer by layer to the failure layer, and positioning the position of the detection hot spot on the failure layer according to the first distance and the second distance. According to the method, the first laser mark and the second laser mark are used as reference points to locate the hot spot of the failure layer, so that the problem that the locating accuracy of the hot spot on the failure layer is affected due to the fact that the top layer or the bottom layer of the chip sample is different from the structural size of the failure layer is effectively avoided.
Drawings
FIG. 1 is a schematic diagram of the prior art in which positioning inaccuracy is caused by positioning a detection hotspot according to a top or bottom layer frame and a failure layer frame;
FIG. 2 is a schematic diagram of locating a probe hotspot with a first laser mark and a second laser mark as fiducial points according to an embodiment of the present invention;
FIG. 3 is a flow chart of a failure positioning method according to an embodiment of the present invention;
wherein, each reference sign is as follows:
a 1/1' -top or bottom layer; a 2/2' -failure layer; 21/21' -probing hotspots; 31-first laser marking; 32-second laser marking; h is a 1 -a first distance; h is a 2 -a second distance.
Detailed Description
The invention provides a failure positioning and analyzing method and a sample preparation method of a transmission electron microscope, which are further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
Referring to fig. 2 to 3, the present embodiment provides a failure positioning method, including:
step S1: providing a chip sample with multiple film layers, wherein one film layer of the chip sample is a failure layer 2, the failure layer 2 is provided with a failure position, and the failure position forms a detection hot spot 21;
step S2: forming a first laser mark 31 and a second laser mark 32 which vertically penetrate through each film layer of the chip sample on the chip sample, wherein the first laser mark 31 is positioned in a first direction of the failure position, the second laser mark 32 is positioned in a second direction of the failure position, and the first direction and the second direction are perpendicular;
step S3: detecting the position of the detection hot spot 21 on the top layer or bottom layer 1 of the chip sample, and measuring a first distance h between the first laser mark 31 and the detection hot spot 21 on the top layer or bottom layer 1 of the chip sample 1 And a second distance h between the second laser mark 32 and the detection hot spot 21 2 The method comprises the steps of carrying out a first treatment on the surface of the The method comprises the steps of,
step S4: grinding the chip sample layer by layer to the failure layer 2, and according to the first distance h 1 The second distance h 2 And positioning the detection hot spot 21 at the position of the failure layer 2.
According to the above method, the first laser mark 31 and the second laser mark 32 are used as reference points for locating the position of the detection hot spot 21, so that the problem that in the prior art, when the top layer or bottom layer 1 and the border of the failure layer 2 are used for locating the position of the detection hot spot 21 on the failure layer 2, the detection hot spot 21 is located inaccurately on the failure layer 2 due to the deviation between the top layer or bottom layer 1 and the structural size of the failure layer 2 can be effectively avoided.
The device used in the prior art for locating and failure analysis of the chip sample may be a Transmission Electron Microscope (TEM), a Scanning Electron Microscope (SEM), a focused ion beam microscope (focus ion BeamMicroscope, FIB) or an optical emission microscope (EMMI). Among them, TEM is an important tool in electron microscopy, and is generally used to detect morphology, size, characteristics, etc. of thin films constituting semiconductor devices, and the respective rates can reach 0.1nm. After a TEM sample is placed in a TEM observation chamber, the main working principle of the TEM is as follows: the high-energy electron beam penetrates the TEM sample to generate phenomena such as scattering, absorption, interference and diffraction, so that contrast is formed on an imaging plane, an image of the TEM sample is formed, and the TEM sample for TEM failure analysis can be a thin slice sample with the thickness of about 100 nanometers after the image is observed, measured and analyzed. SEM is the most commonly used failure analysis device, and its main working principle is that high-energy electrons are incident on the surface of a solid sample, and elastically or inelastically scatter with the nucleus and extranuclear electrons of the sample, so as to excite the sample to generate various physical signals, and an electron detector is used to receive the signals to form an image. The SEM can be used for carrying out fine observation on the section or the surface of the sample, confirming the components of the sample to be tested, and the like. SEM magnification can be from thousands to hundreds of thousands, resolution reaches nm level, and a sample can inspect thousands or even tens of thousands of MOS transistors, thus meeting the requirements of integrated circuit microstructure observation in the present stage or even in the coming decades. FIB is widely used in semiconductor electronic industry and Integrated Circuit (IC) industry, and the working principle of FIB is to effectively control and remove materials by impacting a sample with a heavy metal ion, and the FIB uses a high-energy Ion Beam (IB) to enter a solid sample to strip surface atoms, so as to prepare a sample for TEM observation, elastically or inelastically scatter with atomic nuclei and extranuclear electrons of the sample, excite the sample to generate secondary electrons, and receive the generated secondary electron signals to form images by an Electron Beam (EB) scanner or detector for observation. EMMI is a very useful and highly efficient analytical tool capable of detecting photons emitted inside an Integrated Circuit (IC), and is mainly used for the fixed point analysis of leakage failures, and its main working principle is to use the luminescence phenomenon of semiconductors, and in devices with leakage, breakdown, hot carrier effects, photons are emitted from the failure point, and the failure point can be located by applying a voltage to a sample through a microscope.
Preferably, in this embodiment, the location of the detection hot spot 21 is detected by using a light emission microscope positioning machine or a thermal emission microscope positioning machine.
The chip sample is generally manufactured in the same process as the semiconductor devices in the wafer, and the chip sample and the semiconductor devices have a mutual correspondence. Since the chip sample and the semiconductor device are prepared in the same process and have a corresponding relationship with each other, the performance of the semiconductor device in the wafer can be obtained by detecting the performance of the chip sample.
In step S4, the method for positioning the position of the probe hotspot 21 on the failure layer 2, in some embodiments, a first straight line is formed along a first direction on the failure layer 2 by using the position point of the first laser mark 31 as a base point, and a second straight line is formed along a second direction by using the position point of the second laser mark 32 as a base point; and taking the intersection point position of the first straight line and the second straight line as the position of the detection hot spot 21. The method is used for positioning the detection hot spot on the failure layer 2, and a measuring tool is used, so that only the first laser mark 31 and the first direction and the second laser mark 32 and the second direction are needed to be determined, and the positioning method steps are simplified.
In other embodiments, on the failure layer 2, the first laser mark 31 is located at the first distance h along the first direction with the location point of the first laser mark 31 as the base point 1 Form a first target point as the detection hot spot 21The method comprises the steps of carrying out a first treatment on the surface of the Or, on the failure layer 2, the second laser mark 32 is located at the second distance h along the second direction with the location point of the second laser mark 32 as the base point 2 Form a second target point, which is taken as the detection hotspot 21.
In view of the gradual decrease in the size of the semiconductor device, the actual length and width of the device are often in nanometer units, and the accuracy of the commonly used positioning machines such as EMMI (light emission microscope), OBIRCH (light induced impedance change microscope), thermal (Thermal emission microscope) and the like is in micrometer level, which may cause the suspected range of the probe hotspots 21 to be increased during positioning, thereby increasing the workload of engineers.
To solve the above problem, the first distance h between the first laser mark 31 and the detection hot spot 21 is defined 1 And defining the second distance h between the second laser mark 32 and the detection hot spot 21 2 Is not too large, preferably, the first distance h 1 From 1 μm to 50 μm, the second distance h 2 Is 1-50 μm.
In some specific application scenarios, locating the probing hot spot 21 at the location of the failure layer 2 requires ensuring that the structure of the failure layer 2 is intact, that is, laser marks need to be formed outside the structure of the chip sample. In this embodiment, the first laser mark 31 and the second laser mark 32 are formed inside or outside the structure of the chip sample, and are determined by a worker according to a real environment.
Methods for forming laser marks are various, for example, laser marking by a laser cutter, laser marking by a FIB milling machine, and the like. When the laser marks are made by the two methods, the area of the laser marks is larger, for example, the area of the laser marks made by a laser cutting machine is 400 μm 2 ～2500μm 2 Although the laser marks are easily distinguished by a microscope or a scanning electron microscope, they are also susceptible to delamination around the laser marks due to a high polishing rate when polished in the vicinity of the laser marksAnd (5) grinding continuously. In addition, the laser cutting machine cannot detect the detection hot spot 21, that is, after the laser cutting machine or FIB completes the laser marking, another machine is required to observe the laser marking and obtain the positional relationship between the laser marking and the detection hot spot 21, which affects the positioning accuracy.
In order to avoid the above-mentioned problems, it is preferable that in the present embodiment, the first laser mark 31 and the second laser mark 32 are formed by using the laser coordinate device, and the laser coordinate device belongs to a positioning machine-function device. After the first laser mark 31 and the second laser mark 32 are formed by using the laser coordinate device of the positioning machine, the first laser mark 31 and the second laser mark 32 are observed by using the lens belonging to the positioning machine, and the positional relationship between the first laser mark 31 and the second laser mark 32 and the detection hot spot 21 is obtained, so that the positioning accuracy is improved. In addition, the diameter sizes of the first laser mark 31 and the second laser mark 32 formed by the laser coordinate apparatus are 330nm to 820nm, and the uniformity of subsequent grinding is not affected.
In step S2, the method of forming the first laser mark and the second laser mark preferably emits a first laser beam in a direction perpendicular to the chip sample to form the first laser mark; and emitting a second laser beam in a direction perpendicular to the chip sample to form the second laser mark.
Further, the first laser mark 31 and the second laser mark 32 penetrate vertically through each film layer of the chip sample, so that when the chip sample is polished to the failure layer 2, the first laser mark 31 and the second laser mark 32 are still visible, so as to locate the detection hot spot 21 on the failure layer 2.
In order to make the first laser mark 31 and the second laser mark 32 vertically penetrate through each film layer of the chip sample, parameters of the laser coordinate device are adjusted, preferably, power of the laser source is adjusted to be 10 mW-100 mW, and corresponding positions on the chip sample for forming the first laser mark 31 and the second laser mark 32 are bombarded continuously for 15 min-30 min.
The embodiment of the invention also provides a failure analysis method, which comprises the following steps:
providing a chip sample, and positioning a detection hot spot 21 at a failure position of the chip sample at a failure layer 2 by using the failure positioning method; and performing electrical analysis on the failure position by utilizing the nano probe so as to analyze and obtain a failure mechanism.
In summary, the embodiment of the present invention provides a failure positioning and failure analysis method, where the failure positioning method includes: providing a chip sample with multiple film layers, wherein one film layer of the chip sample is a failure layer, the failure layer is provided with a failure position, and the failure position forms a detection hot spot; forming a first laser mark and a second laser mark which vertically penetrate through each film layer of the chip sample on the chip sample, wherein the first laser mark is positioned in a first direction of the failure position, the second laser mark is positioned in a second direction of the failure position, and the first direction and the second direction are vertical; detecting the position of the detection hot spot on the top layer or the bottom layer of the chip sample, and measuring a first distance between the first laser mark and the detection hot spot and a second distance between the second laser mark and the detection hot spot on the top layer or the bottom layer of the chip sample; and grinding the chip sample layer by layer to the failure layer, and positioning the position of the detection hot spot on the failure layer according to the first distance and the second distance. According to the method, the first laser mark and the second laser mark are used as reference points to locate the hot spot of the failure layer, so that the problem that the locating accuracy of the hot spot in the failure layer is affected due to the fact that the top layer or the bottom layer of the chip sample is different from the failure layer in structural size is effectively avoided.
It should also be appreciated that while the present application has been disclosed in the context of a preferred embodiment, the above embodiment is not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (10)
1. A failure positioning method, comprising:
providing a chip sample with multiple film layers, wherein one film layer of the chip sample is a failure layer, the failure layer is provided with a failure position, and the failure position forms a detection hot spot;
forming a first laser mark and a second laser mark which vertically penetrate through each film layer of the chip sample on the chip sample, wherein the first laser mark is positioned in a first direction of the failure position, the second laser mark is positioned in a second direction of the failure position, and the first direction and the second direction are vertical;
detecting the position of the detection hot spot on the top layer or the bottom layer of the chip sample, and measuring a first distance between the first laser mark and the detection hot spot and a second distance between the second laser mark and the detection hot spot on the top layer or the bottom layer of the chip sample; the method comprises the steps of,
and grinding the chip samples layer by layer to the failure layer, and positioning the position of the detection hot spot on the failure layer according to the first distance and the second distance.
2. The failure localization method of claim 1, wherein the method of locating the probe hotspots at the location of the failure layer comprises:
forming a first straight line along the first direction by taking the position point of the first laser mark as a base point and forming a second straight line along the second direction by taking the position point of the second laser mark as a base point on the failure layer; the method comprises the steps of,
and taking the intersection point position of the first straight line and the second straight line as the position of the detection hot spot.
3. The failure localization method of claim 1, wherein the method of locating the probe hotspots at the location of the failure layer comprises:
forming a first target point on the failure layer by taking a position point where the first laser mark is located as a base point, and forming the first target point along the first direction from the position where the first laser mark is located as the first distance, wherein the first target point is taken as the detection hot spot; or,
and forming a second target point on the failure layer by taking the position point of the second laser mark as a base point and taking the second target point as the detection hot spot along the second direction from the position of the second laser mark as the second distance.
4. The failure localization method of claim 1, wherein the first distance is 1 μm to 50 μm and the second distance is 1 μm to 50 μm.
5. The failure localization method of claim 1, wherein the first laser mark has a diameter of 330nm to 820nm and the second laser mark has a diameter of 330nm to 820nm.
6. The failure localization method of claim 1, wherein the method of forming the first laser mark and the second laser mark on the chip sample comprises:
emitting a first laser beam in a direction perpendicular to the chip sample to form the first laser mark; the method comprises the steps of,
a second laser beam is emitted in a direction perpendicular to the chip sample to form the second laser mark.
7. The failure localization method of claim 6, wherein the method of forming the first laser marking and the second laser marking comprises:
and adjusting the power of the laser source to be 10 mW-100 mW, and bombarding corresponding positions on the chip sample for forming the first laser mark and the second laser mark for 15 min-30 min.
8. The failure localization method of claim 1 or 6, wherein the first laser marking and the second laser marking are formed using a laser coordinate device.
9. The failure localization method of claim 1, wherein the location of the probing hot spot is detected using a light emission microscope localization machine or a thermal emission microscope localization machine.
10. A failure analysis method, comprising:
providing a chip sample;
positioning the failure location of the chip sample using the failure positioning method of any one of claims 1-9; the method comprises the steps of,
and carrying out electrical analysis on the failure position by utilizing the nano probe so as to analyze and obtain a failure mechanism.
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| CN202310780526.5A CN116718602A (en) | 2023-06-28 | 2023-06-28 | Failure positioning and failure analysis method |
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