CN101233609B - Method for manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device fabricating method capable of managing a process having a step of forming a hole in a semiconductor wafer, more strictly and conveniently than the prior art while employing a non-destructive inspection. The semiconductor device fabricating method performs the process management of the semiconductor device, by specifying one of a plurality of holes formed in the semiconductor wafer, as an object hole, and by non-destructively measuring the shape or diameter of the hole top of the object hole, the shape or diameter of the hole bottom of the object hole, and the state or residue of the bottom of the object hole. The process of the semiconductor device is managed on the basis of the shape or diameter of the hole top, the shape or diameter of the hole bottom, and the state or residue of the bottom.

Description

Manufacturing method of semiconductor device

technical field

The invention relates to a method for manufacturing a semiconductor device. Furthermore, the present invention relates to a technique for performing process evaluation in a manufacturing process of a semiconductor device using electron beams, ion beams, light, electromagnetic waves, or the like.

Background technique

Generally, more than tens of millions of holes called contact holes or via holes are formed in a semiconductor device. These holes are usually formed by etching. Since these holes are holes for conducting electricity, it is necessary to confirm whether they have the desired finished shape.

16 is an exemplary partial cross-sectional view of a hole formed on a semiconductor wafer. An oxide film 202 is formed on the surface of a silicon substrate 201 of a semiconductor wafer. The hole is formed to pass through the oxide film 202 , that is, to expose the surface of the silicon substrate 201 . The opening diameter of the hole is the hole top diameter d1. The diameter of the hole bottom is the hole bottom diameter d2. In addition, residue 203 sometimes exists at the bottom of the hole, and the residue 203 is composed of an etching residue of the oxide film 202, a film formed by oxidizing silicon at the bottom of the hole, photoresist residue, or the like.

As a method of non-destructively observing the completion of contact holes, via holes, etc., observation by critical dimension scanning electron microscope (CDSEM, Critical Dimension Scanning Electron Microscopy) is known. CDSEM is a kind of high-performance electron microscope, which can collect and image the secondary electrons (Secondary Electron) generated by scanning the electron beam on the sample (silicon substrate 201), and can measure the length of the hole top diameter d1 and The ability to observe the shape of the opening of the hole.

Observation or length measurement by CDSEM is currently the only management means for hole formation processing in semiconductor processing. In particular, in a mass-produced factory, the pore top diameter d1 is measured by CDSEM after the pore forming process.

On the other hand, a method (EBSCOPE substrate current method) for evaluating the quality of semiconductor device processing (EBSCOPE substrate current method) was invented by the inventor of the present application by irradiating an electron beam to a semiconductor wafer and using the current passing through the semiconductor wafer during the irradiation, that is, the substrate current. For example, refer to Patent Documents 1 to 3).

The EBSCOPE substrate current method is a method in which, for example, an electron beam with a certain energy is irradiated to a semiconductor wafer in an etched state for a few seconds, and the processing state is known by the magnitude or polarity of the substrate current generated at this time. As the electron beam energy, for example, 0 to several Kev is used, and as the current amount, a current amount of picoampere (pA) or nanoampere (nA) is used.

In the EBSCOPE substrate current method, when the processing results of two semiconductor wafers are the same, the same substrate current is generated, and when the processing results are different, different currents are generated, so that it can be judged whether the processed processing is the same as the standard state. Furthermore, in this method, the hole bottom diameter d2 can be directly measured using the waveform of the substrate current generated when the electron beam is scanned on the sample.

Patent Document 1: Japanese Patent No. 3334750

Patent Document 2: Japanese Patent No. 3292159

Patent Document 3: Japanese Patent No. 3175765

However, in the prior art, due to technical constraints, only the control of the pore top diameter d1 by CDSEM was performed, and other quantities required for evaluation of pore formation were not measured. In recent years, as disclosed in the background art, techniques for measuring each part of the hole structure have been conceived. However, there is a problem that whether the machining is optimized after measuring the hole structure as a whole or comprehensively, and a method for knowing this point relatively easily has not yet been widely used.

For this reason, even at present, the hole forming process uses only a measured amount of the hole top diameter d1 for process control, and as a result, insufficient process control has caused defective products to be produced.

In addition, conventionally, there is cross-sectional observation using a scanning electron microscope (SEM, Scanning Electron Microscopy) as a destruction inspection. FIG. 17 is a flowchart showing a process evaluation method of a semiconductor device using SEM. First, in order to evaluate etching characteristics, the same pattern is formed on a plurality of semiconductor wafers by photolithography (step S101 ).

Then, each semiconductor wafer is processed by changing the etching standard (step S102). Next, the photoresist is peeled off as a sample to be measured (step S103). Next, use a focused ion beam (FIB, Focused Ion Beam) or manually break the semiconductor wafer to expose the cross section of the hole (step S104). Then, the cross section of the hole is observed using SEM or transmission electron microscope (TEM, Transmission Electron Microscope) (step S105). Based on the observation result, optimal etching conditions are selected (step S106).

However, semiconductor wafers inspected by SEM or TEM cannot be used as products because they are broken by FIB or by hand. Therefore, in the process evaluation of semiconductor devices using SEM or TEM, it becomes a small number of sampling inspections in each lot. In addition, in processing evaluation using SEM or TEM, since it takes a lot of time to prepare a sample, a very small number of points are measured for each semiconductor wafer. Furthermore, since a part of the precious pore structure may be lost during the preparation of the sample, there is also a problem that it is not possible to observe the portion desired to be observed.

Therefore, in processing evaluation by SEM or TEM, there are problems that the number of analysis samples required to truly optimize processing cannot be fully obtained, nor can it be guaranteed that the sample points measured are representative. The collection method of the sample will damage the sample itself, so the real analysis result cannot be obtained.

For finer processing below 90nm, TEM is necessary because the resolution of SEM is insufficient. However, this method requires more time and effort, and is not practical.

Contents of the invention

The present invention is made to solve the above-mentioned problems in the prior art. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can perform stricter and simpler process management than conventional ones while using non-destructive testing in the process management of a process including forming holes in a semiconductor wafer.

In order to solve the above-mentioned problems, the semiconductor device manufacturing method of the present invention is characterized in that one of the plurality of holes formed on the semiconductor wafer is determined as the hole to be measured, and the shape of the top of the hole to be measured or the shape of the hole top of the hole to be measured is determined. diameter, the shape or diameter of the hole bottom of the hole to be measured, and the bottom state or bottom residue of the hole to be measured are non-destructively measured, and according to the shape or diameter of the hole top, the shape or the bottom of the hole Diameter, and the state of the bottom or the residue at the bottom, for the processing management of semiconductor devices, according to the edge of the hole extracted from the top of the hole and the bottom of the hole, a mathematical approximation curve that conforms to the shape of the hole is generated, and the approximate curve is passed The characteristic quantity is to obtain the diameter, short diameter, long diameter, center position, deformation, roughness, center coordinates of the hole top and center coordinates of the hole bottom or their offset, hole formation angle, and hole depth.

According to the semiconductor device manufacturing method of the present invention, any one of the holes formed in the semiconductor wafer is used as the hole to be measured. Then, the shape of the hole top, the shape of the bottom of the hole, the state of the bottom of the hole, etc. of the hole to be measured are measured, and processing management is performed. Therefore, it is possible to comprehensively evaluate as a whole whether or not a specific measurement target hole is normally formed, and to perform stricter and more accurate processing management than conventionally. That is, in the conventional CDSEM, since only the top shape of a specific hole to be measured is measured, strict processing management cannot be performed. In addition, in the conventional EBSCOPE substrate current method, although the measurement of the pore bottom diameter (diameter of the pore bottom) can be realized, the overall measurement of the pore shape and the like of a specific measurement object has not been performed. In addition, processing management using SEM or TEM requires a lot of time and cost, and there is a problem that the semiconductor wafer to be measured is damaged. According to the present invention, strict and accurate processing management can be performed while avoiding the above-mentioned problems. Therefore, the present invention can manufacture high-performance semiconductor devices at low cost.

Furthermore, in the semiconductor device manufacturing method of the present invention, the measurement of the shape or diameter of the top of the hole includes a process of measuring secondary electrons and reflected electrons generated by irradiating the semiconductor wafer with an electron beam.

According to the semiconductor device manufacturing method of the present invention, in the measurement of the entirety of one pore, the measurement of the shape of the pore top and the like can be performed non-destructively using a CDSEM.

In addition, in the semiconductor device manufacturing method of the present invention, the measurement of the shape or diameter of the hole bottom includes a process of measuring a substrate current, which is a current generated on the semiconductor wafer by irradiating the semiconductor wafer with an electron beam.

According to the semiconductor device manufacturing method of the present invention, in the measurement of the entirety of one hole, the shape of the bottom of the hole and the like can be measured non-destructively using the EBSCOPE substrate current method.

In addition, the semiconductor device manufacturing method of the present invention is characterized in that the measurement of the bottom state or the bottom residue includes a process of measuring a substrate current, which is a current generated on the semiconductor wafer by irradiating the semiconductor wafer with an electron beam.

According to the semiconductor device manufacturing method of the present invention, in the measurement of the entirety of a hole, the state of the bottom of the hole, residues, etc. can be measured non-destructively using the EBSCOPE substrate current method.

In addition, the semiconductor device manufacturing method of the present invention is characterized in that the shape or diameter of the hole top is a predetermined value, the shape or diameter of the hole bottom is a predetermined value, and the bottom state or bottom residue is a predetermined value. state, it is determined that the hole to be measured is normally formed.

According to the semiconductor device manufacturing method of the present invention, when the three factors of the shape of the top of the hole, the shape of the bottom of the hole, and the state of the bottom are all appropriate, it can be judged that the hole to be measured is normally formed. Therefore, it is possible to perform remarkably high-precision machining management compared to the conventional case where machining management is performed by one factor.

In addition, the semiconductor device manufacturing method of the present invention is characterized in that in the non-destructive measurement, the electron beam is irradiated to the semiconductor wafer in such a manner that the electron beam trajectory traverses the hole to be measured, and The secondary electron waveform, the current waveform generated in the semiconductor wafer during the irradiation, that is, the substrate current waveform is detected, the shape or diameter of the hole top is measured using the secondary electron waveform, and the substrate current waveform to measure the shape or diameter of the bottom of the hole, irradiate the hole to be measured with an electron beam thicker than the electron beam that traverses the hole to be measured for a certain period of time, and measure the EBS value, and the EBS value is The value obtained by dividing the substrate current generated during this irradiation by the current incident on the semiconductor wafer through the thick electron beam; and according to the diameter of the hole top, the diameter of the hole bottom and ESB values are used for process management of semiconductor devices.

According to the semiconductor device manufacturing method of the present invention, the shape of the top of the hole can be measured by CDSEM, the shape of the bottom of the hole can be measured with the line scanning mode of the EBSCOPE substrate current method, and the covering (blanket) of the EBSCOPE substrate current method can be used. In this mode, the residue at the bottom of the hole, etc. is measured. Here, the line-scanning mode of the EBSCOPE substrate current method refers to a mode in which electron beams are irradiated to a sample after being narrowly focused like a CDSEM. In addition, the coverage mode of the EBSCOPE substrate current method refers to a mode in which a rough electron beam of a certain energy is irradiated to a sample for a certain period of time.

Furthermore, the semiconductor device manufacturing method of the present invention is characterized in that the secondary electron waveform and the substrate current waveform are waveforms obtained simultaneously by irradiating the semiconductor wafer with the electron beam.

According to the method of manufacturing a semiconductor device of the present invention, the shape, etc. of the top of the hole and the shape, etc. of the bottom of the hole can be measured simultaneously by scanning with one electron beam. Therefore, according to the present invention, strict processing management can be performed relatively quickly and at low cost.

Furthermore, the semiconductor device manufacturing method of the present invention is characterized in that the process management of the semiconductor device is performed based on the arrangement density of holes in the semiconductor wafer and the measurement result.

According to the semiconductor device manufacturing method of the present invention, process management can be performed according to the hole top shape, hole bottom shape, hole bottom state, etc. of the holes to be measured, as well as the arrangement density of the holes. Accordingly, stricter and more accurate processing management can be performed.

Furthermore, the semiconductor device manufacturing method of the present invention is characterized in that the process management of the semiconductor device is performed based on the layout (arrangement pattern or arrangement pattern) of the holes in the semiconductor wafer and the measurement results.

According to the semiconductor device manufacturing method of the present invention, processing management can be performed according to the top shape, bottom shape, and state of the hole bottom of the hole to be measured, as well as the layout of the holes concerned. Accordingly, stricter and more accurate processing management can be performed.

In addition, the semiconductor device manufacturing method of the present invention is characterized in that the measurement of the shape or diameter of the top of the hole includes a process of measuring secondary electrons and reflected electrons generated by irradiating the semiconductor wafer with an electron beam, and the bottom of the hole is The measurement of the shape or diameter of the semiconductor wafer includes the process of measuring the current generated on the semiconductor wafer by irradiating electron beams to the semiconductor wafer. Based on the data obtained by measuring the top and bottom of the hole, the top of the hole is expressed. The image and numerical value of the shape, and the image and numerical value representing the shape of the hole bottom are displayed on the display device.

According to the semiconductor device manufacturing method of the present invention, the hole top shape and the hole bottom shape of a specific hole to be measured can be displayed on the screen. This display can be performed without damaging the semiconductor wafer to be measured, and can be performed quickly and at a significantly lower cost than SEM and TEM. Thus, with the present invention, a high-performance semiconductor device can be manufactured at low cost.

In addition, the semiconductor device manufacturing method of the present invention is characterized in that the shape or diameter of the hole top, the shape or diameter of the hole bottom, and the bottom state or bottom residue are displayed on a display device.

According to the method of manufacturing a semiconductor device of the present invention, the overall and comprehensive structure of a specific measurement target hole can be displayed on the screen. This display can be performed without damaging the semiconductor wafer to be measured, and can be performed quickly and at a significantly lower cost than SEM and TEM. Thus, with the present invention, a high-performance semiconductor device can be manufactured at low cost.

Through the present invention, very strict management of non-destructive hole processing can be carried out. Strict hole processing management directly contributes to the improvement of yield in semiconductor manufacturing. Since any hole desired to be managed can be selected as a measurement target, it is applicable to actual semiconductor devices having all layouts. The present invention can also directly test product devices, and does not need to prepare test wafers.

Instead of electron beams, laser light or the like can also be applied to the present invention. Using laser light in the same manner as electron beams can also obtain the same measurement results as in the case of electron beams. That is, in order to know the hole top diameter, hole bottom diameter, hole bottom residue, etc., measured values of scatterometry (scatterometry) using the laser light diffraction phenomenon can also be used.

In addition, obviously, the present invention can also use electromagnetic waves or ions as probes (instead of electron beams). In addition, it is obvious that the present invention is not limited to the three factors of hole top, hole bottom, and hole bottom residue, and other factors may be measured and included as evaluation objects.

In addition, it is obvious that the present invention can obtain the same effect as above even if the present invention uses nearby holes considered to have received substantially the same processing or their average measurement values in processing management, even if the holes are not exactly the same.

Description of drawings

FIG. 1 is a flow chart showing a method of manufacturing a semiconductor device in a first embodiment of the present invention;

2 is an explanatory diagram showing an outline of a CDSEM used in the semiconductor device manufacturing method according to the first embodiment of the present invention;

3 is an explanatory diagram showing the outline of EBSCOPE used in the semiconductor device manufacturing method according to the first embodiment of the present invention;

FIG. 4 is an example top view of an exposure region configuration for a semiconductor wafer;

Fig. 5 is a plan view showing in detail one exposure area in Fig. 4;

6 is a diagram showing a table of values to be managed in the semiconductor device manufacturing method of the first embodiment;

7 is a diagram showing a set of processing management for performing optimal processing in the semiconductor device manufacturing method according to the first embodiment;

8 is a flowchart showing a method of manufacturing a semiconductor device in a second embodiment of the present invention;

FIG. 9A is an example diagram of measured values obtained in the second embodiment;

FIG. 9B is an example diagram of measured values obtained in the second embodiment;

FIG. 9C is an example diagram of measured values obtained in the second embodiment;

FIG. 10 is an explanatory diagram showing a modified example of the second embodiment;

11 is a schematic diagram of EBSCOPE used in the semiconductor device manufacturing method of the third embodiment of the present invention;

12 is a schematic diagram of a semiconductor device manufacturing method in a fourth embodiment of the present invention;

13A is a schematic diagram of a semiconductor device manufacturing method in a fifth embodiment of the present invention;

13B is a schematic diagram of a semiconductor device manufacturing method in a fifth embodiment of the present invention;

13C is a schematic diagram of a semiconductor device manufacturing method in a fifth embodiment of the present invention;

14 is a schematic diagram of a semiconductor device manufacturing method in a sixth embodiment of the present invention;

15A is a schematic top view of a semiconductor device manufacturing method in a seventh embodiment of the present invention;

15B is a schematic cross-sectional view of a semiconductor device manufacturing method in a seventh embodiment of the present invention;

16 is an exemplary partial cross-sectional view of a hole formed on a semiconductor wafer;

FIG. 17 is a flowchart showing a process evaluation method of a semiconductor wafer using SEM.

Explanation of symbols

11, 21, 71, 81 electron beam source

12, 22, 72 deflection electrodes

13, 23, 73 electron beam

14, 24, 74 Determination of samples

15, 25, 75 XY coordinate stage

16, 26, 76 Secondary electron detector

17, 27, 77 Chambers

18, 28, 78 DC power supply

29, 79 ammeter

40 Semiconductor Chips

41 Exposure Area

41a, 41b, 41c, 41d chips

41ak chip origin

41k Origin of exposure area

42 Exposure interval

82 Secondary electron waveform

85 Substrate current waveform

Detailed ways

The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

(first embodiment)

FIG. 1 is a flowchart showing a method of manufacturing a semiconductor device in the first embodiment of the present invention. In this embodiment mode, a method for achieving the object of the present invention is shown by combining and utilizing existing devices. FIG. 2 is an explanatory diagram showing an outline of a CDSEM used in the present semiconductor device manufacturing method. FIG. 3 is an explanatory diagram showing an outline of EBSCOPE (EBSCOPE substrate current method) used in the present semiconductor device manufacturing method.

First, one of the plurality of holes formed on the semiconductor wafer is selected and determined as the hole A to be measured (step S1).

That is, it is necessary to select the hole A to be measured from the very large number of holes existing on one semiconductor wafer. In order to select the well A to be measured, information for identifying the well A to be measured is required. In order to select specific holes existing on the semiconductor wafer, an XY rectangular coordinate system constructed with a specific point on the semiconductor wafer taken as the origin of coordinates is used. Semiconductor devices are generally designed using a coordinate system using XY rectangular coordinates.

FIG. 4 is a top view of an example of an exposure region configuration for a semiconductor wafer. Semiconductor devices are fabricated using photolithography techniques. That is to say, the layout information of semiconductor devices is all recorded on a mask called equivalent to camera film. By shining (exposing) light on this mask, the layout information on the mask is copied to the semiconductor wafer 40 . The range that can be exposed at one time is called an exposure area (shot) 41, and has a size of about 2 cm×3 cm. Therefore, there are about 20 exposure regions 41 on one 8-inch semiconductor wafer 40 . Each exposure area 41 is aligned in the vertical and horizontal directions, and the position of the exposure area is uniquely determined by specifying the columns and rows in the semiconductor wafer 40 . In addition, there is an exposure area interval 42 between each exposure area 41 .

FIG. 5 is a top view showing one exposure area 41 in FIG. 4 in further detail. As shown in FIG. 5 , one or more regions that ultimately function as one semiconductor device are formed in one exposure region 41 , and these regions are called chips 41 a , 41 b , 41 c and 41 d . The interval between the exposure area 41 and the exposure area 41 , that is, the exposure area interval 42 is arbitrary and not fixed. Therefore, the coordinates specified on the XY coordinate axes extending over the entire semiconductor wafer 40 do not necessarily correspond to one hole. Therefore, in order to designate one hole A to be measured, the origin of the XY coordinate system extending independently into the exposure area 41 on the semiconductor wafer 40 or inside the chips 41a, 41b, 41c, and 41d is designated as a reference.

More specifically, in order to accurately specify a hole, the columns and rows of the exposure area 41 or the chips 41a, 41b, 41c, and 41d are first specified. Then, the electron beam irradiation position is moved using a precision stage at the XY coordinate position indicating the measurement target position obtained with respect to the exposure area origin 41k or the chip origin 41ak.

The hole position on the layout (design position) and the actual hole position are not necessarily the same due to manufacturing errors. Therefore, the well A to be measured is accurately extracted from the wells appearing at the XY coordinate positions using the pattern matching technique. When it is difficult to extract the hole A to be measured by pattern matching only once, the measurement point for the hole A to be measured is extracted by performing pattern matching a necessary number of times.

Then, the hole top diameter of the hole A to be measured selected in step S1 is measured by CDSEM (step S2).

The CDSEM used in this step S2 will be described with reference to FIG. 2 . CDSEM is known as critical dimension SEM, which is a type of scanning electron microscope. The CDSEM includes an electron beam source 11 , a deflection electrode 12 , an XY coordinate stage 15 , a secondary electron detector 16 , a chamber 17 and a DC power supply 18 in structure. In addition, an electron beam source 11 , a deflection electrode 12 , a measurement sample 14 , an XY coordinate stage 15 , and a secondary electron detector 16 are disposed in a chamber 17 forming a vacuum container.

CDSEM is originally a device that uses short-wavelength electron beams 13 instead of conventionally used light in order to complement the resolution capability of optical microscopes, and can obtain image resolution capabilities of several nanometers. The working principle is similar to cathode ray (Braun) tube TV. In a CRT TV, an electron beam with a diameter of about 0.1mm sequentially scans the light-emitting layer on a screen formed on glass, while in a CDSEM, an electron beam is used to scan the object to be observed (measurement sample 14) itself. Here, the measurement sample 14 is, for example, a semiconductor wafer 40 , and is placed on the aforementioned XY coordinate stage 15 .

The electron beam 13 is emitted from the electron beam source 11 . The energy source of the electron beam source 11 is a DC power supply 18 . In addition, the electron beam 13 emitted from the electron beam source 11 passes through the deflection electrode 12 and the like, and is narrowly focused to about several nm. The finer the electron beam 13 is concentrated, the more the image resolution performance can be improved.

The electron beam 13 is irradiated so as to sequentially scan the observation target object (measurement target hole A of the semiconductor wafer 40 ) over the entire surface. This full scan irradiation is performed by moving the XY coordinate stage 15 in the XY direction. Then, the secondary electrons generated on the surface of the sample by the irradiation are detected by the secondary electron detector 16, and the detected signal is converted into an electrical signal waveform and imaged.

An image obtained with such a CDSEM is, for example, an aggregate of pixels composed of 512×512 pixels, and the brightness of each pixel corresponds to the amount of detected secondary electrons. By extracting the edge of the hole A to be measured from this image using the differential method, the Full Width at Half Maximum method, the Laplacian operator method, or the Sobel method, the measurement can be obtained. The hole top diameter (diameter of the surface) of the target hole A.

Then, the bottom diameter (diameter of the bottom of the well) of the well A to be measured selected in step S1 is measured using the line scan mode of EBSCOPE (step S3 ).

The line scan mode of EBSCOPE used in this step S3 will be described with reference to FIG. 3 . As described in Japanese Patent No. 3334750, Japanese Patent No. 3292159, and Japanese Patent No. 3175765 listed in the "Background Technology" column, EBSCOPE is a method that uses an ammeter 29 to irradiate an electron beam 23 on a measurement sample. (semiconductor wafer 40) means for generating substrate current.

That is, EBSCOPE structurally includes an electron beam source 21 , a deflection electrode 22 , an XY coordinate stage 25 , a secondary electron detector 26 , a chamber 27 , a DC power supply 28 and an ammeter 29 . In addition, an electron beam source 21 , a deflection electrode 22 , a measurement sample 24 , an XY coordinate stage 25 , a secondary electron detector 26 , and an ammeter 29 are arranged in a chamber 27 forming a vacuum container.

The electron beam source 21 emits an electron beam 23 using a DC power supply 28 as an energy source. The electron beam 23 emitted from the electron beam source 21 is finely focused by the deflection electrode 22 and the like. This electron beam 23 is irradiated onto a measurement sample (semiconductor wafer 40 ) 24 . The secondary electrons generated on the sample surface by the irradiation are detected by the secondary electron detector 26 , and the current (substrate current) generated in the measurement sample 24 by the irradiation is measured by the ammeter 29 .

Also, like CDSEM, EBSCOPE has a measurement method called a line scan mode in which electron beams 23 are irradiated onto a measurement sample 24 after being finely focused. When the same hole as the hole observed by CDSEM (hole A to be measured) was measured in the line scan mode using EBSCOPE, the relative value of the bottom diameter of the hole was obtained from the measured substrate current waveform. Furthermore, by correcting the length using a standard sample as the measurement sample 24, the relative value of the hole bottom diameter can be converted into an absolute value.

Then, the state of the bottom of the well A of the measurement object selected in step S1 or the residue at the bottom is measured by the coverage mode of EBSCOPE (step S4).

The coverage mode of EBSCOPE used in this step S3 will be described with reference to FIG. 3 . In EBSCOPE, in addition to the line scan mode, there is another measurement mode called an overlay mode in which a measurement sample 24 is irradiated with a rough electron beam 23 of a certain energy for a certain period of time.

This overlay mode can sensitively detect the state of the film at the bottom of the well. The output result of the overlay mode is represented by an average value of the ESB value of the substrate current value passed during the evaluation measurement. That is, the EBS value is a value obtained by dividing the substrate current generated when the measurement sample 24 is irradiated with the relatively thick electron beam 23 for a certain period of time by the current incident on the measurement sample 24 from the coarse electron beam 23 . Using this EBS value, the state of the bottom of the well A to be measured or the bottom residue can be measured. That is, the EBS value when there is an abnormality such as oxidation of the bottom state of the hole A to be measured or residues such as etching residues is different from the ESB value in the normal case without these abnormalities.

Then in steps S2, S3, S4, the hole bottom diameter of the measurement object hole A measured, the hole bottom diameter, the residue at the bottom of the hole and the standard value comparison, judge whether the measurement object hole A is a qualified product (steps S5, S6).

That is to say, judge whether the measured hole top diameter, hole bottom diameter and residue at the bottom of the hole are within the range of design allowable value. Specifically, proceed as follows. First, as shown in the above step S2, the diameter of the hole top is measured using the CDSEM for the measurement target hole A selected for processing management, and the measured value is stored in the storage device. For the sake of accuracy, the measurement using CDSEM was performed by automatic measurement.

The hole top diameter stored in the storage device is compared with the design reference value by the CPU. For example, if the design value is a hole with a diameter of 0.1 μm, the range of 0.1 μm±0.01 μm is taken as the allowable value. When the allowable value is exceeded, a warning signal is issued.

Next, as shown in the above-mentioned step S3, the hole bottom diameter of the hole A to be measured is measured using EBSCOPE, and stored in the storage device. The movement (navigation) to the measurement point is the same as that of CDSEM. Electron beams are irradiated to the hole A to be measured, and the substrate current waveform is measured. Edge extraction processing is performed from the substrate current waveform to measure the pore bottom diameter.

Next, the measured hole bottom diameter was compared with the design reference value. For example, if the hole is designed to have a diameter of 0.05 μm, the range of 0.05 μm±0.005 μm is set as the allowable value. Warn if outside design tolerances.

To sum up, if the holes that pass the two references of the measured values in steps S2 and S3 are selected, the holes whose shapes are manufactured according to the design values can be selected.

Furthermore, in the hole, although there are no design values that give a geometrically defined hole shape, there are important properties (factors) that affect the final electrical characteristics. This is the state of the interface at the bottom of the hole. At the bottom of the hole, there are residues of the nanoscale oxide film, a film formed by the oxidation of the material at the bottom of the hole, or photoresist residues and cleaning residues, which have a decisive impact on the operation of the electronic device.

These various characteristics can be measured in the EBSCOPE coverage mode used in the above-mentioned step S4, and the measured values are expressed in units of the above-mentioned EBS value. The measured value has a property that the measured value is a negative value when an oxide film-like substance is located at the bottom of the hole, and a positive value when a photoresist-like substance is present.

In the EBSCOPE overlay mode, the same well A to be measured as the well measured in the EBSCOPE line scan mode is measured and stored in the storage device. The ESB value is an evaluation quantity unique to the device shown in Fig. 3, and there is no data corresponding to the EBS value in the computer-aided design (CAD, Computer aided design) data currently used for semiconductor device design. Therefore, the reference value of the EBS value should be determined by performing experiments in advance.

For example, when a measured value of 100EBS is selected as a reference value as an index indicating a good hole bottom state, ±10EBS can be set as an allowable range. Comparing the EBS value measured in the above step S4 with the reference value, further select qualified wells.

In the semiconductor device manufacturing method of the present embodiment, in each measurement of the hole top diameter, the hole bottom diameter, and the residue at the bottom of the hole in steps S2, S3, and S4, it can be compared with the standard value one by one, or it can be compared with the standard value in all. After performing the measurements in steps S2, S3, and S4, the three measured values are collectively compared with the standard value. In addition, the order of each of steps S2, S3, and S4 is not limited to the above-mentioned order, and may be mutually changed.

In addition, in the above-mentioned steps S2 and S3, the diameter of the top of the hole and the diameter of the bottom of the hole were measured, but instead of these, the shape of the top of the hole and the shape of the bottom of the hole may be measured. In this case, the reference value in step S5 is a reference value regarding the shape of the top of the hole, the shape of the bottom of the hole, the state of the bottom, and the like.

FIG. 6 is an example diagram of a table sorting out values to be managed in the semiconductor device manufacturing method of the present embodiment. As shown in Figure 6, qualified holes can be managed by three processing indicators: hole top diameter, hole bottom diameter and EBS value.

FIG. 7 is a diagram showing a processing management set for optimal processing in the semiconductor device manufacturing method of the present embodiment. As shown in FIG. 7 , in the present embodiment, the management of the hole top diameter, the management of the hole bottom diameter, and the management of the EBS value (residue) are performed for one hole A to be measured. Therefore, according to this embodiment, it is possible to realize very strict management and manufacture a semiconductor device with remarkably high reliability, compared with the management of only the hole top diameter using CDSEM in the conventional semiconductor device process management.

(second embodiment)

8 is a flowchart showing a method of manufacturing a semiconductor device in the second embodiment of the present invention. FIG. 8 shows an example in which processing is optimized using the processing evaluation method of the first embodiment described above.

First, the same pattern for etching characteristic evaluation is formed on a plurality of identical semiconductor wafers by photolithography (step S11 ).

In the pattern formed in step S11, several different hole patterns are formed with arrangement density, size, and the like as parameters.

Then, each semiconductor wafer is processed by changing the etching standard (step S12).

Next, in order to perform a strict measurement, the photoresist is uniformly peeled off for each semiconductor wafer, and it is set as a measurement object sample (step S13).

Next, as shown in the first embodiment, the well A to be measured is selected from the plurality of wells formed in the sample to be measured and measured (step S14 ).

The measurement is, for example, measurement of pore top diameter, pore bottom diameter and EBS value. Therefore, for example, use CDSEM to measure the top diameter of the pore, and use EBSCOPE to measure the pore bottom diameter and EBS value. In addition, SCI and SEM can also be used for measurement.

Optimizing the process is performed with the aim of uniformly forming holes that meet the design values in the entire semiconductor wafer. Therefore, the points to be measured in step S14 are a plurality of points to the extent that the in-plane distribution of the semiconductor wafer can be measured.

9A, 9B, and 9C are diagrams showing examples of measurement values acquired in step S14. In addition, FIG. 9A shows measured values in shades of colors on the plane of the semiconductor wafer 40 . Fig. 9B graphically shows the measured values of the pore top diameter. FIG. 9C graphically shows the measured values of the hole bottom diameter.

Among the etching standards provided in the experiment, the processing with the hole top diameter and hole bottom diameter closest to the design value, and the in-plane distribution of the hole top diameter, hole bottom diameter and EBS value is the smallest is selected as the best processing.

In optimal processing, there is another dimension called robustness. Semiconductor processing performs the same processing on many semiconductor wafers, performing mass production of semiconductor devices. However, semiconductor manufacturing equipment fluctuates in performance due to daily operation. In this case, too, it is desirable to form pores with desired characteristics. In order to select such processing conditions, it is possible to investigate the variation characteristics of the processing results that occur when the processing conditions are changed. As a method for investigating this characteristic, the Taguchi method is generally known, and its evaluation index can use the hole top diameter, hole bottom diameter, and EBS value. By using the method described above, the most stable processing can be selected (step S15).

Since the EBSCOPE shown in FIG. 3 has the secondary electron detector 26, the pore top diameter can be measured using only the EBSCOPE. Therefore, even without using the CDSEM of the manufacturing method shown in FIG. 1 , it is possible to measure the pore top diameter, pore bottom diameter, pore residue, and the like using only EBSCOPE. In this case, hole management is performed as follows.

Although the order can be changed, first, the hole B to be measured selected for the hole formation process management is scanned with the electron beam, and the hole top diameter is measured using the secondary electrons generated at this time, and stored in the storage device. Then, the line scan mode of EBSCOPE is applied to the hole B to be measured as described above, and the bottom diameter of the hole is measured and stored in the storage device. Then, the coverage mode of EBSCOPE is applied to the well B to be measured as described above, and the EBS value representing the information on the bottom of the well is obtained and stored in the storage device. The stored three values are sequentially compared with the reference values corresponding to the respective values, and the completion result of the hole is evaluated from the comparison result.

FIG. 10 is an explanatory diagram showing a modified example of the present embodiment. That is, FIG. 10 shows a state in which the measurement results of the above-mentioned step S14 are displayed on the display device as images or numerical values. The screen 50 shows the shape of the top of the hole measured by the SEM, and the like. Furthermore, on the screen 50 , an image 51 showing the shape of the hole top and numerical data 52 related to the shape of the hole top are displayed. In addition, scales Mx2 and My2 for hole top measurement for visually confirming the absolute value of the image 51 are also displayed. In addition, the screen 50 can also be considered as displaying the data measured by EBSCOPE shown in FIG. 3 .

The screen 60 shows the shape of the bottom of the hole measured by the line scan mode of EBSCOPE and the like. Furthermore, an image 61 showing the shape of the hole bottom and numerical data 62 related to the shape of the hole bottom are displayed on the screen 60 . Moreover, the scales Mx1 and My1 for hole bottom measurement for visually confirming the absolute value of the image 61 are also displayed.

The screen 50 and the screen 60 may be simultaneously displayed on one display screen, or may be displayed separately. In addition, in addition to the screens 50 and 60 , images showing the state of the hole bottom, numerical values, and the like may be displayed on the display device.

According to this modification, the overall and comprehensive structure of a specific hole to be measured can be displayed on the screen, and this display can be performed quickly and at a remarkably low cost without damaging the semiconductor wafer to be measured.

(third embodiment)

11 is a schematic diagram of EBSCOPE used in the semiconductor device manufacturing method according to the third embodiment of the present invention. The EBSCOPE of this embodiment is the same as the EBSCOPE of FIG. 3 in terms of basic structure. Furthermore, the EBSCOPE of this embodiment includes an electron beam source 71 , deflection electrodes 72 , XY coordinate stage 75 , secondary electron detector 76 , chamber 77 , DC power supply 78 and ammeter 79 structurally. In addition, an electron beam source 71 , a deflection electrode 72 , a measurement sample 74 , an XY coordinate stage 75 , a secondary electron detector 76 , and an ammeter 79 are arranged in a chamber 77 forming a vacuum container.

EBSCOPE can simultaneously measure secondary electrons and substrate current while scanning the electron beam 73 by adjusting the internal parameters of the device such as irradiation current, irradiation speed and irradiation energy. Therefore, for example, the hole top diameter and hole bottom diameter of the measurement target hole C selected for hole etching process management can be measured simultaneously.

In this way, the measured values of the hole top diameter and the hole bottom diameter can be obtained for the exact same hole C to be measured, and furthermore, the same position inside the hole C to be measured. Accordingly, the measured values of the hole top diameter and the hole bottom diameter are more effective as evaluation data, and more accurate hole completion results can be evaluated.

(fourth embodiment)

12 is a schematic diagram of a method of manufacturing a semiconductor device in a fourth embodiment of the present invention. In the present embodiment, a Si substrate 84 which is a semiconductor wafer is used as a measurement sample. Furthermore, an oxide film 83 is formed on the surface of the Si substrate 84, and holes penetrating the oxide film 83 are formed at the same time. The electron beam 81 is scanned (row-scanned) to traverse the aperture. Then, EBSCOPE was used to measure the diameter d1 of the top of the hole, the diameter of the bottom of the hole d2 and the state of the bottom of the hole.

In EBSCOPE, the wave height h1 of the substrate current waveform 85 measured during line scan measurement can be measured. This wave height h1 may contain information indicating the state of the hole bottom similar to the information obtained using the overlay mode. Therefore, in order to increase the measurement speed, etc., during a line scan measurement, the hole top diameter d1 is measured according to the secondary electron waveform 82, the hole bottom diameter d2 is measured according to the substrate current waveform 85, and the hole bottom diameter d2 is measured according to the wave height h1 of the substrate current waveform. Bottom state of the hole. These three measurements are performed simultaneously, and their measured values are stored in a storage device. Holes are managed by comparing this stored value with a previously determined reference value.

(fifth embodiment)

13A, 13B, and 13C are schematic views of a semiconductor device manufacturing method in a fifth embodiment of the present invention. That is, FIGS. 13A , 13B, and 13C show examples of cross-sectional shapes of holes in semiconductor devices.

The cross-sectional shape of a hole in a recent semiconductor device is not only a circle, but also an ellipse as shown in FIG. 13A or other shapes. In order to accurately evaluate these pore diameters, it is necessary to perform shape approximation processing corresponding to each pore, and to extract feature quantities.

The usual CDSEM scans a specific point with a linear electron beam to measure the length, while the line scan mode of EBSCOPE performs multiple electron beam scans covering the entire hole and extracts the edge of the hole. From the extracted edge of the hole, a mathematical approximate curve conforming to the shape of the hole is generated, and the diameter, short diameter, long diameter, center position, deformation amount, roughness (refer to FIG. 13B ), and hole The center coordinates of the top and the center coordinates of the bottom of the hole or their offset (refer to FIG. 13C ), the angle of the hole formation, the depth of the hole, etc. These indicators also have a certain benchmark value, and there is a strict tolerance. Therefore, the target values are determined and managed after tabulating the measurement quantities necessary for these process managements.

(sixth embodiment)

14 is a schematic diagram of a method of manufacturing a semiconductor device in a sixth embodiment of the present invention. That is, FIG. 14 shows a top view of one chip 90 in a semiconductor wafer. A plurality of holes H1 , H2 are formed in the chip 90 .

The index of processing evaluation is rarely determined by the characteristics of a hole, and the aggregate characteristics of several holes are of great significance. For example, hole completion results are known to vary according to a loading effect known as the Micro Loading Effect. Therefore, depending on the density of the formed holes, different processing results are generally obtained even with the same processing.

For example, when it is known that the more isolated the hole (H1) is, the smaller the result is, the standard of the hole completion result and the thickness of the hole can be linked together and expressed as a function of the hole thickness. In this way, it is possible to distinguish and manage the portion where small pores are likely to be formed on average and the portion where large pores are likely to be formed, or to use different evaluation criteria for pores with different pore formation densities. Therefore, more detailed processing management can be performed. For example, index 1 is used for the hole H1 having a small hole density, and index 2 is used for the hole H2 having a large hole density.

(seventh embodiment)

15A and 15B are schematic views of a semiconductor device manufacturing method in a seventh embodiment of the present invention. That is, FIGS. 15A and 15B show one wafer 100 among the semiconductor wafers. Also, FIG. 15A shows a top view, and FIG. 15B shows a cross-sectional view at position X1-X2.

Grooves 101 are formed on the surface of the chip 100 . Further, in the formation region of the groove 101 , a plurality of holes H are formed at equal intervals along the groove 101 . In addition, a plurality of holes H are also formed outside the formation area of the groove 101 . The arrangement of the holes H outside the groove 101 formation region (layout R2 ) is different from the arrangement of the holes H on the groove 101 formation region (layout R1 ).

The hole H is formed on the entire surface of the semiconductor wafer by an etching process. Therefore, in order to judge whether the holes H are formed as designed, it is necessary to know the nature of the holes H formed on the entire semiconductor wafer. Etching is known to be performed by forming a plasma, but generally produces distribution within the wafer plane. There are various shapes, either concentric circles or unidirectional inclinations.

Therefore, for example, about 100 points are taken out from the entire surface of the semiconductor wafer, and the hole top diameter, hole bottom diameter, hole bottom residue, etc. of the hole H are measured. In general, due to a loading effect called a microloading effect, even for holes of the same diameter, the completion of the hole H varies depending on the surrounding layout. Therefore, the hole H located at the same position in the layout is selected as a measurement point to evaluate the variation. The deviation can be evaluated within an amount using a standard deviation such as 3σ (sigma).

For example, the evaluation of the completion of an etching process is based on the average value of the hole top diameter, the average value of the hole bottom diameter, the average value of the hole residue (EBS value), the 3σ value of the in-plane deviation of the hole top diameter, and the value of the hole bottom diameter. The 3σ value of the in-plane deviation and the 3σ value of the in-plane deviation of hole residue (EBS value) are evaluated.

A single semiconductor device includes multiple layouts, and it is considered that the standard value is different for each layout. At this time, the management standards are managed separately by layout. For example, for the hole H of the layout R1, set the allowable value of the following values: the average value of the hole top diameter, the average value of the hole bottom diameter, the average value of the hole residue (EBS value), and the 3σ value of the in-plane deviation of the hole top diameter , the 3σ value of the in-plane deviation of the hole bottom diameter, and the 3σ value of the in-plane deviation of the hole residue (EBS value).

For the hole H of the layout R2, set the allowable value of the following values: the average value of the hole top diameter, the average value of the hole bottom diameter, the average value of the hole residue (EBS value), the 3σ value of the in-plane deviation of the hole top diameter, the hole The 3σ value of the in-plane deviation of the bottom diameter and the 3σ value of the in-plane deviation of the hole residue (EBS value). In this way, according to the present embodiment, it is possible to set the standard value or index of the machining completion result individually and in detail.

The embodiments of the present invention have been described above, but the semiconductor device manufacturing method of the present invention is not limited to the above embodiments, and of course various modifications can be added without departing from the gist of the present invention.

The present invention measures the current and secondary electrons of a sample passing through a semiconductor wafer or the like by irradiation with electron beams, so that holes formed in the semiconductor wafer can be precisely measured, and the manufacturing process of semiconductor devices can be strictly controlled. Therefore, the present invention is applicable not only to various semiconductor device manufacturing methods but also to various semiconductor device manufacturing apparatuses.

Claims (11)

1. the manufacture method of a semiconductor device is characterized in that,

To on semiconductor wafer, be defined as the determination object hole in a hole in formed a plurality of holes,

The shape at the bottom of the hole in the shape on top, the hole in described determination object hole or diameter, this determination object hole or the bottom state or the bottom residues thing in diameter and this determination object hole are carried out nondestructively measuring,

According to shape or diameter and described bottom state or the bottom residues thing at the bottom of the shape on top, described hole or diameter, the described hole, carry out the management processing of semiconductor device,

According to the bore edges that at the bottom of top, described hole and described hole, extracts, generation meets the mathematical curve of approximation of hole shape, by this curve of approximation characteristic quantity, obtain at the bottom of the centre coordinate on diameter, minor axis, major diameter, center, deflection, roughness, top, described hole and the described hole centre coordinate or its side-play amount, angled, the hole depth of hole shape.

2. the manufacture method of semiconductor device according to claim 1 is characterized in that, the shape on top, described hole or the mensuration of diameter comprise the secondary electron that mensuration produces described semiconductor wafer irradiating electron beam and the processing of reflection electronic.

3. the manufacture method of semiconductor device according to claim 1 is characterized in that, the shape at the bottom of the described hole or the mensuration of diameter comprise that mensuration is to described semiconductor wafer irradiating electron beam and the electric current that produces at this semiconductor wafer is the processing of substrate current.

4. the manufacture method of semiconductor device according to claim 1, it is characterized in that the mensuration of described bottom state or bottom residues thing comprises that mensuration is to described semiconductor wafer irradiating electron beam and the electric current that produces at this semiconductor wafer is the processing of substrate current.

5. the manufacture method of semiconductor device according to claim 1, it is characterized in that, shape at the bottom of the shape on top, described hole or diameter are setting, described hole or diameter are setting and then described bottom state or bottom residues thing when being specified states, are judged as described determination object hole and normally form.

6. the manufacture method of semiconductor device according to claim 1 is characterized in that,

About described nondestructively measuring, cross the mode in described determination object hole according to electron beam trace, to described semiconductor wafer irradiating electron beam; The current waveform substrate current waveform that produces at described semiconductor wafer when the secondary electron waveform that produces during to described irradiation, described irradiation detects; Utilize described secondary electron waveform to measure the shape or the diameter on top, described hole; Utilize shape or diameter at the bottom of described substrate current waveform is measured described hole; To described determination object hole irradiation certain hour, than the thick electron beam of electron beam that crosses described determination object hole, and measure EBS value, the described substrate current of described EBS value generation when carrying out this irradiation is divided by the value that arrives the electric current gained of described semiconductor wafer by described thick electron beam incident;

About the management processing of semiconductor device, carry out according to the diameter on top, described hole, diameter and the EBS value at the bottom of the described hole.

7. the manufacture method of semiconductor device according to claim 6 is characterized in that, described secondary electron waveform and substrate current waveform are by described semiconductor wafer is shone described electron beam and simultaneously-acquired waveform.

8. the manufacture method of semiconductor device according to claim 1 is characterized in that, the management processing of described semiconductor device carries out according to the configuration density of described semiconductor wafer mesopore and the result of described mensuration.

9. the manufacture method of semiconductor device according to claim 1, it is characterized in that, the management processing of described semiconductor device is according to carrying out about the layout in hole and the result of described mensuration in the described semiconductor wafer, and described layout is arrangement form pattern or configuration pattern.

10. the manufacture method of semiconductor device according to claim 1 is characterized in that,

The shape on top, described hole or the mensuration of diameter comprise the secondary electron that mensuration produces described semiconductor wafer irradiating electron beam and the processing of reflection electronic,

The shape at the bottom of the described hole or the mensuration of diameter comprise the processing of the electric current that mensuration produces to described semiconductor wafer irradiating electron beam and at this semiconductor wafer,

According to the data that the mensuration at the bottom of described Kong Ding and the hole is obtained, make the image and the numerical value of expression top, described hole shape and represent that the image and the numerical value of described hole Bottom Shape are presented on the display unit.

11. the manufacture method of semiconductor device according to claim 1 is characterized in that, shape at the bottom of the shape on top, described hole or diameter, the described hole or diameter and described bottom state or bottom residues thing are presented on the display unit.

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