CN116705640A

CN116705640A - Test method

Info

Publication number: CN116705640A
Application number: CN202310841468.2A
Authority: CN
Inventors: 李作胜; 熊海峰
Original assignee: Shanghai Taisi Microelectronics Co ltd
Current assignee: Shanghai Taisi Microelectronics Co ltd
Priority date: 2023-07-11
Filing date: 2023-07-11
Publication date: 2023-09-05

Abstract

The embodiment of the application provides a testing method, and relates to the field of package testing. The method comprises the following steps: and performing first cutting on the wafer at the cutting channel, wherein the wafer comprises a plurality of chips which are not separated, and the first cutting separates the circuit layers of the chips which are not separated. And performing probe test on the chips separated by the circuit layer, and performing secondary cutting on the chips subjected to the probe test at the cutting channels so as to separate the wafer into a plurality of independent chips. In this embodiment, the first dicing of the wafer can make the plurality of chips incompletely separated, and the probe test is performed on the plurality of chips incompletely separated, and then the second dicing is performed on the plurality of chips subjected to the probe test, so as to separate the plurality of chips into a plurality of independent chips. Therefore, through the first cutting, after the electrical performance test of the chip is completed under the condition of incomplete separation, the second cutting is performed, so that the chip is completely separated, and the probability of missed detection of the bad chip can be reduced.

Description

Test method

Technical Field

The embodiment of the application relates to the field of package testing, in particular to a testing method.

Background

The wafer test is to perform needle test on each chip on the wafer, to mount a probe (probe) which is made of copper plating and gold plating into fine hair, to contact with a solder ball or a bonding pad on the chip to test the electrical characteristics of the probe, to generate a corresponding test pattern according to the test result after the test is completed, and to select qualified chips according to the generated test pattern after the wafer is cut into independent chips by taking the chips as units, and to leave unqualified chips on the blue film.

In the prior art, the electrical characteristics of the wafer level package are tested after the quality control inspection of the finished product, and after the wafer test is completed, the wafer needs to be subjected to processes such as lapping, back-gluing and printing, and the like, and the processes can lead to new bad chips. Since the chips are cut into independent chips, the bad chips generated in the processes cannot be detected through appearance, so that the bad chips of the wafer-level packaging product are lost to the end customer.

Therefore, a test method is needed to solve the problem of missing bad chips.

Disclosure of Invention

In view of the above problems, the embodiments of the present application provide a testing method, which overcomes or at least partially solves the problem that the bad chip is missed.

The embodiment of the application provides a testing method, which comprises the following steps: and performing first cutting on the wafer at the cutting channel, wherein the wafer comprises a plurality of chips which are not separated, and the first cutting separates the circuit layers of the chips which are not separated. And performing probe test on the chips separated by the circuit layer, and performing secondary cutting on the chips subjected to the probe test at the cutting channels so as to separate the wafer into a plurality of independent chips.

In this embodiment, the first dicing of the wafer can make the plurality of chips incompletely separated, and the probe test is performed on the plurality of chips incompletely separated, and then the second dicing is performed on the plurality of chips subjected to the probe test, so as to separate the plurality of chips into a plurality of independent chips. Therefore, through the first cutting, after the electrical performance test of the chip is completed under the condition of incomplete separation, the second cutting is performed, so that the chip is completely separated, and the probability of missed detection of the bad chip can be reduced.

In an alternative, the first cut has a cutting depth in the range of 30 microns to 50 microns.

In this embodiment, by setting the range of the cutting depth of the first cut to between 30 micrometers and 50 micrometers, it is possible to ensure complete separation of the circuit layers of the plurality of chips. Therefore, damage to the circuit layers of the plurality of chips which are not separated due to the shallower cutting depth of the first cutting can be avoided.

In an alternative way, the probe test is performed on a plurality of chips separated by a circuit layer, including: and parallel testing is carried out on the plurality of chips separated by the circuit layer through the probe station.

In this embodiment, since the wafer is not divided into individual chips after the first dicing, the pitch between adjacent chips is hardly changed, and thus, a plurality of chips separated by the circuit layer can be tested in parallel by using the probe stage, thereby improving the test efficiency.

In an alternative, the first cut has a greater cut width than the second cut.

In this embodiment, the cutting width of the first cut is greater than the cutting width of the second cut, so that the cutting edge of the first cut is not contacted during the second cut, and the cutting range of the second cut is not beyond the range of the cutting track, so as to avoid damaging the chip during the second cut.

In an alternative, the difference between the cut width of the first cut and the cut width of the second cut is greater than 20 microns.

In an alternative way, before the dicing street makes the first dicing of the wafer, the method further comprises: and forming a first insulating protective layer on the surface of the wafer, and arranging a first windowing area in a part area of the first insulating protective layer. And forming a redistribution layer on the first insulating protection layer by physical sputtering and electroplating, wherein the part of the redistribution layer located in the first windowing region is contacted with the welding pad. And forming a second insulating protective layer on the surface of the redistribution layer, and arranging a second windowing region in a part of the second insulating protective layer. And forming an under bump metal layer on the second insulating protection layer by physical sputtering and electroplating, wherein the part of the under bump metal layer, which is positioned in the second windowing region, is contacted with the redistribution layer. And (5) sequentially performing ball planting, finished product quality control inspection FQC, grinding, gum backing and printing on the under-bump metal layer.

In this embodiment, the steps of lapping, back-bonding, printing, etc. may be advanced before the step of probe testing, so that the probability of missing a defective chip may be further reduced.

In an alternative, the wafer has a thickness after lapping of greater than 300 microns.

In this embodiment, the thickness of the wafer after lapping is greater than 300 μm, so that the thickness of the wafer after the first dicing is sufficient for the second dicing.

In an alternative manner, after performing the probe test on the plurality of chips separated by the circuit layer, the method further includes: and generating a test map corresponding to each chip. After the dicing street makes a second dicing of the plurality of chips that completed the probe test, the method further comprises: and selecting a target chip meeting preset conditions from the plurality of chips according to the test pattern.

In this embodiment, after the probe test, a test pattern corresponding to each chip may be generated, and after the dicing lane performs the second dicing on the plurality of chips that have completed the probe test, a target chip that meets the preset condition may be selected from the plurality of chips according to the test pattern. In this way, the likelihood that the target chip is a defective chip will be greatly reduced.

In an alternative, the first cut is by laser cutting or mechanical cutting.

The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and may be implemented according to the content of the specification, so that the technical means of the embodiments of the present application can be more clearly understood, and the following specific embodiments of the present application are given for clarity and understanding.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart diagram of a test method provided in the prior art.

Fig. 2 is a flow chart illustrating a testing method according to some embodiments of the present application.

Fig. 3 is a schematic structural diagram of a wafer after first dicing according to some embodiments of the present application.

Fig. 4 is a schematic structural diagram of a wafer after a second dicing according to some embodiments of the present application.

FIG. 5 is a flow chart diagram of another testing method provided by some embodiments of the present application.

FIG. 6 is a flow chart diagram of yet another testing method provided by some embodiments of the present application.

Reference numerals illustrate:

1. a chip; 2. cutting the channel; 3. solder balls; 4. an under bump metal layer; 5. a redistribution layer; 6. a first insulating protective layer; 7. a passivation layer; 8. a circuit layer; 9. monocrystalline silicon; 10. a bonding pad; 11. and a second insulating protective layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

The terms "comprising" and "having" and any variations thereof in the description and claims of the application and in the description of the drawings are intended to cover and not exclude other matters. The word "a" or "an" does not exclude the presence of a plurality.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Furthermore, the terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order, and may be used to improve one or more of these features either explicitly or implicitly.

In the description of the present application, unless otherwise indicated, the meaning of "plurality" means two or more (including two), and similarly, "plural sets" means two or more (including two).

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, e.g., as a "connected" or "coupled" of a mechanical structure may refer to a physical connection, e.g., as a fixed connection, e.g., via a fastener, such as a screw, bolt, or other fastener; the physical connection may also be a detachable connection, such as a snap-fit or snap-fit connection; the physical connection may also be an integral connection, such as a welded, glued or integrally formed connection. "connected" or "connected" of circuit structures may refer to physical connection, electrical connection or signal connection, for example, direct connection, i.e. physical connection, or indirect connection through at least one element in the middle, so long as circuit communication is achieved, or internal communication between two elements; signal connection may refer to signal connection through a medium such as radio waves, in addition to signal connection through a circuit. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

In the prior art, as shown in fig. 1, 101 to step 105 are included in the packaging process of the wafer.

Step 101, forming a first insulating protection layer on the surface of the wafer, and setting a first window opening area in a partial area of the first insulating protection layer.

And 102, forming a redistribution layer on the first insulating protection layer by means of physical sputtering and electroplating, wherein the part of the redistribution layer located in the first windowing region is in contact with the welding pad.

And 103, forming a second insulating protection layer on the surface of the redistribution layer, and setting a second windowing area in a part area of the second insulating protection layer.

And 104, forming an under bump metal layer on the second insulating protection layer by means of physical sputtering and electroplating, wherein the part of the under bump metal layer located in the second windowing region is in contact with the redistribution layer.

And 105, after ball placement and FQC are sequentially performed on the under-bump metal layer, performing electrical test on the wafer, and then performing grinding, back-bonding, printing and cutting procedures.

After that, the plurality of chips obtained after dicing may be individually packaged for use.

The inventors have found that in the prior art, after the wafer has undergone the processes of lapping, back-bonding, printing and dicing, new bad chips may still be generated. Since the wafer has been divided into a plurality of individual chips, the spacing between adjacent chips changes, whereas in the multi-station probe card of the probe station, the spacing between adjacent stations is fixed and no longer coincides with the spacing between adjacent chips. Therefore, after the wafer is divided into a plurality of individual chips, the probe station cannot perform electrical test again on the chip to be put into use, so that the newly generated defective chip is missed.

Based on the above, the embodiment of the application provides a testing method for reducing the possibility of missed detection of bad chips.

Fig. 2 is a flow chart illustrating a testing method according to some embodiments of the present application. The method shown in fig. 2 is applied to the packaging process of the wafer shown in fig. 3 and 4, and the testing method specifically includes the following steps:

in step 201, the wafer is diced for the first time at dicing streets, so that the circuit layers of the plurality of chips which are not separated are separated.

Fig. 3 is a schematic structural diagram of a wafer after first dicing according to some embodiments of the present application. Referring to fig. 3, the wafer includes a plurality of unseparated chips 1 in a direction perpendicular to a gravitational direction, and a scribe line 2 is included between two adjacent chips 1. Each chip 1 comprises, from top to bottom in the direction of gravity, a solder ball 3, an under bump metal layer 4, a second insulating protective layer 11, a redistribution layer 5, a first insulating protective layer 6, a passivation layer 7, a circuit layer 8, and monocrystalline silicon 9.

The bonding pad 10 is further included between the adjacent passivation layers 7, and the solder balls 3, the under bump metal layer 4, the redistribution layer 5, the first insulating protection layer 6, the passivation layer 7, the circuit layer 8, the monocrystalline silicon 9, the bonding pad 10, and the second insulating protection layer 11 may be multiple. Dicing streets 2 are dicing areas for separating each two adjacent chips 1. The solder balls 3, the under bump metal layer 4, the redistribution layer 5, the first insulating protection layer 6, the passivation layer 7, the circuit layer 8, the monocrystalline silicon 9, the bonding pads 10 and the second insulating protection layer 11 are related structures of a wafer well known to those skilled in the art, and the embodiments of the present application will not be repeated.

As can be seen from fig. 3, the wafer comprises a plurality of chips 1 which are not separated. The wafer provided by the embodiment of the application can separate the circuit layers 8 of the plurality of chips 1 which are not separated after the wafer is subjected to the first cutting in the cutting channel 2, so that the plurality of chips 1 can be conveniently subjected to the probe test.

The first cut may be by way of example, laser cutting or mechanical cutting.

In practice, the first cut may have a cut depth in the range of 30 microns to 50 microns.

In the present embodiment, by setting the range of the cutting depth of the first cut to between 30 micrometers and 50 micrometers, it is possible to ensure complete separation of the circuit layers 8 of the plurality of chips 1. Thus, damage to the circuit layers 8 of the plurality of chips 1 which are not separated due to the shallower dicing depth of the first dicing can be avoided.

Step 202, performing probe test on the plurality of chips separated by the circuit layer.

In some embodiments, probing the plurality of chips 1 separated by the circuit layer 8 includes: the plurality of chips 1 separated by the circuit layer 8 are tested in parallel by the probe station.

Specifically, a special probe station capable of supporting the supporting iron ring can be used for probe test, and the probes of the probe station can be contacted with the solder balls 3 to realize the probe test. One probe corresponds to one solder ball 3 so that the probe station can perform parallel testing on a plurality of chips 1 separated by the circuit layer 8.

In this embodiment, since the wafer is not divided into individual chips 1 after the first dicing, the pitch between adjacent chips 1 is hardly changed, and thus, parallel testing can be performed on the plurality of chips 1 separated by the circuit layer 8 by using the probe stage, thereby improving the testing efficiency.

After the first dicing, a probe test is performed to detect whether the electrical properties of the chip 1 still meet the preset conditions after the first dicing. The electrical properties include threshold voltage, saturation current, leakage current, and the like. The chip 1 having the electrical properties such as the threshold voltage, the saturation current, and the leakage current in the normal range may be considered to meet the preset conditions.

In step 203, a second dicing is performed on the plurality of chips that have completed the probe test at the dicing streets.

Fig. 4 is a schematic structural diagram of a wafer after being subjected to a second dicing according to some embodiments of the present application.

For example, the second dicing may be mechanical dicing, and referring to fig. 4, the wafer may be separated into a plurality of independent chips 1 through the second dicing for use.

In this embodiment, the first dicing of the wafer can make the plurality of chips 1 incompletely separated, perform the probe test on the plurality of chips 1 incompletely separated, and then perform the second dicing on the plurality of chips 1 subjected to the probe test to separate the plurality of independent chips 1. Thus, through the first cutting, after the chip 1 completes the electrical performance test under the condition of incomplete separation, the second cutting is performed, so that the chip 1 is completely separated, and the probability of missed detection of bad chips can be reduced.

In some embodiments, the first cut has a greater cut width than the second cut.

For example, the difference between the cut width of the first cut and the cut width of the second cut may be greater than 20 microns. That is, the cutting width of the first cut may be 20 microns or more wider than the cutting width of the second cut.

In this embodiment, the cutting width of the first cut is greater than the cutting width of the second cut, so that the cutting edge of the first cut is not contacted during the second cut, and the cutting range of the second cut is not beyond the range of the cutting track 2, so as to avoid damaging the chip 1 during the second cut.

FIG. 5 is a flow chart diagram of another testing method provided by some embodiments of the present application. Referring to fig. 5, the test method provided in the embodiment of the present application includes steps 501 to 507.

In step 501, a first insulating protection layer is formed on the surface of the wafer, and a first window area is disposed in a partial area of the first insulating protection layer.

For example, referring to fig. 1 and 2, the first insulating protective layer 6 refers to a polyimide film having a thickness of several micrometers coated on the surface of a wafer.

Thus, the electrical property and mechanical strength of the wafer can be improved, and the surface of the wafer is protected from pollution and damage.

In step 502, a redistribution layer is formed on the first insulating protection layer by physical sputtering and electroplating, and a portion of the redistribution layer located in the first window area is in contact with the bonding pad.

For example, the redistribution layer 5 may be formed on the first insulating protection layer 6 by means of physical sputtering and electroplating. The redistribution layer 5 is formed by depositing one or more layers of material on the wafer, first depositing a dielectric for isolation, then exposing the original contacts, and then depositing a new metal layer, such as a titanium metal layer or a copper metal layer, to form the redistribution layer 5.

In step 503, a second insulating protection layer is formed on the surface of the redistribution layer, and a second window area is disposed in a partial area of the second insulating protection layer.

The first insulating protective layer 6 and the second insulating protective layer 11 may be insulating protective layers made of the same material.

In step 504, an under bump metal layer is formed on the second insulating protection layer by physical sputtering and electroplating, where a portion of the under bump metal layer located in the second window region is in contact with the redistribution layer.

The under bump metal layer 4 may be used to support solder balls 3 or contact balls of other materials.

Step 505, performing ball placement, finished product quality control inspection (Final Quality Control, FQC), lapping, gum and printing on the under bump metallization layer in sequence.

Specifically, the solder balls 3 can be formed by performing ball implantation on the under bump metal layer 4, the FQC can be used for detecting the physical properties of the chip 1, and the wafer can be subjected to grinding to ensure that the processing damage on the surface of the wafer is uniform and consistent, so that the flatness of the surface of the wafer is improved. The FQC procedure can also be used to detect if the chip 1 has cracks, if the color is abnormal, if there is foreign material, etc.

In step 506, the wafer is diced for the first time at the dicing streets, so that the circuit layers of the plurality of chips which are not separated are separated.

In step 507, a probe test is performed on the plurality of chips separated by the circuit layer.

At step 508, a second dicing is performed on the plurality of chips that have completed the probe test at the dicing lanes.

In practical applications, the thickness of the wafer after lapping should be greater than 300 microns. In this way, the thickness of the wafer after the first dicing is sufficient for the second dicing.

In some embodiments, referring to fig. 6, fig. 6 is a flow chart diagram of yet another testing method provided by some embodiments of the present application. The test method provided by the embodiment of the application can comprise the following steps:

in step 601, a first insulating protection layer is formed on the surface of the wafer, and a first window opening area is disposed in a partial area of the first insulating protection layer.

In step 602, a redistribution layer is formed on the first insulating protection layer by physical sputtering and electroplating, and a portion of the redistribution layer located in the first window area is in contact with the bonding pad.

In step 603, a second insulating protection layer is formed on the surface of the redistribution layer, and a second window area is disposed in a partial area of the second insulating protection layer.

In step 604, an under bump metal layer is formed on the second insulating protection layer by physical sputtering and electroplating, where a portion of the under bump metal layer located in the second window region is in contact with the redistribution layer.

Step 605, ball placement, finished product quality control inspection (Final Quality Control, FQC), lapping, gum and printing are performed in sequence on the under bump metallization layer.

In step 606, the wafer is diced for the first time at dicing streets to separate the circuit layers of the plurality of chips that are not separated.

In step 607, a probe test is performed on the plurality of chips separated by the circuit layer.

In step 608, a test pattern corresponding to each chip is generated.

In step 609, a second dicing is performed on the plurality of chips that have completed the probe test at the dicing lanes.

Step 610, selecting a target chip meeting a preset condition from a plurality of chips according to the test pattern.

Specifically, after the probe station performs parallel test on the plurality of chips 1 separated by the circuit layer 8, a test pattern corresponding to each chip may be generated. The test patterns can be used for reflecting whether each chip accords with preset conditions, and the chip positions on the test patterns correspond to the chip positions of the wafer one by one.

For example, the position of the a chip on the test pattern corresponds to the position of the a chip on the wafer, if the position of the a chip on the test pattern is a circle, the a chip may be considered to meet the preset condition, otherwise, the a chip does not meet the preset condition. For another example, the position of the B chip on the test pattern corresponds to the position of the B chip on the wafer, and if the position of the B chip on the test pattern is the letter "T", the B chip may be considered to meet the preset condition, and if the position of the B chip on the test pattern is the letter "F", the B chip may be considered to not meet the preset condition.

It should be noted that, the above example of determining whether the chip meets the preset condition by using the test pattern is merely an example, the generated test pattern is not limited in the embodiment of the present application, and in practical application, the target chip meeting the preset condition may be selected from the plurality of chips 1 according to the generated test pattern.

After the dicing street 2 performs the second dicing on the plurality of chips 1 that have completed the probe test, the plurality of chips 1 included in the wafer are completely separated, and according to the test pattern, a target chip that meets the preset condition may be selected from the plurality of chips 1. For example, the chip sorter may sort out the target chip that meets the preset condition from the plurality of chips 1 based on the test pattern. The target chip may be considered as a qualified chip subjected to an electrical performance test.

In this embodiment, after the probe test, a test pattern corresponding to each chip 1 may be generated, and after the dicing lane 2 performs the second dicing on the plurality of chips 1 that have completed the probe test, a target chip that meets the preset condition may be selected from the plurality of chips 1 according to the test pattern. In this way, the likelihood that the target chip is a defective chip will be greatly reduced.

Those skilled in the art will appreciate that while some embodiments herein include certain features that are included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of testing, the method comprising:

performing first cutting on the wafer in the cutting channel; the wafer includes a plurality of chips that are not separated; the first dicing separates circuit layers of the plurality of chips that are not separated;

performing a probe test on the plurality of chips separated by the circuit layer;

and performing secondary cutting on the chips which are subjected to the probe test at the cutting path so as to separate the wafer into a plurality of independent chips.

2. The method of claim 1, wherein the first cut has a cut depth in the range of 30 microns to 50 microns.

3. The method of claim 1, wherein the probing the plurality of chips separated by the circuit layer comprises: and carrying out parallel test on the chips separated by the circuit layer through a probe station.

4. The method of claim 1, wherein the first cut has a greater cut width than the second cut.

5. The method of claim 4, wherein the difference between the cut width of the first cut and the cut width of the second cut is greater than 20 microns.

6. The method of claim 1, wherein the method further comprises, prior to the first dicing of the wafer by the dicing lanes:

forming a first insulating protection layer on the surface of the wafer, and arranging a first windowing area in a part area of the first insulating protection layer;

forming a redistribution layer on the first insulating protection layer by means of physical sputtering and electroplating, wherein the part of the redistribution layer, which is positioned in the first windowing region, is in contact with a welding pad;

forming a second insulating protective layer on the surface of the redistribution layer, and arranging a second windowing region in a part region of the second insulating protective layer;

forming an under bump metal layer on the second insulating protection layer by means of physical sputtering and electroplating, wherein a part of the under bump metal layer, which is positioned in the second windowing region, is in contact with the redistribution layer;

and sequentially performing ball planting, finished product quality control inspection FQC, grinding, gum coating and printing on the under-bump metal layer.

7. The method of claim 6, wherein the wafer has a thickness after the lapping of greater than 300 microns.

8. The method of claim 3, wherein after the probing of the plurality of chips separated by the circuit layer, the method further comprises:

generating a test map corresponding to each chip;

after the dicing street makes a second dicing of the plurality of chips that completed the probe test, the method further comprises:

and selecting a target chip meeting preset conditions from the plurality of chips according to the test pattern.

9. The method of claim 1, wherein the first cutting is by laser cutting or mechanical cutting.