CN118299284B - Packaging test method utilizing wafer corner area - Google Patents
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- CN118299284B CN118299284B CN202410723194.1A CN202410723194A CN118299284B CN 118299284 B CN118299284 B CN 118299284B CN 202410723194 A CN202410723194 A CN 202410723194A CN 118299284 B CN118299284 B CN 118299284B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 40
- 238000010998 test method Methods 0.000 title claims abstract description 6
- 238000012360 testing method Methods 0.000 claims description 129
- 239000000523 sample Substances 0.000 claims description 81
- 238000005530 etching Methods 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 abstract description 14
- 238000005538 encapsulation Methods 0.000 abstract description 8
- 238000013507 mapping Methods 0.000 description 13
- 239000010410 layer Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000012858 packaging process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a packaging test method utilizing a wafer corner region. By utilizing the technical scheme provided by the invention, the electrical conduction detection can be carried out on the via holes of the signal points of the intermediate layer encapsulation area for connecting the formal chip, the electrical conduction yield of the corresponding via holes of the intermediate layer is ensured, and after the detection is finished and the judgment is qualified, the signal points can be cut in the corner area to form open circuits among each other, the original functions and circuit structures of each signal pin after the chip encapsulation are not influenced, so that the subsequent encapsulation can be directly carried out, the detection efficiency and the accuracy are ensured, and the yield and the efficiency of the final encapsulation can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging and testing, in particular to a packaging testing method utilizing a wafer corner region.
Background
Semiconductor chip packaging is the final stage of the semiconductor device manufacturing process. At this critical point, the semiconductor blocks are covered with a protective layer that protects the Integrated Circuits (ICs) from potential external hazards and time erosion. Such packages essentially act as protective enclosures, shielding the IC blocks and facilitating electrical connections responsible for transmitting signals to the electronic device circuit board. Advanced packaging has emerged in a variety of sophisticated technologies, each with unique advantages that can meet the increasing demands of modern technology. 2.5D packaging involves stacking two or more chips side by side and connecting them through an interposer. This approach improves performance and power efficiency by facilitating faster data transfer between chips. The interposer is a bridge for electrically connecting the chip and the substrate, and connects the chip on the upper surface and the substrate on the lower surface through the through silicon via in the center. Because the interposer is used for circuit switching, the arrangement quantity of the through silicon vias is more, and the conduction yield of the through silicon vias directly influences the yield of the packaged integrated circuit, the conduction of the through silicon vias of the interposer needs to be tested in the packaging process, and defective interposers are removed and repaired in time, so that the defect of low yield of finished products caused by the defects of the interposers in finished products is avoided. In some wafer packaging structures, the interposer has a plurality of corner regions not required to be connected to the die, the corner regions and the packaging regions connected to the die are separated by dicing streets, and the dicing streets generally penetrate through the whole wafer edge in a straight line, and the corner regions need to be diced and removed by the dicing streets in the packaging process.
By searching, technical literature on relevant package testing is disclosed in the prior art. For example, the invention patent publication with publication number "CN117913073a" entitled "semiconductor structure and method of forming, detecting, and packaging. The disclosed technical scheme includes that the wafer comprises a bonding surface, wherein the bonding surface is provided with a device area and a detection area which is close to the edge of the wafer and surrounds the device area; an interconnection pad located in the bonding surface of the device region; and the detection ring is positioned in the bonding surface of the detection region and surrounds the device region, the detection ring is provided with an opening, and the ends of the detection rings at the two sides of the opening are used for applying test signals to the detection ring so that the detection ring forms a circuit path. The main purpose of this prior art is to apply the test signal to detect the ring and detect whether the ring is sputtered and washed by the cleaning solution and lost, so as to determine whether the preset cleaning width of the edge cleaning process is reasonable, and no related technical scheme is proposed for the electrical conductivity of the interposer.
For example, the invention patent publication with publication number "CN104299959a" entitled "test structure for flip chip, and method of manufacturing flip chip". A flip chip test structure, a flip chip and a method of manufacturing a flip chip are disclosed. The flip chip comprises a wafer and a packaging substrate in a test structure of the flip chip, and the test structure comprises: one or more via link structures disposed within the die; the plurality of electric connection units are arranged on the functional surface of the wafer and connected with the through hole chain structure, and the plurality of electric connection units are connected in series through the through hole chain structure; and the two test leads are fixed on the packaging substrate and are respectively connected with the electric connection units at the head and tail positions in a one-to-one correspondence manner.
For example, japanese patent publication No. "JP2006165325A" entitled "wiring structure of board mounted IC package and method of inspecting electric connection defect". A new wiring structure and inspection method are proposed for solving the problems associated with inspection of the electrical connection quality of an IC package in which an IC package (BGA package) having a semiconductor element mounted on an intermediate layer is electrically connected to a substrate through a conductive element. A wiring structure of a substrate on which an IC package is mounted, wherein a plurality of solder rings are provided on an interposer and connected by wires through the wiring, a BGA package is mounted on the substrate, and conductive members of the wires constitute a series of series circuit test loops.
Although the conductivity of the package system can be tested in the above prior art, the conductivity of the via hole of the interposer cannot be tested, so it is of great significance in the art to propose a package testing method using the wafer corner region, which can achieve the above-mentioned testing purpose and does not affect the subsequent packaging process.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a packaging test method by utilizing a wafer corner area, at least one test area is deployed in the corner area of an interposer, the interposer is a packaging area in a non-coverage area of the test area, the upper surface of the packaging area is provided with a signal point A n to be tested, and the signal point A n is mapped to a probe point C n on the lower surface by a first via hole of the packaging area; the signal point A n is mapped to the signal point B n of the test area by the surface etching circuit of the intermediate layer, a probe test loop is formed among the signal point A n, the probe point C n and the signal point B n by the surface etching circuit of the intermediate layer, probe test is carried out on the probe signal input point selected by the probe test loop, whether the first through holes are normally conducted is judged according to the probe test result, if all the first through holes are normally conducted, the test result is normal, wherein n is a positive integer.
Further, a second via is formed in the test area for mapping the signal point B n to the signal point D n on the lower surface of the test area, and a series test loop is formed by using the first via, the second via and the surface etching circuit of the interposer.
Further, the signal point a n and the signal point B n+1 are connected through an upper surface etching circuit mapping of the interposer, the signal point D n and the probe point C n are connected through a lower surface etching circuit mapping of the interposer, and the signal point B n and the signal point D n are mapped through a second via hole, so that a series test loop is formed between the signal point B 1 and the signal point B n.
Or the signal point a n and the signal point B n are connected through an upper surface etching circuit mapping of the interposer, the probe point C n and the signal point D n+1 are connected through a lower surface etching circuit mapping of the interposer from the probe point C 2, the signal point B n and the signal point D n are connected through a second mapping of the via hole from the signal point B 3, the signal point B 1 and the signal point B 2 are short-circuited through the surface etching circuit of the interposer, and a series test loop is formed between the probe point C 1 and the probe point C n.
Further, the signal point a n is mapped to the signal point B n of the test area by the etching circuit on the upper surface of the interposer, and the signal points B 1 to B n are shorted on the upper surface of the interposer, so that a parallel test loop is formed between the probe point C 1 and the probe point C n.
Or the signal point A n is mapped to the signal point B n of the test area by the etching circuit on the upper surface of the interposer, the probe point C n is mapped to the signal point D n of the test area by the etching circuit on the lower surface of the interposer, and the signal points D 1 -D n are short-circuited on the lower surface of the interposer, so that a parallel test loop is formed between the signal points B 1 -B n.
Further, the interval between the signal points B n is larger than the interval between the signal point a n and the probe point C n, the signal point B n is sequentially used as a probe signal input point for probe test in the test area, when all the signal points B n in the test loops are conducted normally, the test result returns to normal, otherwise, the test result returns to abnormal.
Further, the probe points C n are sequentially used as probe signal input points to carry out probe test on the back of the packaging area, when the probe points C n in all the test loops are conducted normally, the test result returns to normal, otherwise, the test result returns to abnormal.
Also provided is a packaged test integrated circuit comprising an interposer, wherein the interposer upper surface signal points A n to the interposer edge or the interposer lower surface probe points C n to the interposer edge are connected by surface etched circuits, and the surface etched circuits are open.
The packaging method is also provided, the interposer is round, arched testing areas are arranged at the peripheral edges of the round interposer, and the center of each testing area is a rectangular packaging area; after the packaging test result returns to normal, cutting the test area along the edge of the packaging area after the probe test is finished, so that a surface etching circuit between the signal point A n and the signal point B n is cut off to form an open circuit between the signal points A n; and then connecting the formal chip on the upper surface of the packaging area, and finally connecting the intermediate layer with the substrate.
Compared with the prior art, the technical scheme of the application has the following beneficial effects: by utilizing the technical scheme provided by the application, the electrical conduction detection can be carried out on the via holes of the signal points of the intermediate layer encapsulation area for connecting the formal chip, the electrical conduction yield of the corresponding via holes of the intermediate layer is ensured, and after the detection is finished and the judgment is qualified, the signal points can be cut in the corner area to form open circuits among each other, the original functions and circuit structures of each signal pin after the chip encapsulation are not influenced, so that the subsequent encapsulation can be directly carried out, the detection efficiency and the accuracy are ensured, and the yield and the efficiency of the final encapsulation can be improved.
Drawings
Fig. 1: the first schematic plan view of the interposer provided in the embodiment of the invention;
Fig. 2: a schematic diagram of a test loop according to a first embodiment of the present invention;
fig. 3: a schematic diagram of a test loop in the second embodiment of the present invention;
fig. 4: a test loop schematic diagram of the third embodiment of the present invention;
fig. 5: a test loop schematic diagram of a fourth embodiment of the present invention;
Fig. 6: a test loop schematic diagram of a fifth embodiment of the present invention;
Fig. 7: the second schematic plan view of the interposer provided in the embodiment of the present invention;
fig. 8: in the sixth embodiment of the invention, a formal chip connection and test area cutting schematic diagram is provided;
fig. 9: in the sixth embodiment of the invention, a substrate is connected.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1 and fig. 7, in a package testing method using a wafer corner area, at least one testing area 11 is disposed in a corner area of an interposer 1, the interposer 1 is a packaging area 12 in a non-coverage area of the testing area 11, a signal point a n to be tested is provided on an upper surface of the packaging area 12, and the signal point a n is mapped to a probe point C n on a lower surface by a first via 121 of the packaging area 12; the signal point A n is mapped to the signal point B n of the test area 11 by the surface etching circuit of the interposer 1, a probe test loop is formed among the signal point A n, the probe point C n and the signal point B n by using the surface etching circuit of the interposer 1, a probe signal input point is selected for the probe test loop to conduct probe test, whether the first through hole 121 is normally conducted is judged according to the probe test result, and if all the first through holes 121 are normally conducted, the test result is normal, wherein n is a positive integer.
In this embodiment, the interposer 1 is circular, which is common in wafer packaging. A rectangular area is divided in the central area of the interposer 1 as a packaging area 12 for connecting the formal chip 2 to the interposer 1, so that the upper surface of the interposer 1 in the packaging area 12 has signal points a n to be tested. These signal points are mapped to the lower surface by the first via 121 of the package region 12, thereby electrically transferring the regular chip 2 through the interposer 1 and the substrate 3. In the processing process of the interposer 1, the yield of the first via 121 determines the electrical connection effectiveness between the main chip 2 and the substrate 3, so that the electrical conductivity of the first via 121 can be tested, the defect condition of the interposer 1 can be timely found, and the time and economic cost loss caused by the detection and finding of the defect after the subsequent connection of the main chip 2 and the completion of the whole packaging process can be avoided. Because the pitch of the signal points a n to be tested is smaller on the upper surface of the interposer 1, the pitch between the probe points C n is relatively larger due to the fan-out after the probe points C n are mapped to the lower surface by the first via 121, and thus the probe test on the first via 121 cannot be performed directly through the signal points a n and the probe point C n. Therefore, in this embodiment, the signal point A n is mapped to the signal point B n of the test region 11 by using the surface etching circuit of the interposer 1, so that the signal point B n can be fanned out by a larger pitch, and the signal point A n can be fanned out by using the surface etching circuit, a probe test loop is formed between probe point C n and signal point B n, so that signal point A n, signal point B n or probe point C n can be utilized to test the probe point, the electrical conductivity of via one 121 between probe points C n was tested. After the test is completed, since the signal point B n exists in the test region 11, an open circuit is formed between the signal points a n when the test region 11 is cut through the dicing lane; the pin functions of the main chip 2 are not affected in the subsequent packaging process.
The construction of the test circuit is described in detail below with different embodiments.
Embodiment one, as shown in fig. 2.
Two through holes 111 are formed in the test area 11 for mapping the signal point B n to the signal point D n on the lower surface of the test area 11, the signal point A n and the signal point B n+1 are connected through the etching circuit mapping on the upper surface of the interposer 1, The signal point D n and the probe point C n are connected through the etching circuit mapping of the lower surface of the intermediate layer 1, the signal point B n and the signal point D n are mapped through the second through hole 111, so that a series test loop is formed between the signal points B 1 -B n. Two paths of signal points are used for illustration, the signal points A 1 and A 2 are connected with the probe point C 1 and the probe point C 1 through the etching circuit mapping of the lower surface of the interposer 1, Signal point B 1 and signal point B 2 are connected to signal point D 1 and signal point D 2 through via two 111, And signal points A 1 and B 2 are connected with signal points A 2 and B 4 through the upper surface etching circuit mapping of the interposer 1, Thus, a series test loop is formed between the signal points B 1 -B 3.
In the second embodiment, as shown in fig. 3.
Unlike the second embodiment, the signal points a n and B n are connected by the upper surface etching circuit pattern of the interposer 1, the probe points C n and D n+1 are connected by the lower surface etching circuit pattern of the interposer 1 from the probe point C 2, From signal point B 3, signal point B n and signal point D n are mapped by via two 111, signal point B 1 and signal point B 2 are shorted by the interposer 1 surface etch circuit, So that a series test loop is formed between the probe points C 1 -C n. Four signal points are used for illustration. The signal points A 1 -A 4 and the probe points C 1 -C 1 are connected through the upper surface etching circuit mapping of the interposer 1, Signal points B 3 -B 4 are connected to signal points D 3 and D 4 via second via 111, Signal point B 1 -signal point B 2 are shorted by etching circuitry on the upper surface of interposer 1, and probe point C 2, signal point D 3 and probe point C 3, The signal points D 4 are connected through the etching circuit mapping on the lower surface of the interposer 1, so that a series test loop is formed between the probe points C 1 and C 4.
Embodiment three, as shown in fig. 4.
The difference between the third embodiment and the second embodiment is that the signal points B 1 -B 2 are short-circuited by etching the circuit on the lower surface of the interposer 1, that is, the signal points D 1 -D 2 are short-circuited, so that the same series test circuit can be formed in the second embodiment, but two more vias 111 are provided than in the second embodiment, so that the second embodiment is relatively preferable.
Unlike the serial test loops formed in the first, second and third embodiments, the parallel test loops are formed in the fourth and fifth embodiments. In which case the fourth embodiment is shown in figure 5.
The signal point A n is mapped to the signal point B n of the test area 11 by the etching circuit on the upper surface of the interposer 1, and the signal points B 1 -B n are shorted on the upper surface of the interposer 1, so that a parallel test loop is formed between the probe point C 1 -C n. Taking three signal points as an example. Signal points a 1 -a 3 are mapped to signal points B 1 -B 3 of the test area 11 by the upper surface etching circuit of the interposer 1, and signal points B 1 -B 3 are shorted to form a parallel test loop by the upper surface etching circuit of the interposer 1, so that the test area 11 does not need to process the second via 111.
Fifth embodiment, as shown in fig. 6.
Unlike the fourth embodiment, the signal point a n is mapped to the signal point B n of the test area 11 by the upper surface etching circuit of the interposer 1, the probe point C n is mapped to the signal point D n of the test area 11 by the lower surface etching circuit of the interposer 1, and the signal points D 1 to D n are shorted on the lower surface of the interposer 1, so that a parallel test loop is formed between the signal points B 1 to B n. Taking three signal points as an example, the signal points a 1 -a 3 are mapped to the signal points B 1 -B 3 of the test area 11 by the etching circuit on the upper surface of the interposer 1, and the probe points C 1 -C 3 are mapped to the signal points D 1 -D 3 of the test area 11 by the etching circuit on the lower surface of the interposer 1, so as to form a parallel test loop, and in this embodiment, the processing of the second via 111 on the test area 11 is not required.
After the series or parallel test loops are formed, the probe test can be performed. For the first and fifth embodiments, since the loop start point formed is mapped to the test area 11, the signal point B n can be directly selected as the probe signal input point at the test area 11. Taking the first embodiment as an example, the signal point B 1 may be used as the positive electrode, and the signal point B 2 and the signal point B 3 may be used as the negative electrode in sequence for performing the probe test. When each probe test is conducted normally, it indicates that the electrical conduction of the first via 121 to be tested is normal.
In contrast to the above embodiments, the second, third and fourth embodiments are different from the above embodiments in that the probe test should be performed by sequentially using the probe point C n as the probe signal input point on the back surface of the package region 12. Taking the fourth embodiment as an example, the back of the package region 12 may be used to make the probe point C 1 as the positive electrode, and the probe point C 2 and the probe point C 3 as the negative electrode sequentially for the probe test. When each probe test is conducted normally, it indicates that the electrical conduction of the first via 121 to be tested is normal.
The above embodiments have been described separately from different circuit forming schemes, and in the above embodiments, the interposer 1 has its upper surface or lower surface mapped with signal power by a surface etching circuit in order to form the above test circuit. After the test area 11 is cut, the signal points a n are open, although the surface circuitry remains. In this state, therefore, the upper surface signal point An of the interposer 1 to the edge of the interposer 1 or the lower surface probe point Cn of the interposer 1 to the edge of the interposer 1 are connected by the surface etching circuit, and the surface etching circuits are open-circuited to each other.
In the sixth embodiment, as shown in fig. 7 to 9.
The embodiment proposes a packaging method, based on the packaging test method designed in the above embodiment, an arcuate test area 11 is disposed at the peripheral edge of a circular interposer 1, and the center of the test area 11 is a rectangular packaging area 12; after the package test result returns to normal, the test area 11 is cut off at the edge of the package area 12 after the probe test is completed, so that the surface etching circuit between the signal point A n and the signal point B n is cut off to form an open circuit between the signal points A n; the formal chip 2 is then connected to the upper surface of the package region 12, and finally the interposer 1 is connected to the substrate 3. It should be noted that, the foregoing dicing test area 11 is not only for forming an open circuit between the signal points a n, but the dicing test area 11, which is originally the leftover material, needs to be diced in the packaging process, and the foregoing limitation is performed on the dicing mode, so that the open circuit between the signal points a n is further ensured, and the normal pin functions of the package area 12 will not be affected after the formal chip 2 is mounted.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (2)
1. A packaging test method using wafer corner region is characterized by comprising An interposer (1), wherein signal points An on the upper surface of the interposer (1) are connected to the edge of the interposer (1) or probe points C n on the lower surface of the interposer (1) are connected to the edge of the interposer (1) through surface etching circuits, and the surface etching circuits are mutually opened;
At least one test area (11) is arranged in the corner area of the interposer (1), the non-coverage area of the interposer (1) in the test area (11) is a packaging area (12), the upper surface of the packaging area (12) is provided with a signal point A n to be tested, and the signal point A n is mapped to a probe point C n on the lower surface by a first through hole (121) of the packaging area (12); the signal point A n is mapped to the signal point B n of the test area (11) by the surface etching circuit of the intermediate layer (1), a probe test loop is formed among the signal point A n, the probe point C n and the signal point B n by using the surface etching circuit of the intermediate layer (1), a probe signal input point is selected for probe test on the probe test loop, whether the first through holes (121) are normally conducted is judged according to the probe test result, and if all the first through holes (121) are normally conducted, the test result is normal, wherein n is a positive integer;
The interposer (1) is circular, an arched test area (11) is arranged at the periphery of the circular interposer (1), and the center of the test area (11) is a rectangular packaging area (12); after the packaging test result returns to normal, cutting the test area (11) along a wafer cutting path at the edge of the packaging area (12) after the probe test is finished, so that a surface etching circuit between the signal point A n and the signal point B n is cut off to form an open circuit between the signal points A n; the formal chip (2) is connected on the upper surface of the packaging area (12), and finally the intermediate layer (1) is connected with the substrate (3);
The signal point A n is mapped to the signal point B n of the test area (11) by the etching circuit on the upper surface of the interposer (1), and the signal points B 1 -B n are short-circuited on the upper surface of the interposer (1), so that a parallel test loop is formed between the probe point C 1 -the probe point C n.
2. The method for testing a package using a corner region of a wafer according to claim 1, wherein the pitch between signal points B n is larger than the pitch between signal points a n and probe point C n, and the probe test is performed in the test area (11) by sequentially using signal point B n as a probe signal input point, and when all the signal points B n in the test loops are conducted normally, the test result returns to normal, otherwise, the test result returns to abnormal.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103325771A (en) * | 2012-03-22 | 2013-09-25 | 矽品精密工业股份有限公司 | Interposer and electrical testing method thereof |
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| US6777965B1 (en) * | 1998-07-28 | 2004-08-17 | Micron Technology, Inc. | Interposer for electrically coupling a semiconductive device to an electrical apparatus |
| JP4131137B2 (en) * | 2002-07-17 | 2008-08-13 | 凸版印刷株式会社 | Interposer substrate continuity inspection method |
| JP2011247767A (en) * | 2010-05-27 | 2011-12-08 | Kyocera Corp | Interposer substrate |
| US8680882B2 (en) * | 2011-10-31 | 2014-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3D-IC interposer testing structure and method of testing the structure |
| CN112394202B (en) * | 2020-10-29 | 2023-06-27 | 珠海天成先进半导体科技有限公司 | Interconnection test fixture and interconnection test method for silicon adapter plate |
| CN112736159A (en) * | 2020-12-31 | 2021-04-30 | 三江学院 | Preparation method of selective polycrystalline silicon thickness and doping concentration battery structure |
| CN115692233A (en) * | 2022-11-16 | 2023-02-03 | 苏州赛迈测控技术有限公司 | Test method of radio frequency chip |
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| CN103325771A (en) * | 2012-03-22 | 2013-09-25 | 矽品精密工业股份有限公司 | Interposer and electrical testing method thereof |
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