CN116646352B - LDMOS process TVS device and method for manufacturing the same - Google Patents
LDMOS process TVS device and method for manufacturing the same Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
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- 238000005530 etching Methods 0.000 claims description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 32
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
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- 239000004065 semiconductor Substances 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 4
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides an LDMOS (laterally diffused metal oxide semiconductor) process TVS device and a manufacturing method thereof, wherein a cell area, a trigger area and an inner ring terminal area are formed in an inner ring area of the TVS device, a first MOS tube is formed in the cell area, a TVS tube is formed in the trigger area, a first grid resistor and a first grid structure are formed on a substrate main body of the inner ring area, a second MOS tube, a second grid resistor and a second grid structure are formed on a substrate main body of the outer ring area, an interconnection metal is used for enabling an anode of the TVS tube to be connected with a grid of the first MOS tube through the first grid structure, one end of the first grid resistor is connected with an anode of the TVS tube and the grid structure, the other end of the first grid resistor is connected with a source of the first MOS tube, a drain of the first MOS tube is connected with a cathode of the TVS tube and a drain of the second MOS tube, and one end of the second grid resistor is connected with a source of the first MOS tube, and the other end of the second grid resistor is connected with a source of the second MOS tube.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an LDMOS (laterally diffused metal oxide semiconductor) process TVS (transient voltage suppressor) device and a manufacturing method thereof.
Background
Transient Voltage Suppressors (TVSs) are widely applied to the field of ESD protection, traditional TVS devices generally adopt diode structures, and have the defects of high clamping voltage and large clamping coefficient, and are difficult to effectively protect circuits.
In the prior art, the TVS device with the SCR structure can effectively reduce the clamping coefficient, but the TVS device with the structure has the problems of high trigger voltage, easy trigger latch-up, difficult optimization of an ESD window and the like.
Therefore, how to reduce the clamping coefficient without affecting other performance of the device is a problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide an LDMOS (laterally diffused metal oxide semiconductor) process TVS device and a manufacturing method thereof, which can reduce the clamping coefficient of the device and improve the electrostatic protection and current discharge capacity of the device.
In order to achieve the above object, the present invention provides an LDMOS process TVS device, including:
the substrate comprises a substrate body, a first MOS tube, a second MOS tube, a first Metal Oxide Semiconductor (MOS) tube and a second MOS tube, wherein the substrate body comprises an inner ring region and an outer ring region from the center to the periphery;
A first grid resistor and a first grid structure are formed on the substrate main body of the inner ring region, and the first grid structure is connected with the grid of the first MOS tube;
a second MOS tube, a second grid resistor and a second grid structure are formed on the substrate main body of the outer ring region, and the second grid structure is connected with the grid of the second MOS tube;
interconnecting metal, so that the anode of the TVS tube is connected with the grid electrode of the first MOS tube through the first grid electrode structure; one end of the first grid resistor is connected with the anode of the TVS tube and the first grid structure, and the other end of the first grid resistor is connected with the source electrode of the first MOS tube; connecting the drain electrode of the first MOS to the cathode of the TVS tube and the drain electrode of the second MOS tube, and connecting one end of the second grid resistor to the second grid structure and the source electrode of the first MOS, and connecting the other end of the second grid resistor to the source electrode of the second MOS tube;
the first MOS tube and the second MOS tube are manufactured through an LDMOS process, and the interconnection metals are all arranged on the same side of the substrate main body.
In an alternative scheme, the terminal area of the inner ring area surrounds the periphery of the cell area, the terminal area of the inner ring area comprises a partial pressure inner ring and a partial pressure outer ring, and the trigger area is arranged between the partial pressure inner ring and the partial pressure outer ring.
In an alternative scheme, the cell area is located in the center of the inner ring area, the trigger area is located at one side edge of the cell area, and the inner ring terminal area is annular and surrounds the cell area and the trigger area.
In an alternative scheme, the substrate main body comprises a substrate of a first conductive type and a homoepitaxial layer formed on the substrate, wherein the doping concentration of the substrate is larger than that of the epitaxial layer;
The trigger region comprises a heavily doped first-conductivity-type first deep body region and a first-conductivity-type first well region formed in the epitaxial layer, and a second-conductivity-type first injection region formed in the first well region, wherein the first deep body region and the first injection region form the TVS tube in the form of a diode.
In an alternative scheme, the cell region and the cell region to the trigger region comprise a second well region of a second conductivity type formed in the epitaxial layer, a second injection region of a heavily doped second conductivity type formed in the second well region, a second deep body region of a heavily doped first conductivity type formed in the epitaxial layer, a third well region of a first conductivity type formed on the upper periphery of the deep body region, a third injection region of a second conductivity type formed in the third well region, and polysilicon formed above the epitaxial layer, wherein the second injection region forms the drain electrode of the first MOS tube, the second deep body region, the third well region and the third injection region together form the source electrode of the first MOS tube, and the polysilicon forms the gate electrode of the first MOS tube, the first gate structure and the first gate resistor, or the second well region forms the first gate resistor.
In an alternative scheme, an annular isolation oxidation ring is arranged between the inner ring region and the outer ring region.
In an alternative scheme, the TVS device further comprises an outer ring terminal area surrounding the outer ring area, the outer ring terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the partial pressure inner ring and the partial pressure outer ring are annular polycrystalline silicon columns.
The invention also provides a manufacturing method of the TVS device of the LDMOS process, which comprises the following steps:
providing a substrate body comprising a substrate of a first conductivity type and a homoepitaxial layer formed on the substrate, the substrate having a doping concentration greater than the doping concentration of the epitaxial layer;
Planning an inner ring zone and an outer ring zone, planning an inner ring cell zone, a trigger zone and an inner ring terminal zone in the inner ring zone, and planning an outer ring cell zone in the outer ring zone;
Forming a deep body region with a first heavily doped conductivity type in the epitaxial layer through an implantation and diffusion process, wherein the deep body region in the trigger region is defined as a first deep body region, and the deep body regions in the inner ring cell region and the outer ring cell region are defined as a second deep body region;
Forming a first oxide layer to cover the epitaxial layer and the deep body region;
forming a first silicon nitride layer on the first oxide layer;
Forming lightly doped second well regions of a second conductivity type in the inner ring cell region and the epitaxial layer of the outer ring cell region by utilizing photoetching, etching and injection processes;
forming a second oxide layer on the second well region;
Removing the first silicon nitride on the first oxide layer by using an etching process;
Forming a lightly doped well region of a first conductivity type in the epitaxial layer by using an implantation process and the second oxide layer as masks, wherein the well region positioned in the trigger region is defined as a first well region, and the well regions positioned in the inner ring cell region and the outer ring cell region are defined as a third well region;
removing the first oxide layer and the second oxide layer on the surface of the epitaxial layer by using an etching process;
forming a third oxide layer on the epitaxial layer by using thermal oxygen or a thin film process;
Depositing second silicon nitride on the third oxide layer by using a thin film process;
Removing part of the second silicon nitride by utilizing a photoetching and etching process, and forming a fourth oxide layer on the epitaxial layer by utilizing a thermal oxidation process;
Removing the rest second silicon nitride by using an etching process, and forming a fifth oxide layer on the epitaxial layer by using a thermal oxidation process;
Depositing polysilicon on the fourth oxide layer and the fifth oxide layer by using a thin film process;
Forming a first injection region of a heavy doping second conductivity type in the first well region by utilizing photoetching and injection processes, forming a second injection region of the heavy doping second conductivity type in the second well region, and forming a third injection region of the heavy doping second conductivity type in the third well region;
forming a sixth oxide layer on the fourth oxide layer, the fifth oxide layer and the polysilicon by using a thin film process;
Etching the sixth oxide layer and the fifth oxide layer by utilizing photoetching and etching processes so as to form a contact hole on the epitaxial layer;
forming an interconnection metal in the metal hole and on the upper surface of the substrate body;
The first deep body region and the first injection region form a TVS tube in the form of a diode;
The second injection region is positioned in the inner ring region, the second deep body region, the third well region and the third injection region form a drain electrode of a first MOS tube, the second deep body region, the third well region and the third injection region form a source electrode of the first MOS tube together, the polysilicon forms a grid electrode of the first MOS tube, a first grid electrode structure and a first grid electrode resistor, or the second well region forms the first grid electrode resistor;
The second injection region is positioned in the outer ring region, the second deep body region, the third well region and the third injection region form a drain electrode of a second MOS tube, the second deep body region, the third well region and the third injection region form a source electrode of the second MOS tube together, the polysilicon forms a grid electrode of the second MOS tube, a second grid electrode structure and a second grid electrode resistor, or the second well region forms the second grid electrode resistor;
The interconnection metal enables the anode of the TVS tube to be connected with the grid electrode of the first MOS tube through the first grid electrode structure, one end of the first grid electrode resistor is connected with the anode of the TVS tube and the first grid electrode structure, the other end of the first grid electrode resistor is connected with the source electrode of the first MOS tube, the drain electrode of the first MOS is connected with the cathode of the TVS tube and the drain electrode of the second MOS tube, one end of the second grid electrode resistor is connected with the second grid electrode structure and the source electrode of the first MOS tube, the other end of the second grid electrode resistor is connected with the source electrode of the second MOS tube, and the first polycrystalline silicon in the inner ring cell area is connected with the source electrode of the first MOS tube.
In an alternative scheme, the inner ring terminal region surrounds the periphery of the inner ring cell region;
the inner ring terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the triggering area is arranged between the partial pressure inner ring and the partial pressure outer ring.
In an alternative scheme, the inner ring cell area is located in the center of the inner ring area, the trigger area is located at one side edge of the inner ring cell area, and the inner ring terminal area is annular and surrounds the inner ring cell area and the trigger area.
In an alternative, the method further comprises forming an annular isolation oxide ring between the inner ring region and the outer ring region.
In an alternative scheme, the junction depth of the deep body region is larger than that of the second well region.
In an alternative, the deep body region is contiguous with the substrate.
The invention has the beneficial effects that:
The invention converts the dynamic resistance of the TVS tube into the transconductance of the MOS tube, and the MOS tube has negative temperature coefficient, which leads the TVS device to have smaller dynamic resistance per unit area compared with the traditional TVS device, reduces the clamping coefficient of the device and improves the electrostatic protection and current discharge capacity of the device.
Drawings
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.
Fig. 1 shows a schematic structure of an LDMOS process TVS device according to an embodiment of the present invention.
Fig. 2 illustrates a circuit diagram of an LDMOS process TVS device according to an embodiment of the present invention.
Fig. 3 illustrates an LDMOS process TVS device inner ring area layout in accordance with an embodiment of the present invention.
Fig. 4 illustrates an LDMOS process TVS device inner ring area layout according to another embodiment of the present invention.
Fig. 5 to 18 are schematic structural diagrams illustrating cross-sections corresponding to different positions in the LDMOS process TVS device manufacturing process according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
Referring to fig. 1 to 18, the present embodiment provides an LDMOS process TVS device, including:
the substrate comprises a substrate body, a trigger region 210 and an inner ring terminal region 201, wherein the substrate body comprises an inner ring region and an outer ring region from the center to the periphery, a cell region 200, a first MOS tube, a TVS tube and a TVS tube are formed in the inner ring region 200, the trigger region 210 and the inner ring terminal region 201;
A first grid resistor 202 and a first grid structure 203 are formed on the substrate main body of the inner circle region, and the first grid structure 203 is connected with the grid of the first MOS tube;
A second MOS tube, a second grid resistor and a second grid structure are formed on the substrate main body of the outer ring region, and the second grid structure is connected with the grid of the second MOS tube;
The method comprises the steps of connecting an anode of a TVS tube with a grid electrode of a first MOS tube through a first grid electrode structure 203, connecting one end of a first grid electrode resistor 202 with the anode of the TVS tube and the first grid electrode structure 203, connecting the other end of the first grid electrode resistor with a source electrode of the first MOS tube, connecting a drain electrode of the first MOS with a cathode of the TVS tube and a drain electrode of a second MOS tube, connecting one end of the second grid electrode resistor with a source electrode of the second grid electrode structure and the first MOS tube, and connecting the other end of the second grid electrode resistor with a source electrode of the second MOS tube;
the first MOS tube and the second MOS tube are manufactured through an LDMOS process, and the interconnection metals are all arranged on the same side of the substrate main body.
Referring to fig. 3, in this embodiment, the inner ring area terminal area 201 surrounds the outer periphery of the cellular area 200, and the inner ring area terminal area 201 includes a partial pressure inner ring and a partial pressure outer ring, and the trigger area 210 is disposed between the partial pressure inner ring and the partial pressure outer ring. The partial pressure inner ring and the partial pressure outer ring are annular polycrystalline silicon columns surrounding the cell area and the first oxide layer on the periphery of the annular polycrystalline silicon columns.
Referring to fig. 4, in another embodiment, the cell region is located at the center of the inner ring region, the trigger region 210 is located at one side edge of the cell region 200, and the inner ring terminal region 201 is ring-shaped to enclose the cell region 200 and the trigger region 210.
In the embodiment, the substrate body comprises a substrate of a first conductivity type and a homoepitaxial layer formed on the substrate, the doping concentration of the substrate is larger than that of the epitaxial layer, the trigger region comprises a heavily doped first-conductivity-type first deep body region and a first-conductivity-type first well region formed in the epitaxial layer, and a second-conductivity-type first injection region formed in the first well region, and the first deep body region and the first injection region form the TVS tube in a diode mode.
The cell region and the cell region to the trigger region comprise a second well region of a second conductivity type formed in the epitaxial layer, a second injection region of a heavily doped second conductivity type formed in the second well region, a second deep body region of a heavily doped first conductivity type formed in the epitaxial layer, a third well region of a first conductivity type formed on the upper periphery of the deep body region, a third injection region of a second conductivity type formed in the third well region, and polysilicon formed above the epitaxial layer, wherein the second injection region forms a drain electrode of the first MOS tube, the second deep body region, the third well region and the third injection region together form a source electrode of the first MOS tube, and the polysilicon forms a gate electrode of the first MOS tube, the first gate structure and the first gate resistor, or the second well region forms the first gate resistor.
An annular isolation oxidation ring is arranged between the inner ring region and the outer ring region.
The TVS device further comprises an outer ring terminal area surrounding the outer ring area, wherein the outer ring terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the partial pressure inner ring and the partial pressure outer ring are annular polycrystalline silicon columns.
It should be noted that, in the present application, one of the first conductivity type and the second conductivity type is N type, and the other is P type.
Example 2
The embodiment provides a method for manufacturing a TVS device of an LDMOS process, which can manufacture the TVS device of embodiment 1, and the method for manufacturing the TVS device includes:
providing a substrate body comprising a substrate of a first conductivity type and a homoepitaxial layer formed on the substrate, the substrate having a doping concentration greater than the doping concentration of the epitaxial layer;
An inner ring region and an outer ring region are planned, an inner ring cell region (the inner ring cell region is a region for forming a first MOS tube later), a trigger region (the trigger region is a region for forming a TVS tube later) and an inner ring terminal region are planned in the inner ring region, and an outer ring cell region (the outer ring cell region is a region for forming a second MOS tube) is planned in the outer ring region;
Forming a deep body region with a first heavily doped conductivity type in the epitaxial layer through an implantation and diffusion process, wherein the deep body region in the trigger region is defined as a first deep body region, and the deep body regions in the inner ring cell region and the outer ring cell region are defined as a second deep body region;
Forming a first oxide layer to cover the epitaxial layer and the deep body region;
forming a first silicon nitride layer on the first oxide layer;
Forming lightly doped second well regions of a second conductivity type in the inner ring cell region and the epitaxial layer of the outer ring cell region by utilizing photoetching, etching and injection processes;
forming a second oxide layer on the second well region;
Removing the first silicon nitride on the first oxide layer by using an etching process;
Forming a lightly doped well region of a first conductivity type in the epitaxial layer by using an implantation process and the second oxide layer as masks, wherein the well region positioned in the trigger region is defined as a first well region, and the well regions positioned in the inner ring cell region and the outer ring cell region are defined as a third well region;
removing the first oxide layer and the second oxide layer on the surface of the epitaxial layer by using an etching process;
forming a third oxide layer on the epitaxial layer by using thermal oxygen or a thin film process;
Depositing second silicon nitride on the third oxide layer by using a thin film process;
Removing part of the second silicon nitride by utilizing a photoetching and etching process, and forming a fourth oxide layer on the epitaxial layer by utilizing a thermal oxidation process;
Removing the rest second silicon nitride by using an etching process, and forming a fifth oxide layer on the epitaxial layer by using a thermal oxidation process;
Depositing polysilicon on the fourth oxide layer and the fifth oxide layer by using a thin film process;
Forming a first injection region of a heavy doping second conductivity type in the first well region by utilizing photoetching and injection processes, forming a second injection region of the heavy doping second conductivity type in the second well region, and forming a third injection region of the heavy doping second conductivity type in the third well region;
forming a sixth oxide layer on the fourth oxide layer, the fifth oxide layer and the polysilicon by using a thin film process;
Etching the sixth oxide layer and the fifth oxide layer by utilizing photoetching and etching processes so as to form a contact hole on the epitaxial layer;
forming an interconnection metal in the metal hole and on the upper surface of the substrate body;
The first deep body region and the first injection region form a TVS tube in the form of a diode;
The second injection region is positioned in the inner ring region, the second deep body region, the third well region and the third injection region form a drain electrode of a first MOS tube, the second deep body region, the third well region and the third injection region form a source electrode of the first MOS tube together, the polysilicon forms a grid electrode of the first MOS tube, a first grid electrode structure and a first grid electrode resistor, or the second well region forms the first grid electrode resistor;
The second injection region is positioned in the outer ring region, the second deep body region, the third well region and the third injection region form a drain electrode of a second MOS tube, the second deep body region, the third well region and the third injection region form a source electrode of the second MOS tube together, the polysilicon forms a grid electrode of the second MOS tube, a second grid electrode structure and a second grid electrode resistor, or the second well region forms the second grid electrode resistor;
The interconnection metal enables the anode of the TVS tube to be connected with the grid electrode of the first MOS tube through the first grid electrode structure, one end of the first grid electrode resistor is connected with the anode of the TVS tube and the first grid electrode structure, the other end of the first grid electrode resistor is connected with the source electrode of the first MOS tube, the drain electrode of the first MOS is connected with the cathode of the TVS tube and the drain electrode of the second MOS tube, one end of the second grid electrode resistor is connected with the second grid electrode structure and the source electrode of the first MOS tube, the other end of the second grid electrode resistor is connected with the source electrode of the second MOS tube, and the first polycrystalline silicon in the inner ring cell area is connected with the source electrode of the first MOS tube.
The distribution forms of the inner ring cell region, the trigger region and the inner ring terminal region in the inner ring region comprise the following two types:
1. The inner ring terminal region surrounds the periphery of the inner ring cell region, the inner ring terminal region comprises a partial pressure inner ring and a partial pressure outer ring, and the trigger region is arranged between the partial pressure inner ring and the partial pressure outer ring.
2. The inner ring cell region is positioned in the center of the inner ring region, the trigger region is positioned at one side edge of the inner ring cell region, and the inner ring terminal region is annular and surrounds the inner ring cell region and the trigger region.
The MOS transistor of the present embodiment is manufactured by an LDMOS process, and the following briefly describes a manufacturing method of the TVS device of the present embodiment:
Referring to fig. 5 to 18, the following briefly describes the method of manufacturing the TVS device of the present embodiment:
Step S1, growing an epitaxial layer P-EPI of a first conductivity type on a heavily doped silicon substrate P+SUB of the first conductivity type (P type);
S2, forming a hard mask on the epitaxial layer P-EPI by utilizing a thermal oxygen or thin film process;
Step S3, etching the hard mask by utilizing a photoetching and etching process, and forming Deep P+ regions (Deep body regions comprising a first Deep body region positioned in a trigger region and a second Deep body region positioned in an inner ring cell region and an outer ring cell region) on the epitaxial layer by an injection and diffusion process;
Preferably, the junction depth is made to be 2um-3um greater than the NW junction depth;
preferably, it is connected to the substrate p+sub;
s4, removing the hard mask on the surface of the epitaxial layer P-EPI;
s5, forming a first oxide layer by utilizing a hot oxygen or film process;
Step S6, forming a first silicon nitride on the first oxide layer by using a thin film process;
Step S7, forming lightly doped N-well (second well region) of the second conductivity type by utilizing photoetching, etching and injection processes;
S8, forming a second oxide layer on the epitaxial layer P-EPI by using a diffusion process;
Step S9, removing the silicon nitride on the first oxide layer by using an etching process;
Step S10, forming lightly doped P-wells (a first well region and a third well region) of the first conductivity type by using the implantation process and the second oxide layer as masks;
Step S11, removing the first oxide layer and the second oxide layer on the surface of the epitaxial layer P-EPI by using an etching process;
Step S12, forming a third oxide layer on the epitaxial layer P-EPI by utilizing a thermal oxygen or thin film process;
step S13, depositing second silicon nitride on the third oxide layer by utilizing a thin film process;
step S14, removing part of the second silicon nitride by utilizing photoetching and etching processes, and forming a fourth oxide layer on the epitaxy by utilizing a thermal oxidation process;
step S15, removing the rest second silicon nitride by using an etching process, and forming a fifth oxide layer on the epitaxy by using a thermal oxidation process;
step 16, depositing polysilicon on the fourth and fifth oxide layers by using a thin film process;
Step 17, removing part of the polysilicon by using an etching process, and forming an N+ injection region (comprising a first injection region (located in a first well region of the trigger region), a second injection region (located in a second well region of the inner cell region and the outer cell region) and a third injection region (located in a third well region of the inner cell region and the outer cell region) on the epitaxial layer by using a photoetching and injection process;
Step 18, forming a sixth oxide layer on the fourth oxide layer, the fifth oxide layer and the polysilicon by using a thin film process;
Step 19, etching the sixth oxide layer and the fifth oxide layer by utilizing photoetching and etching processes, and forming contact holes on the epitaxial layer;
Step 20, depositing interconnection metal in the contact hole and on the upper surface of the substrate main body;
preferably, a multi-layer metal process may be used, saving area, better forming the interconnect.
Preferably, the method further comprises forming an annular isolation trench surrounding the inner ring region between the inner ring region and the outer ring region, wherein the depth of the isolation trench is 2-3um greater than the thickness of the epitaxial layer 110, and then forming an oxide layer in the isolation trench by using a thermal oxygen or thin film process to form an isolation oxide ring.
It should be noted that, the second MOS transistor, the second gate resistor, and the second gate structure formed in the outer ring region are formed in the same step with the first MOS transistor, the first gate resistor, and the first gate structure in the inner ring region respectively by using the same material, but the positions formed are different.
The above two embodiments have the following advantages:
First, the present embodiment uses an LDMOS process, which is compatible with the existing process;
Secondly, the clamping coefficient of the traditional TVS device is generally 1.2-1.4, the LDMOS technology is improved under the existing equipment condition, the TVS is increased, the clamping coefficient is reduced to a level below 1.1, and the electrostatic protection, the current discharge capacity and the unit area utilization rate of the device are improved.
Thirdly, two times of MOS process TVS are nested, and the requirement of grid resistance is reduced.
Example 3
The difference between this embodiment and the above 2 embodiments is that in the first 2 embodiments, the first gate resistance of the inner ring region is formed of polysilicon of the inner ring region, the second gate resistance of the outer ring region is formed of polysilicon of the outer ring region, and in this embodiment, the first gate resistance of the inner ring region is formed of a second well region of the inner ring region, and the second gate resistance of the outer ring region is formed of a second well region of the outer ring region.
In example 3 of the present specification, only the portions different from example 1 are described, and the same portions as example 1 are referred to example 1.
The invention converts the dynamic resistance of the TVS tube into the transconductance of the MOS tube, and the MOS tube has negative temperature coefficient, which leads the TVS device to have smaller dynamic resistance per unit area compared with the traditional TVS device, reduces the clamping coefficient of the device and improves the electrostatic protection and current discharge capacity of the device.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (13)
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