CN116487384B - A SGT MOS process TVS device and its manufacturing method - Google Patents
A SGT MOS process TVS device and its manufacturing method Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 62
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 90
- 229920005591 polysilicon Polymers 0.000 claims description 86
- 239000010409 thin film Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 210000000746 body region Anatomy 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 6
- 230000001413 cellular effect Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
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- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
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Abstract
The invention provides a TVS device of SGT MOS technology and a manufacturing method thereof, wherein a cell area, a trigger area and an inner ring terminal area are formed in an inner ring area of the TVS device; a first MOS tube is formed in the cell region, and a TVS tube is formed in the trigger region; a first grid resistor and a first grid structure are formed on the substrate main body of the inner ring region; a second MOS tube, a second grid resistor and a second grid structure are formed on the substrate main body of the outer ring region; interconnecting metal, so that the anode of the TVS tube is connected with the grid electrode of the first MOS tube through the first grid electrode structure; one end of the first grid resistor is connected with the anode and the grid structure of the TVS tube, and the other end of the first grid resistor is connected with the source electrode of the first MOS tube; connecting the drain electrode of the first MOS with the cathode of the TVS tube and the drain electrode of the second MOS tube; one end of the second grid resistor is connected with the second grid structure and the source electrode of the first MOS, and the other end of the second grid resistor is connected with the source electrode of the second MOS tube.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a TVS device of an SGT MOS process and a manufacturing method thereof.
Background
Transient Voltage Suppressors (TVSs) are widely applied to the field of ESD protection, traditional TVS devices generally adopt diode structures, and have the defects of high clamping voltage and large clamping coefficient, and are difficult to effectively protect circuits.
In the prior art, the TVS device with the SCR structure can effectively reduce the clamping coefficient, but the TVS device with the structure has the problems of high trigger voltage, easy trigger latch-up, difficult optimization of an ESD window and the like.
Therefore, how to reduce the clamping coefficient without affecting other performance of the device is a problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide an SGT MOS process TVS device and a manufacturing method thereof, which can reduce the clamping coefficient of the device and improve the electrostatic protection and current discharge capacity of the device.
In order to achieve the above object, the present invention provides an SGT MOS process TVS device, including:
a substrate body including an inner ring region and an outer ring region from a center to an outer periphery; a cellular region, a trigger region and an inner ring terminal region are formed in the inner ring region; a first MOS tube is formed in the cell region, and a TVS tube is formed in the trigger region;
a first grid resistor and a first grid structure are formed on the substrate main body of the inner ring region; the first grid structure is connected with the grid of the first MOS tube;
A second MOS tube, a second grid resistor and a second grid structure are formed on the substrate main body of the outer ring region, and the second grid structure is connected with the grid of the second MOS tube;
the substrate body includes a substrate of a first conductivity type and a homoepitaxial layer formed on the substrate; the epitaxial layers of the inner ring region and the outer ring region are formed with: a base region of a second conductivity type, a source region of a first conductivity type and a body region of the second conductivity type in the base region, and first polysilicon and second polysilicon isolated from each other, wherein the second polysilicon is located above the first polysilicon;
located in the inner ring region: the source region forms a source electrode of the first MOS tube, the substrate is used as a drain electrode of the first MOS tube, and the second polysilicon forms a grid electrode and a first grid electrode structure of the first MOS tube; the first polysilicon outside the cell region forms the first grid resistor, or the first grid resistor is formed by the base region;
Located in the outer ring region: the source region forms a source electrode of the second MOS tube, the substrate is used as a drain electrode of the second MOS tube, and the second polysilicon forms a grid electrode and a second grid electrode structure of the second MOS tube; the first polysilicon forms the second grid resistor, or the second grid resistor is formed by the base region;
Interconnecting metal, so that the anode of the TVS tube is connected with the grid electrode of the first MOS tube through the first grid electrode structure; one end of the first grid resistor is connected with the anode of the TVS tube and the first grid structure, and the other end of the first grid resistor is connected with the source electrode of the first MOS tube; connecting the drain electrode of the first MOS to the cathode of the TVS tube and the drain electrode of the second MOS tube; one end of the second grid resistor is connected with the second grid structure and the source electrode of the first MOS, and the other end of the second grid resistor is connected with the source electrode of the second MOS tube; and connecting the first polysilicon in the cell region with the source electrode of the first MOS tube, and connecting the first polysilicon in the outer ring region with the source electrode of the second MOS tube.
In an alternative scheme, the terminal area of the inner ring area surrounds the periphery of the cellular area;
the inner ring area terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the trigger area is arranged between the partial pressure inner ring and the partial pressure outer ring.
In an alternative scheme, the cell area is located in the center of the inner ring area, the trigger area is located at one side edge of the cell area, and the inner ring terminal area is annular and surrounds the cell area and the trigger area.
In an alternative, the trigger area includes: and forming a first doped region of a first conductivity type and a second doped region of a second conductivity type which are arranged up and down or left and right in the epitaxial layer to form the TVS tube of the PN structure.
In an alternative scheme, an annular isolation oxidation ring is arranged between the inner ring region and the outer ring region.
In an alternative scheme, the TVS device further comprises an outer ring terminal area surrounding the outer ring area, the outer ring terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the partial pressure inner ring and the partial pressure outer ring are annular polycrystalline silicon columns.
The invention also provides a manufacturing method of the TVS device of the SGT MOS process, which comprises the following steps:
Providing a substrate body comprising a substrate of a first conductivity type and a homoepitaxial layer formed on the substrate;
Planning an inner ring zone and an outer ring zone, planning an inner ring cell zone, a trigger zone and an inner ring terminal zone in the inner ring zone, and planning an outer ring cell zone in the outer ring zone;
Forming a plurality of trenches in the epitaxial layer;
Forming a first oxide layer to cover the inner wall of the groove and forming first polysilicon in the groove;
removing the first polysilicon at the upper parts of the grooves in the inner ring cell region and the outer ring cell region;
forming a second oxide layer to cover the first polysilicon;
forming second polysilicon on the first polysilicon in the grooves of the inner ring cell region and the outer ring cell region;
forming a base region of a second conductivity type on the whole surface of the epitaxial layer by using an injection and diffusion process;
Forming a first doped region of a first conductivity type and a second doped region of a second conductivity type in the base region of the trigger region by utilizing photoetching, injection and diffusion processes;
Forming a heavily doped source region of a first conductivity type in the inner ring cell region and the outer ring cell region by utilizing photoetching, injection and annealing processes;
forming a surface oxide layer by using a thin film process, and covering the whole epitaxial layer;
Forming a contact hole in the surface oxide layer to expose the epitaxial layer, the first polysilicon and the second polysilicon;
Forming a heavily doped body region of a second conductivity type at the bottom of the contact hole;
forming a front metal in the contact hole and on the surface oxide layer;
Thinning the substrate on the back and forming back metal; the front side metal and the back side metal constitute an interconnect metal;
the first doped region and the second doped region form a TVS tube in the form of a diode;
Located in the inner ring region: the source region forms a source electrode of a first MOS tube, the substrate is used as a drain electrode of the first MOS tube, the second polysilicon forms a grid electrode of the first MOS tube and a first grid electrode structure, and the first grid electrode structure is connected with the grid electrode of the first MOS tube; the first polysilicon outside the inner cell region forms the first grid resistor, or the first grid resistor is formed by the base region;
Located in the outer ring region: the source region forms a source electrode of the second MOS tube, the substrate is used as a drain electrode of the second MOS tube, the second polysilicon forms a grid electrode of the second MOS tube and a second grid electrode structure, and the second grid electrode structure is connected with the grid electrode of the second MOS tube; the first polysilicon forms the second grid resistor, or the second grid resistor is formed by the base region;
The interconnection metal enables the anode of the TVS tube to be connected with the grid electrode of the first MOS tube through the first grid electrode structure; one end of the first grid resistor is connected with the anode of the TVS tube and the first grid structure, and the other end of the first grid resistor is connected with the source electrode of the first MOS tube; connecting the drain electrode of the first MOS to the cathode of the TVS tube and the drain electrode of the second MOS tube; one end of the second grid resistor is connected with the second grid structure and the source electrode of the first MOS, and the other end of the second grid resistor is connected with the source electrode of the second MOS tube; and connecting the first polysilicon in the cell region with the source electrode of the first MOS tube, and connecting the first polysilicon in the outer ring region with the source electrode of the second MOS tube.
In an alternative, the inner ring of termination regions surrounds the periphery of the cell region;
The inner ring terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the triggering area is arranged between the partial pressure inner ring and the partial pressure outer ring.
In an alternative scheme, the cell area is located in the center of the inner ring area, the trigger area is located at one side edge of the cell area, and the inner ring terminal area is annular and surrounds the cell area and the trigger area.
In an alternative, the method further comprises: an annular isolation oxide ring is formed between the inner ring region and the outer ring region.
The invention has the beneficial effects that:
the invention converts the dynamic resistance of the TVS tube into the transconductance of the MOS tube, and the MOS tube has negative temperature coefficient, which leads the TVS device to have smaller dynamic resistance per unit area compared with the traditional TVS device, reduces the clamping coefficient of the device and improves the electrostatic protection and current discharge capacity of the device.
Drawings
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.
Fig. 1 shows a schematic structural diagram of an SGT MOS process TVS device according to an embodiment of the present invention.
Fig. 2 shows a circuit diagram of an SGT MOS process TVS device in accordance with an embodiment of the present invention.
Fig. 3 illustrates a layout of a SGT MOS process TVS device inner ring region in accordance with one embodiment of the present invention.
Fig. 4 illustrates a layout of a SGT MOS process TVS device inner ring region in accordance with another embodiment of the present invention.
Fig. 5 to 8 are schematic structural diagrams corresponding to different cross sections of a SGT MOS process TVS device according to an embodiment of the present invention.
Reference numerals illustrate:
100-a substrate; 110-an epitaxial layer; 200-cell region; 201-an inner ring termination region; 210-a trigger zone; 202-a first gate resistance; 203-a first gate structure; 30-a surface oxide layer; 61-first polysilicon; 62-second polysilicon; a 111-base region; 112-body region; 113-source region; 120-a first doped region; 121-a second doped region; 90-contact hole metal; 91-front side metal; 92-back metal; 20-a first oxide layer; 22-a second oxide layer; 23-a third oxide layer.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
Referring to fig. 1 to 8, the present embodiment provides an SGT MOS process TVS device, including:
A substrate body including an inner ring region and an outer ring region from a center to an outer periphery; a cell region 200, a trigger region 210 and a inner ring terminal region 201 are formed in the inner ring region; a first MOS transistor is formed in the cell region 200, and a TVS transistor is formed in the trigger region 210;
A first gate resistor 202 and a first gate structure 203 are formed on the substrate main body of the inner circle region; the first gate structure 203 is connected with the gate of the first MOS transistor;
A second MOS tube, a second grid resistor and a second grid structure are formed on the substrate main body of the outer ring region, and the second grid structure is connected with the grid of the second MOS tube;
The substrate body includes a substrate 100 of a first conductivity type and a homoepitaxial layer 110 formed on the substrate 100; the epitaxial layer 110 of the inner ring region and the outer ring region is formed with: a base region 111 of a second conductivity type, a source region 113 of a first conductivity type and a body region 112 of a second conductivity type located in the base region 111, a first polysilicon 61 and a second polysilicon 62 isolated from each other, wherein the second polysilicon 62 is located above the first polysilicon 61;
Located in the inner ring region: the source region 113 forms a source of the first MOS transistor, the substrate 110 is used as a drain of the first MOS transistor, and the second polysilicon 62 forms a gate of the first MOS transistor and a first gate structure 203; the first polysilicon 61 outside the cell region constitutes the first gate resistor 202;
Located in the outer ring region: the source region 113 forms a source of the second MOS transistor, the substrate 110 is used as a drain of the second MOS transistor, and the second polysilicon 62 forms a gate and a second gate structure of the second MOS transistor; the first polysilicon 61 constitutes the second gate resistance;
Interconnect metal (including front metal 91, back metal 92 and contact hole metal 90) to connect the anode of the TVS tube with the gate of the first MOS tube through the first gate structure 203; one end of the first gate resistor 202 is connected to the anode of the TVS tube and the first gate structure 203, and the other end is connected to the source of the first MOS tube; connecting the drain electrode of the first MOS to the cathode of the TVS tube and the drain electrode of the second MOS tube; one end of the second grid resistor is connected with the second grid structure and the source electrode of the first MOS, and the other end of the second grid resistor is connected with the source electrode of the second MOS tube; the first polysilicon 61 in the cell region is connected with the source electrode of the first MOS tube, and the first polysilicon 61 in the outer ring region is connected with the source electrode of the second MOS tube.
Referring to fig. 3, in this embodiment, the inner ring area terminal area 201 surrounds the outer periphery of the cell area 200; the inner ring zone terminal zone 201 includes a partial pressure inner ring and a partial pressure outer ring, and the trigger zone 210 is located between the partial pressure inner ring and the partial pressure outer ring. The partial pressure inner ring and the partial pressure outer ring are annular polycrystalline silicon columns surrounding the cell area and the first oxide layer on the periphery of the annular polycrystalline silicon columns.
Referring to fig. 4, in another embodiment, the cell region is located at the center of the inner ring region, the trigger region 210 is located at one side edge of the cell region 200, and the inner ring terminal region 201 is ring-shaped to enclose the cell region 200 and the trigger region 210.
In this embodiment, the trigger region includes a first doped region 120 of a first conductivity type and a second doped region 121 of a second conductivity type formed in the epitaxial layer 110 to form the TVS tube of a PN structure.
An annular isolation oxidation ring is arranged between the inner ring region and the outer ring region.
The TVS device further comprises an outer ring terminal area surrounding the outer ring area, wherein the outer ring terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the partial pressure inner ring and the partial pressure outer ring are annular polycrystalline silicon columns.
It should be noted that, in the present application, one of the first conductivity type and the second conductivity type is N type, and the other is P type.
Example 2
The present embodiment provides a method for manufacturing a TVS device of SGT MOS technology, capable of manufacturing a TVS device of embodiment 1, the method comprising:
Providing a substrate body comprising a substrate of a first conductivity type and a homoepitaxial layer formed on the substrate;
an inner ring region and an outer ring region are planned, an inner ring cell region (the inner ring cell region is a region for forming a first MOS tube later), a trigger region (the trigger region is a region for forming a TVS tube later) and an inner ring terminal region are planned in the inner ring region, and an outer ring cell region (the outer ring cell region is a region for forming a second MOS tube) is planned in the outer ring region;
Forming a plurality of trenches in the epitaxial layer;
Forming a first oxide layer to cover the inner wall of the groove and forming first polysilicon in the groove;
removing the first polysilicon at the upper parts of the grooves in the inner ring cell region and the outer ring cell region;
forming a second oxide layer to cover the first polysilicon;
forming second polysilicon on the first polysilicon in the grooves of the inner ring cell region and the outer ring cell region;
forming a base region of a second conductivity type on the whole surface of the epitaxial layer by using an injection and diffusion process;
Forming a first doped region of a first conductivity type and a second doped region of a second conductivity type in the base region of the trigger region by utilizing photoetching, injection and diffusion processes;
Forming a heavily doped source region of a first conductivity type in the inner ring cell region and the outer ring cell region by utilizing photoetching, injection and annealing processes;
forming a surface oxide layer by using a thin film process, and covering the whole epitaxial layer;
Forming a contact hole in the surface oxide layer to expose the epitaxial layer, the first polysilicon and the second polysilicon;
Forming a heavily doped body region of a second conductivity type at the bottom of the contact hole;
forming a front metal in the contact hole and on the surface oxide layer;
Thinning the substrate on the back and forming back metal; the front side metal and the back side metal constitute an interconnect metal;
the first doped region and the second doped region form a TVS tube in the form of a diode;
Located in the inner ring region: the source region forms a source electrode of a first MOS tube, the substrate is used as a drain electrode of the first MOS tube, the second polysilicon forms a grid electrode of the first MOS tube and a first grid electrode structure, and the first grid electrode structure is connected with the grid electrode of the first MOS tube; the first polysilicon outside the inner ring cell region forms the first grid resistor;
located in the outer ring region: the source region forms a source electrode of the second MOS tube, the substrate is used as a drain electrode of the second MOS tube, the second polysilicon forms a grid electrode of the second MOS tube and a second grid electrode structure, and the second grid electrode structure is connected with the grid electrode of the second MOS tube; the first polysilicon forms the second gate resistor;
The interconnection metal enables the anode of the TVS tube to be connected with the grid electrode of the first MOS tube through the first grid electrode structure; one end of the first grid resistor is connected with the anode of the TVS tube and the first grid structure, and the other end of the first grid resistor is connected with the source electrode of the first MOS tube; connecting the drain electrode of the first MOS to the cathode of the TVS tube and the drain electrode of the second MOS tube; one end of the second grid resistor is connected with the second grid structure and the source electrode of the first MOS, and the other end of the second grid resistor is connected with the source electrode of the second MOS tube; and connecting the first polysilicon in the inner ring cell region with the source electrode of the first MOS tube, and connecting the first polysilicon in the outer ring region with the source electrode of the second MOS tube.
The distribution forms of the cell area, the trigger area and the inner ring terminal area in the inner ring area comprise the following two types:
1. The inner ring terminal region surrounds the periphery of the cell region; the inner ring terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the triggering area is arranged between the partial pressure inner ring and the partial pressure outer ring.
2. The cell area is located in the center of the inner ring area, the trigger area is located at one side edge of the cell area, and the inner ring terminal area is annular and surrounds the cell area and the trigger area.
The MOS transistor of the present embodiment is manufactured by SGT MOS process, and referring to fig. 1 to 8, the following briefly describes the manufacturing method of the TVS device of the present embodiment:
Step S1, growing a lightly doped epitaxial layer 110 of the first conductivity type on a heavily doped semiconductor substrate silicon substrate 100 of the first conductivity type;
step S2, forming a hard mask on the epitaxial layer 110 using a thermal oxygen or thin film process;
step S3, etching the hard mask and the epitaxial layer 110 by utilizing a photoetching and etching process to form a plurality of grooves;
step S4, forming a first oxide layer 20 by using a thermal oxygen or thin film process;
Preferably, a first sacrificial oxide layer (the same as the first oxide layer) can be formed before the first oxide layer is formed according to the process requirement, the first sacrificial oxide layer is removed, and then the first oxide layer is formed;
Step S5, forming a first polysilicon 61 in the trench by a thin film process,
S6, removing the upper part of the first polysilicon in the groove of the cellular region;
step S7, forming a second oxide layer 22 by using a thin film process to cover the first polysilicon 61;
Preferably, before depositing the second oxide layer, a second sacrificial oxide layer is formed on the upper surface of the first polysilicon 61 and the surface of the trench, and then the second sacrificial oxide layer is removed, and then the second oxide layer is formed;
S8, removing the second oxide layer and the hard mask on the epitaxial layer by using a planarization or etching process;
preferably, a second oxide layer or hard mask of 0-3000 angstroms is left over epitaxial layer 110;
step S9, removing the second oxide layer and the hard mask outside the top of the first polysilicon 61 in the set area by utilizing a photoetching and etching process;
step S10, forming a third oxide layer 23 by using a thin film or thermal oxidation process;
step S11, forming second polysilicon 62 by using a thin film process;
step S12, removing the second polysilicon outside the groove by using a flattening or etching process;
step S13, forming a heavily doped first doped region 120 of the first conductivity type in the trigger region by photolithography and implantation;
Preferably, the diffusion process can be added after the implantation process according to the process and trigger voltage requirements;
step S14, forming a base region 111 of the second conductivity type on the entire surface of the epitaxial layer 110 by using an implantation and diffusion process;
Preferably, the depth of the base region 111 is lower than the depth of the bottom surface of the second polysilicon 62;
Step S15, forming a second doped region 121 of a second conductivity type in the base region 111 of the trigger region by photolithography, implantation and diffusion processes;
preferably, the diffusion processes for forming the base region 111 and the second doped region 121 may be combined;
preferably, the depth of the second doped region 121 should be less than or equal to the depth of the trigger region trench and greater than the depth of the body region 112;
Step S16, forming a heavily doped source region 113 of the first conductivity type inside the cellular region 200 by photolithography, implantation and annealing;
step S17, forming a surface oxide layer 30 by a thin film process;
preferably, an annealing or flattening process can be added to improve the surface flatness;
Step S18, forming contact holes in the epitaxial layer 110, the first polysilicon 61 and the second polysilicon 62 by utilizing photoetching and etching processes;
Step S19, forming a heavily doped body region 112 of the second conductivity type at the bottom of the contact hole through the contact hole window by using an implantation process;
step S20, forming a surface oxide layer 30 by a thin film process;
preferably, an annealing or flattening process can be added to improve the surface flatness;
step S21, forming a contact hole metal 90 in the contact hole by using a thin film and etching or planarization process;
Step S22, forming a front metal 91 above the surface oxide layer 30 and the contact hole metal 90 by using photolithography and etching processes;
Preferably, a contact hole and a front metal interconnection are utilized to enable second polysilicon at a set position to form a grid electrode of the first MOS tube and the first grid electrode structure, and the first polysilicon forms the first grid electrode resistor;
In step S23, the substrate 100 is thinned and the back metal 92 is formed on the back surface of the substrate 100 by using thinning and thin film process. The contact hole metal 90, the front side metal 91 and the back side metal together constitute an interconnect metal.
It should be noted that the above method describes a step flow of forming each structure of the inner ring region, and the second MOS transistor, the second gate resistor and the second gate structure formed in the outer ring region are formed in the same step with the first MOS transistor, the first gate resistor and the first gate structure of the inner ring region respectively by using the same material, but the formed positions are different.
Preferably, an annular isolation trench surrounding the inner ring region is formed between the inner ring region and the outer ring region, the depth of the isolation trench being greater than the thickness of the epitaxial layer 110 by 2-3um; and forming an oxide layer in the isolation groove by utilizing a thermal oxygen or film process to form an isolation oxide ring.
The above two embodiments have the following advantages:
firstly, an SGT MOS process is utilized, and the SGT MOS process is compatible with the existing process;
Secondly, the clamping coefficient of the traditional TVS device is generally 1.2-1.4, under the existing equipment condition, the SGT MOS process is improved, the trigger area is increased, the clamping coefficient is reduced to a level below 1.1, and the electrostatic protection, the current discharge capacity and the unit area utilization rate of the device are improved;
second, two times of MOS process TVS are nested, and the requirement of grid resistance is reduced.
Example 3
The difference between this embodiment and the above 2 embodiments is that in the first 2 embodiments, the first gate resistance of the inner ring region is formed of the first polysilicon of the inner ring region, the second gate resistance of the outer ring region is formed of the first polysilicon of the outer ring region, and in this embodiment, the first gate resistance of the inner ring region is formed of the base region of the inner ring region, and the second gate resistance of the outer ring region is formed of the base region of the outer ring region.
In example 3 of the present specification, only the portions different from example 1 are described, and the same portions as example 1 are referred to example 1.
The invention converts the dynamic resistance of the TVS tube into the transconductance of the MOS tube, and the MOS tube has negative temperature coefficient, which leads the TVS device to have smaller dynamic resistance per unit area compared with the traditional TVS device, reduces the clamping coefficient of the device and improves the electrostatic protection and current discharge capacity of the device.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. An SGT MOS process TVS device, comprising:
a substrate body including an inner ring region and an outer ring region from a center to an outer periphery; a cellular region, a trigger region and an inner ring terminal region are formed in the inner ring region; a first MOS tube is formed in the cell region, and a TVS tube is formed in the trigger region;
a first grid resistor and a first grid structure are formed on the substrate main body of the inner ring region; the first grid structure is connected with the grid of the first MOS tube;
A second MOS tube, a second grid resistor and a second grid structure are formed on the substrate main body of the outer ring region, and the second grid structure is connected with the grid of the second MOS tube;
the substrate body includes a substrate of a first conductivity type and a homoepitaxial layer formed on the substrate; the epitaxial layers of the inner ring region and the outer ring region are formed with: a base region of a second conductivity type, a source region of a first conductivity type and a body region of the second conductivity type in the base region, and first polysilicon and second polysilicon isolated from each other, wherein the second polysilicon is located above the first polysilicon;
located in the inner ring region: the source region forms a source electrode of the first MOS tube, the substrate is used as a drain electrode of the first MOS tube, and the second polysilicon forms a grid electrode and a first grid electrode structure of the first MOS tube; the first polysilicon outside the cell region forms the first grid resistor, or the first grid resistor is formed by the base region;
Located in the outer ring region: the source region forms a source electrode of the second MOS tube, the substrate is used as a drain electrode of the second MOS tube, and the second polysilicon forms a grid electrode and a second grid electrode structure of the second MOS tube; the first polysilicon forms the second grid resistor, or the second grid resistor is formed by the base region;
Interconnecting metal, so that the anode of the TVS tube is connected with the grid electrode of the first MOS tube through the first grid electrode structure; one end of the first grid resistor is connected with the anode of the TVS tube and the first grid structure, and the other end of the first grid resistor is connected with the source electrode of the first MOS tube; connecting the drain electrode of the first MOS to the cathode of the TVS tube and the drain electrode of the second MOS tube; one end of the second grid resistor is connected with the second grid structure and the source electrode of the first MOS, and the other end of the second grid resistor is connected with the source electrode of the second MOS tube; and connecting the first polysilicon in the cell region with the source electrode of the first MOS tube, and connecting the first polysilicon in the outer ring region with the source electrode of the second MOS tube.
2. The SGT MOS process TVS device of claim 1, wherein said inner ring region termination region surrounds an outer perimeter of said cell region;
the inner ring area terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the trigger area is arranged between the partial pressure inner ring and the partial pressure outer ring.
3. The SGT MOS process TVS device of claim 1, wherein said cell region is centrally located within said inner ring region, said trigger region is located at a side edge of said cell region, and said inner ring terminal region is annular, surrounding said cell region and said trigger region.
4. The SGT MOS process TVS device of claim 1, wherein the trigger region comprises: and forming a first doped region of a first conductivity type and a second doped region of a second conductivity type which are arranged up and down or left and right in the epitaxial layer to form the TVS tube of the PN structure.
5. The SGT MOS process TVS device of claim 1, wherein an annular isolation oxide ring is disposed between said inner ring region and said outer ring region.
6. The SGT MOS process TVS device of claim 1, further comprising an outer ring termination region surrounding the outer ring region, the outer ring termination region comprising a partial pressure inner ring and a partial pressure outer ring, the partial pressure inner ring and the partial pressure outer ring being annular polysilicon pillars.
7. A method for manufacturing a TVS device of an SGT MOS process, comprising:
Providing a substrate body comprising a substrate of a first conductivity type and a homoepitaxial layer formed on the substrate;
Planning an inner ring zone and an outer ring zone, planning an inner ring cell zone, a trigger zone and an inner ring terminal zone in the inner ring zone, and planning an outer ring cell zone in the outer ring zone;
Forming a plurality of trenches in the epitaxial layer;
Forming a first oxide layer to cover the inner wall of the groove and forming first polysilicon in the groove;
removing the first polysilicon at the upper parts of the grooves in the inner ring cell region and the outer ring cell region;
forming a second oxide layer to cover the first polysilicon;
forming second polysilicon on the first polysilicon in the grooves of the inner ring cell region and the outer ring cell region;
forming a base region of a second conductivity type on the whole surface of the epitaxial layer by using an injection and diffusion process;
Forming a first doped region of a first conductivity type and a second doped region of a second conductivity type in the base region of the trigger region by utilizing photoetching, injection and diffusion processes;
Forming a heavily doped source region of a first conductivity type in the inner ring cell region and the outer ring cell region by utilizing photoetching, injection and annealing processes;
forming a surface oxide layer by using a thin film process, and covering the whole epitaxial layer;
Forming a contact hole in the surface oxide layer to expose the epitaxial layer, the first polysilicon and the second polysilicon;
Forming a heavily doped body region of a second conductivity type at the bottom of the contact hole;
forming a front metal in the contact hole and on the surface oxide layer;
Thinning the substrate on the back and forming back metal; the front side metal and the back side metal constitute an interconnect metal;
the first doped region and the second doped region form a TVS tube in the form of a diode;
located in the inner ring region: the source region forms a source electrode of a first MOS tube, the substrate is used as a drain electrode of the first MOS tube, the second polysilicon forms a grid electrode of the first MOS tube and a first grid electrode structure, and the first grid electrode structure is connected with the grid electrode of the first MOS tube; the first polysilicon or the base region outside the inner ring cell region forms a first grid resistor;
Located in the outer ring region: the source region forms a source electrode of a second MOS tube, the substrate is used as a drain electrode of the second MOS tube, the second polysilicon forms a grid electrode of the second MOS tube and a second grid electrode structure, and the second grid electrode structure is connected with the grid electrode of the second MOS tube; the first polysilicon or the base region forms a second grid resistor;
The interconnection metal enables the anode of the TVS tube to be connected with the grid electrode of the first MOS tube through the first grid electrode structure; one end of the first grid resistor is connected with the anode of the TVS tube and the first grid structure, and the other end of the first grid resistor is connected with the source electrode of the first MOS tube; connecting the drain electrode of the first MOS to the cathode of the TVS tube and the drain electrode of the second MOS tube; one end of the second grid resistor is connected with the second grid structure and the source electrode of the first MOS, and the other end of the second grid resistor is connected with the source electrode of the second MOS tube; and connecting the first polysilicon in the inner ring cell region with the source electrode of the first MOS tube, and connecting the first polysilicon in the outer ring region with the source electrode of the second MOS tube.
8. The method of manufacturing a SGT MOS process TVS device of claim 7, wherein said inner ring termination region surrounds an outer perimeter of said cell region;
The inner ring terminal area comprises a partial pressure inner ring and a partial pressure outer ring, and the triggering area is arranged between the partial pressure inner ring and the partial pressure outer ring.
9. The method of manufacturing a SGT MOS process TVS device of claim 7, wherein said cell region is located in the center of said inner ring region, said trigger region is located at one side edge of said cell region, and said inner ring termination region is annular, surrounding said cell region and said trigger region.
10. The method of manufacturing a SGT MOS process TVS device of claim 7, further comprising: an annular isolation oxide ring is formed between the inner ring region and the outer ring region.
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