CN116631858A - Gate structure of trench MOSFET and manufacturing method thereof, trench MOSFET - Google Patents

Abstract

The application discloses a gate structure of a trench MOSFET, a manufacturing method thereof and the trench MOSFET, comprising: forming a trench in the epitaxial layer; forming a shielding gate and a first insulating layer at the lower part of the trench, the first insulating layer isolating the shielding gate and the epitaxial layer from each other; forming a second insulating layer having a protruding upper edge on top of the shield gate; a control gate and a gate dielectric are formed in an upper portion of the trench, the gate dielectric isolating the control gate and the epitaxial layer from each other, a second insulating layer between the control gate and the shield gate, wherein a protruding upper edge of the second insulating layer forms a transition curve between a sidewall and a bottom wall of the control gate corresponding to the upper edge. The application improves the forming step of the control grid to obtain the control grid with the included angle of the bottom wall and the side wall being obtuse angle, thereby reducing the electric field intensity at the bottom of the control grid, reducing the probability of the grid dielectric being broken down in advance and protecting the grid dielectric.

Description

Gate structure of trench MOSFET and manufacturing method thereof, trench MOSFET

technical field

The present application relates to the field of semiconductor technology, in particular to a gate structure of a trench MOSFET, a manufacturing method thereof, and a trench MOSFET.

Background technique

Trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) devices have high input impedance, low drive current, fast switching speed, good high temperature characteristics, etc., and are widely used in the field of power electronics.

In a general manufacturing method of a trench type MOSFET device, the manufacturing method of the control gate includes etching back the oxide layer in the trench to form a groove; depositing polysilicon in the groove; and etching back the polysilicon to form a control gate. In this manufacturing method, the angle between the side wall and the bottom wall of the formed control gate is a right angle, so the electric field intensity in this region is high, which is highly harmful to the gate oxide and may cause premature breakdown.

Contents of the invention

In view of the above problems, the purpose of this application is to provide a trench MOSFET gate structure and its manufacturing method, trench MOSFET, and improve the formation steps of the control gate, so as to obtain the control gate with an obtuse angle between the bottom and the side wall. Gate, thereby reducing the electric field intensity at the bottom of the control gate, reducing the probability of premature breakdown of the gate dielectric, thereby protecting the gate dielectric.

The present application provides a method for manufacturing a trench MOSFET gate structure, including:

forming trenches in the epitaxial layer;

forming a shielding gate and a first insulating layer at the lower part of the trench, the first insulating layer isolating the shielding gate and the epitaxial layer from each other;

forming a second insulating layer with a protruding upper edge on the top of the shielding grid;

A control gate and a gate dielectric are formed on the upper portion of the trench, the gate dielectric isolates the control gate from the epitaxial layer from each other, and the second insulating layer is located between the control gate and the shield gate. between,

Wherein, the protruding upper edge of the second insulating layer makes a transition curved surface corresponding to the upper edge formed between the side wall and the bottom wall of the control gate.

Description of drawings

Through the following description of the embodiments of the application with reference to the accompanying drawings, the above and other purposes, features and advantages of the application will be more clear:

Figure 1 shows a cross-sectional view of a trench MOSFET;

Fig. 2 shows the sectional view of the trench MOSFET of the embodiment of the present application;

Fig. 3a to Fig. 3f show the cross-sectional views of various stages of the manufacturing method of the trench MOSFET device according to the embodiment of the present application.

Detailed ways

In the following figures, the same elements are denoted by similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may refer to being directly on another layer or another region, or between it and Other layers or regions are also included between another layer and another region. Also, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, or region.

If it is to describe the situation directly on another layer or another area, the expression "directly on" or "on and adjacent to" will be used herein.

Unless otherwise specified below, various parts of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors, such as silicon carbide (SiC), etc., II-VI compound semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and Group IV semiconductors, such as silicon (Si), germanium (Ge), etc. The gate conductor can be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN , HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni ₃ Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric can be composed of SiO ₂ or a material with a dielectric constant greater than SiO ₂ , including, for example, oxides, nitrides, oxynitrides, silicates, aluminates, titanates. Also, the gate dielectric may not only be formed of materials known to those skilled in the art, but also materials for gate dielectrics developed in the future may be used.

FIG. 2 shows a cross-sectional view of the trench MOSFET of the first embodiment of the present application. In the present application, the first doping type is one of N-type and P-type, and the second doping type is the other one of N-type and P-type. Implanting N-type dopants, such as P and As, into the semiconductor layer can form the N-type semiconductor layer. Doping a P-type dopant, such as B, into the semiconductor layer can form a P-type semiconductor layer.

The trench MOSFET 100 includes a substrate 101 and an epitaxial layer 111 thereon. The substrate 101 is of a first doping type, which is N-type heavily doped in one embodiment. The epitaxial layer 111 is located on the first surface of the substrate 101 , and the epitaxial layer 111 is lightly doped relative to the substrate 101 .

The trench MOSFET 100 includes a gate structure extending from the upper surface of the epitaxial layer 111 into its interior, the gate structure includes a trench 112 in the epitaxial layer 111, the trench 112 extends from the upper surface of the epitaxial layer 111 to its interior, and terminates In the epitaxial layer 111 : the dielectric layer and the electrode conductor inside the trench 112 , wherein the dielectric layer in the trench 112 includes a first insulating layer 1131 , a gate dielectric 1132 , and a second insulating layer 1133 . The electrode conductors include a shield grid 115 and a control grid 116 . The first insulating layer 1131 and the shielding grid 115 are located at the bottom of the trench 112, and the first insulating layer 1131 isolates the shielding grid 115 from the epitaxial layer 111; the second insulating layer 1133 is located on the top of the shielding grid 115, and the second insulating layer 1133 has Protruding upper edge; the gate dielectric 1132 and the control gate 116 are located on the upper part of the trench 112, the gate dielectric 1132 isolates the control gate 116 and the epitaxial layer 111 from each other, and the second insulating layer 1133 is located between the control gate 116 and the shielding gate 115 , wherein, the protruding upper edge of the second insulating layer 1133 makes a transition curved surface corresponding to the upper edge formed between the sidewall and the bottom wall of the control gate 116 .

Trench MOSFET 100 further includes a body region 118 located on epitaxial layer 111 and adjacent to trench 112 , wherein body region 118 is of the second doping type. A source region 120 of a first doping type is formed in the body region 118; a contact region 119 of a second doping type is formed in the body region 118; a third insulating layer 1134 is formed over the source region 120 and the gate conductor 116 ; Form a conductive channel 121 that penetrates the third insulating layer 1134 and the source region 120 reaches the contact area 119 adjacent to the source region 120; a source electrode 122 is formed above the third insulating layer 1134, and the source electrode 122 passes through the conductive channel 121 Connect to contact area 119 .

In this embodiment, the complete interlayer dielectric layer includes two parts, the second insulating layer 1133 and a part of the gate dielectric layer 1132. For the convenience of description, the part of the gate dielectric layer 1132 located between the control grid 116 and the shielding grid 115 will be hereinafter referred to as The portion located on the upper sidewall of the trench 112 is called the gate dielectric 1132b. In the present application, by improving the formation steps of the second insulating layer 1133, a trench MOSFET with an obtuse angle transition surface at the junction between the bottom wall and the side wall of the gate dielectric 1132b is obtained, that is, the gap between the side wall and the bottom wall is obtained. The included angle between the control gates is an obtuse angle, thereby reducing the electric field intensity at the bottom of the control gate, reducing the probability of premature breakdown of the gate dielectric, thereby protecting the gate dielectric.

3a to 3f show cross-sectional views at various stages of the manufacturing method of the trench MOSFET device according to the first embodiment of the present application. The manufacturing method of the trench MOSFET device provided by the embodiment of the present application will be described below with reference to FIG. 3a to FIG. 3f.

Fig. 3 a shows the initial stage of manufacture of the trench type MOSFET device in the first embodiment of the present application, the cross-sectional view after forming the trench 112, the first insulating layer 1131 and the shield gate 115; as shown in Fig. 3 a, the substrate An epitaxial layer 111 is formed on the bottom 101 , and a trench 112 is formed in the epitaxial layer 111 , and a first insulating layer 1131 , a shielding gate 115 and a second insulating layer 1133 are sequentially formed in the trench 112 .

In this step, an epitaxial layer 111 is formed on the first surface of the semiconductor substrate 101, and the substrate 101 has a first doping type. In an embodiment, the material of the substrate 101 may be an N-type single crystal silicon substrate.

A patterned first mask PR1 is formed on the upper surface of the epitaxial layer 111 , and a trench 112 is formed in the epitaxial layer 111 through the first mask PR1 .

In this step, for example, a deposition process is used to form the first mask PR1, a patterned first mask PR1 is formed by photolithography, and then the epitaxial layer 111 is etched through the patterned first mask PR1, so that the epitaxial layer 111 Trenches 112 are formed in 111 . In one embodiment, etching can be performed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or wet etching. In an embodiment, the first mask PR1 may be a photoresist mask, and after the trench 112 is formed, the first mask PR1 is removed.

Further, a first insulating layer 1131 is formed in the trench 112 .

In one embodiment, the first insulating layer 1131 is formed inside the trench 112 and on the upper surface of the epitaxial layer 111 by means of thermal oxidation or chemical vapor deposition, that is, the first insulating layer 1131 covers the bottom and sides of the trench 112 walls, and the upper surface of the epitaxial layer 111 , the first insulating layer 1131 forms a cavity around the sidewalls of the trench 112 .

In one embodiment, the first insulating layer 1131 may be composed of oxide or nitride, for example, silicon oxide or silicon nitride. Thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO (Selective ReactiveOxidation), chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or subatmospheric pressure chemical vapor deposition SACVD.

Further, the cavity formed around the first insulating layer 1131 is filled with a polysilicon layer, and the polysilicon layer is etched back to form the shielding gate 115 .

In this step, etch back is used to remove the polysilicon layer above the epitaxial layer 111 and above the trench 112 , so that the upper end of the polysilicon layer terminates at the middle of the trench 112 , and the remaining polysilicon layer forms the shield gate 115 . The first insulating layer 1131 isolates the shielding gate 115 from the epitaxial layer 111 . In one embodiment, dry etching may be used for etching back.

In other embodiments, the part of the polysilicon layer above the epitaxial layer 111 may also be removed by chemical mechanical planarization, and then the polysilicon layer in the trench 112 is etched back, so that the upper end of the polysilicon layer terminates at the middle of the trench 112 , forming a shield grid 115 .

Further, the first insulating layer 1131 is etched back. In this step, an etching process is used to remove the first insulating layer 1131 located on the upper surface of the epitaxial layer 111 and the upper part of the trench 112, so that the first insulating layer 1131 is located between the sidewall of the trench 112 and the shielding gate 115, and the second An insulating layer 1131 does not cover the top of the shielding grid 115 . The surface of the first insulating layer 1131 is not lower than the surface of the shielding grid 115; process, reduce light reflection, wet etching can use diluted HF or BOE (Buffered-Oxide-Etch, buffered oxide etching solution), etc.

Further, a second insulating layer 1133 is formed on the upper surface of the first insulating layer 1131 and the upper surface of the shielding gate 115 in the trench.

In this step, the insulating material is deposited by a deposition process and etched back on the insulating material to form a second insulating layer 1133 with a certain thickness, wherein the second insulating layer 1133 covers the upper surface of the first insulating layer 1131 and the shielding gate 115 On the upper surface, the first insulating layer 1131 and the second insulating layer 1133 jointly surround the shielding grid 115 .

In this embodiment, the second insulating layer 1133 is, for example, a silicon oxide layer, and the second insulating layer 1133 isolates the subsequently formed control gate 116 from the shielding gate 115 .

In this embodiment, since the second insulating layer 1133 will be etched back in subsequent steps, the thickness of the second insulating layer 1133 shown in FIG. 3 a is larger than that of the conventional device.

As shown in FIG. 3 b , a sacrificial layer 114 is formed on the upper surface of the second insulating layer 1133 , the upper sidewall of the trench 112 and the upper surface of the epitaxial layer 111 .

In this step, the sacrificial layer 114 is formed by a deposition process, wherein the sacrificial layer 114 covers the upper surface of the second insulating layer 1133 , the upper sidewall of the trench 112 and the upper surface of the epitaxial layer 111 .

In this embodiment, the sacrificial layer 114 is, for example, a silicon nitride layer. In other embodiments, the material of the sacrificial layer 114 may also be other materials that do not react with the etchant of the second insulating layer 1133 .

As shown in FIG. 3 c , the sacrificial layer 114 on the upper surface of the epitaxial layer 111 and part of the upper surface of the second insulating layer 1133 is removed.

In this step, the sacrificial layer 114 on the upper surface of the epitaxial layer 111 and part of the sacrificial layer 114 on the upper surface of the second insulating layer 1133 are removed by etching, leaving only the sacrificial layer 114 on the sidewall of the trench 112 . The lower end of the remaining sacrificial layer 114 is in contact with the surface of the second insulating layer 1133 . In other words, the sacrificial layer 114 forms a cavity around the upper sidewall of the trench 112 and the upper surface of the second insulating layer 1133 , and the sacrificial layer 114 at the bottom of the cavity is removed.

In this embodiment, the etching process is, for example, dry etching.

As shown in FIG. 3 d , the second insulating layer 1133 is etched back using the sacrificial layer 114 as a mask.

In this step, the sacrificial layer 114 is used as a mask, and the surface of the second insulating layer 1133 exposed in the trench 1112 is etched by an etching process to form a groove, and the groove is located in the second insulating layer 1133 . Wherein, when the second insulating layer 1133 is etched, lateral etching and vertical etching are simultaneously performed.

In this embodiment, the etching process is, for example, wet etching. The surface of the second insulating layer 1133 is etched by wet etching, the etched second insulating layer 1133 has a protruding upper edge near the side wall of the trench 112, and the upper surface at the center of the second insulating layer 1133 is in contact with The angle between the projecting upper edges is obtuse. For wet etching, dilute BOE solution (Buffered-Oxide-Etch, buffered oxide etching solution, etc.) can be used.

In other embodiments, the etching process may also be dry etching.

In this embodiment, during the process of etching the surface of the second insulating layer 1133, the ratio of the lateral etching rate to the vertical etching rate is 1:1 to 3:1, and those skilled in the art can For example, adjust the setting of the etching rate.

By controlling the etching time to control the etching process, the etched second insulating layer 1133 has a protruding upper edge, and the groove at the center of the second insulating layer 1133 is not connected to the sidewall of the trench 112 . Further, the thickness of the upper surface of the protruding upper edge of the second insulating layer 1133 is greater than the thickness of the gate dielectric formed in subsequent steps on the sidewall of the trench.

In this embodiment, by controlling the angle at the corner of the groove of the second insulating layer 1133 , the included angle between the side wall and the bottom wall of the control gate formed in subsequent steps can be controlled.

As shown in FIG. 3 e , the sacrificial layer 114 is removed, and a gate dielectric 1132 is formed on the trench 112 .

In this step, the gate dielectric 1132 is formed by a deposition process, wherein the gate dielectric 1132 covers the upper surface of the second insulating layer 1133, the upper sidewall of the trench 112 and the upper surface of the epitaxial layer, and the gate dielectric 1132 surrounds the trench. The upper sidewall of the groove 112 and the upper surface of the second insulating layer 1133 form a cavity.

Referring to FIG. 3 e , the first distance L1 is, for example, the thickness at the upper surface of the protruding upper edge formed after the second insulating layer 1133 is etched; the second distance L2 is, for example, the thickness of the gate dielectric 1132 on the sidewall of the trench 112 . In this embodiment, the first distance L1 is greater than the second distance L2. Further, since the first distance L1 is greater than the second distance L2, the portion of the gate dielectric 1132 located at the angle between the side wall and the bottom wall will protrude toward the cavity, as shown in the dotted line box in FIG. 3e shown in .

In this embodiment, the first distance L1 is greater than the second distance L2. On the one hand, it can reduce the breakdown probability of the gate dielectric 1132 at the bottom corner of the control gate, and on the other hand, it is more conducive to forming an obtuse transition surface.

In this embodiment, the gate dielectric 1132 is located at the part of the angle between the side wall and the bottom wall that protrudes toward the cavity, which further increases the angle between the side wall and the bottom wall of the control gate 116 formed later. The distance between the sidewall of the trench and the trench further reduces the electric field intensity at the bottom of the control gate 116 , prevents premature breakdown, and protects the gate dielectric 1132 .

In this embodiment, the gate dielectric 1132 is, for example, a silicon oxide layer, and the gate dielectric 1132 isolates the subsequently formed control gate 116 from the epitaxial layer 111 .

In this embodiment, the gate dielectric 1132 is a conformal layer, so the angle between the sidewall and the bottom wall of the gate dielectric 1132 retains the angle between the sidewall and the bottom wall of the second insulating layer 1133. shape, so that the angle between the sidewall and the bottom wall of the gate dielectric 1132 is also an obtuse angle. In subsequent steps, the control gate 116 is deposited in the cavity formed by the gate dielectric 1132 around the upper sidewall of the trench 112 and the upper surface of the second insulating layer 1133, so the angle between the sidewall and the bottom wall of the control gate 116 Also an obtuse angle.

In this embodiment, by controlling the etching speed of the surface of the second insulating layer 1133 , the angle between the sidewall and the bottom wall of the control gate 116 is, for example, about 125°. Further, the included angle between the sidewall and the bottom wall of the second insulating layer 1133 and the included angle between the sidewall and the bottom wall of the gate dielectric 1132 are, for example, about 125°.

In this embodiment, the gate dielectric 1132 includes two parts, one part of the gate dielectric 1132a is located on the upper sidewall of the trench 112 for isolating the control gate 116 and the epitaxial layer 111, and the other part of the gate dielectric 1132b is located on the second insulating layer 1133 The upper surface will be used to isolate the shielding grid 115 and the control grid 116 later, so different reference numerals are used to distinguish the gate dielectric 1132 in different regions. In this embodiment, the second insulating layer 1133 and the gate dielectric 1132 b jointly form an interlayer dielectric layer, and the interlayer dielectric layer is used to isolate the shielding gate 115 and the control gate 116 .

As shown in FIG. 3f, the control gate 116 is formed in the trench 112, the body region 118 and the source region 120 are formed in the epitaxial layer 111, the third insulating layer 1134 is formed on the upper surface of the epitaxial layer 111, and the third insulating layer 1134 is formed. And reach the conductive channel 121 of the contact region 119 , and form the source electrode 122 on the surface of the third insulating layer 1134 .

In this step, a polysilicon layer is deposited in the cavity formed by the gate dielectric 1132 around the upper sidewall of the trench 112 and the upper surface of the second insulating layer 1133 by a deposition process to form the control gate 116 .

Further, different ions are implanted into the upper portion of the epitaxial layer 111 by an ion implantation process to form the body region 118 and the source region 120 . In this embodiment, the body region 118 is of the second doping type, wherein the second doping type is opposite to the first doping type. A photoresist mask is used to define the region of the body region 118, and the first ion implantation is performed in the region defined by the photoresist mask to form the body region 118 in the epitaxial layer 111 adjacent to the trench 112, The photoresist mask is removed after the body regions 118 are formed. A region of the source region 120 is defined by a photoresist mask, and a second ion implantation is performed in the region defined by the photoresist mask to form a source region 120 of the first doping type in the body region 118 . By controlling the ion implantation parameters, such as implantation energy and dose, the desired depth and doping concentration can be achieved. The depth of the body region 118 does not exceed the extension depth of the control gate 116 in the trench 112 . The body region 118 and the source region 120 are respectively adjacent to the trench 112 , and the control gate 116 is isolated from the body region 118 and the source region 120 by the gate dielectric 1132 .

Further, a third insulating layer 1134 is formed on the upper surface of the epitaxial layer 111 and the upper surface of the control gate 116 .

In this step, the third insulating layer 1134 located on the upper surface of the epitaxial layer 111 and the upper surface of the control gate 116 is formed through a deposition process, and chemical mechanical planarization is further performed to obtain a flat surface. The third insulating layer 1134 covers top surfaces of the epitaxial layer 111 and the control gate 116 .

In this embodiment, the third insulating layer 1134 is, for example, borophosphosilicate glass.

Further, a contact hole extending through the third insulating layer 1134 and the source region 120 and extending to the inside of the body region 118 is formed.

In this step, for example, a deposition process is used to form a second mask PR2 on the third insulating layer 1134, a patterned second mask PR2 is formed by photolithography, and then the source region 120 and The body region 118 is etched to form a contact hole. The contact hole extends from the upper surface of the third insulating layer 1134 toward the substrate 101 , passes through the third insulating layer 1134 and the source region 120 , and stops inside the body region 118 . In one embodiment, etching can be performed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or wet etching. In an embodiment, the second mask PR2 may be a photoresist mask, and the second mask PR2 is removed after the contact hole is formed.

Further, a contact region 119 of the second doping type is formed in the body region 118 .

In this step, a single ion implantation is performed on the body region 118 through the contact hole, and a contact region 119 of the second doping type is formed in the body region 118 .

In this embodiment, since the contact hole extends into the body region 118, in the process of forming the contact region 119 by performing ion implantation through the contact hole, ions can be directly implanted into the body region 118, compared with the process of performing ion implantation from the upper surface of the source region 120. For ion implantation, this embodiment shortens the time for ion implantation.

Further, a conductive channel 121 and a source electrode 122 are formed.

In this step, a metal layer is formed by a deposition process, and the metal layer covers the third insulating layer 1134 and fills the contact hole to be in contact with the contact region 119 . In this embodiment, the portion of the metal layer filled in the contact hole forms the conductive channel 120 , and the portion of the metal layer located on the upper surface of the third insulating layer 1134 forms the source electrode 122 . The conductive channel 120 extends to the contact area 119 .

In the present application, by improving the step of forming the second insulating layer, the corner angle at the connection between the second insulating layer and the gate dielectric is an obtuse angle, so that the angle between the side wall and the bottom wall of the control gate is also The obtuse angle reduces the electric field intensity at the bottom of the control gate, prevents premature breakdown, and protects the gate dielectric.

Embodiments according to the present application are described above, which do not describe all details in detail, nor do they limit the invention to the specific embodiments described. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application.

Claims (10)

1. A method for manufacturing a gate structure of a trench type MOSFET, comprising: forming trenches in the epitaxial layer; forming a shielding gate and a first insulating layer at the lower part of the trench, the first insulating layer isolating the shielding gate and the epitaxial layer from each other; forming a second insulating layer with a protruding upper edge on the top of the shielding grid; A control gate and a gate dielectric are formed on the upper portion of the trench, the gate dielectric isolates the control gate from the epitaxial layer from each other, and the second insulating layer is located between the control gate and the shield gate. between, Wherein, the protruding upper edge of the second insulating layer makes a transition curved surface corresponding to the upper edge formed between the side wall and the bottom wall of the control gate. 2. The gate structure manufacturing method according to claim 1, wherein the second insulating layer is etched such that the upper surface at the center of the second insulating layer is in contact with the protruding upper edge of the second insulating layer The angle between them is an obtuse angle. 3. The gate structure manufacturing method according to claim 2, wherein the step of forming a control gate and a gate dielectric on the upper portion of the trench comprises: A gate dielectric is formed above the second insulating layer, the gate dielectric forms a cavity around the sidewall of the trench and the second insulating layer, and a cavity is formed between the sidewall and the bottom wall of the gate dielectric. forming a transition curved surface corresponding to the second insulating layer; forming the control gate in the cavity, Wherein, the transition curved surface between the side wall and the bottom wall of the control grid is an obtuse angle. 4. The gate structure manufacturing method according to claim 3, wherein the protruding upper edge of the second insulating layer makes the transition curved surface between the side wall and the bottom wall of the gate dielectric have a protrusion toward the control gate , and the transition curved surface of the side wall and the bottom wall of the control grid has a concave towards the inside of the control grid. 5. The gate structure manufacturing method according to claim 1, wherein the step of forming a second insulating layer on the top of the shield gate comprises: depositing an insulating material on top of the shield gate in the trench; Etching back the insulating material in the trench to obtain a second insulating layer with a certain thickness; forming a sacrificial layer over the second insulating layer in the trench and sidewalls of the trench, the sacrificial layer forming a cavity along the second insulating layer and the trench; removing the sacrificial layer at the bottom of the cavity; and The second insulating layer is etched using the remaining sacrificial layer as a mask to obtain a second insulating layer having a protruding upper edge at the sidewall of the trench. 6. The gate structure manufacturing method according to claim 5, wherein in the step of etching the second insulating layer using the remaining sacrificial layer as a mask, the second insulating layer is simultaneously etching and vertical etching. 7. The gate structure manufacturing method according to claim 6, wherein the ratio of the lateral etching rate to the vertical etching rate is 1:1 to 3:1. 8. The gate structure manufacturing method according to claim 1, wherein the thickness of the protruding upper edge surface of the second insulating layer is a first distance, and the thickness of the gate dielectric at the sidewall of the trench is is a second distance, and the first distance is greater than the second distance. 9. A gate structure of a trench MOSFET, comprising: trenches in the epitaxial layer; A first insulating layer and a shielding gate located at the lower part of the trench, the first insulating layer isolating the shielding gate and the epitaxial layer from each other; a second insulating layer on top of the shielding grid, the second insulating layer having a protruding upper edge; a gate dielectric and a control gate located on the upper part of the trench, the gate dielectric isolates the control gate from the epitaxial layer from each other, the second insulating layer is located between the control gate and the shielding gate, Wherein, the protruding upper edge of the second insulating layer makes a transition curved surface corresponding to the upper edge formed between the side wall and the bottom wall of the control gate. 10. A trench MOSFET comprising: Substrate; an epitaxial layer, located on the upper surface of the substrate, The gate structure according to any one of claims 1-8, located in the epitaxial layer, extending from the upper surface of the epitaxial layer into its interior; IA23000128 a body region, a source region and a contact region in said epitaxial layer; a third insulating layer located on a surface of the epitaxial layer away from the substrate; a conductive channel passing through the third insulating layer and extending to a contact region in the epitaxial layer; A source electrode is located on the third insulating layer and electrically connected to the conductive channel.