CN116230515A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing an epitaxial layer; forming a gate dielectric layer and a gate conductor, wherein the gate conductor and the epitaxial layer are isolated through the gate dielectric layer; forming a body region inside the epitaxial layer; forming a contact region and a source region inside the body region; and forming a conductive path through the source region and the contact region to the body region; the bottom of the conductive channel is positioned in the body region, and the side wall is in contact with the contact region and the source region. The present application extends the conductive via into the body region, thereby reducing reverse recovery charge.

Description

A kind of semiconductor device and its manufacturing method

technical field

The present application relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

The semiconductor device is, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). As shown in FIG. The metal layer 23 on the second surface of the semiconductor substrate 11 . A trench 12a is formed in the epitaxial layer 12 . There is a first conductor 15 and a second conductor 16 in the trench 12a, the first conductor 15 is located in the lower half of the trench, the second conductor 16 is located in the upper half of the trench, between the first conductor 15 and the second conductor 16 It has a second dielectric layer 17 . The first conductor 15 is isolated from the epitaxial layer 12 by the first dielectric layer 13 , and the second conductor 16 is isolated from the epitaxial layer 12 by the third dielectric layer 14 .

The epitaxial layer 12 has a body region 18 (Pwell) adjacent to the trench 12a. The body region 18 is of the second conductivity type, and above the body region 18 is a heavily doped region 19 (P+) of the second conductivity type. The second conductor 16 is isolated from the body region 18 by the third dielectric layer 14 . Above the body region 18 is a heavily doped source region 20 of the first conductivity type, and a conductive channel 21 is formed in the source region 20 and the heavily doped region 19 . The bottom of the conductive channel 21 is located in the heavily doped region 19 .

Among them, the heavily doped region 19 (P+), the body region 18 (Pwell) and the epitaxial layer 12 (N-epi) form a body diode, and the large injection of carriers from the body region 18 to the epitaxial layer 12 will lead to reverse recovery In the process, there is a large turn-off time and turn-off loss.

Contents of the invention

In view of the above problems, the purpose of this application is to provide a semiconductor device and its manufacturing method, which extends the conductive channel to the inside of the body region, thereby reducing the reverse recovery charge, reducing the turn-off time and turn-off loss.

The first aspect of the present application provides a method for preparing a semiconductor structure, including:

providing an epitaxial layer;

forming a gate dielectric layer and a gate conductor, the gate conductor and the epitaxial layer are separated by the gate dielectric layer;

forming a body region within the epitaxial layer;

forming a contact region and a source region inside the body region; and

forming a conductive path through the source region and the contact region to the body region;

Wherein, the bottom of the conductive channel is located inside the body region, and the sidewall is in contact with the contact region and the source region.

The second aspect of the present application provides a trench MOSFET, which includes:

an epitaxial layer of a first doping type;

a gate dielectric layer and a gate conductor, the gate conductor and the epitaxial layer are separated by the gate dielectric layer;

a body region located within the epitaxial layer and adjacent to the trench;

a contact region and a source region located inside the body region; and

a conductive path through the source region and the contact region to the body region;

Wherein, the bottom of the conductive channel is located inside the body region, and the sidewall is in contact with the contact region and the source region.

Description of drawings

Through the following description of the embodiments of the application with reference to the accompanying drawings, the above and other purposes, features and advantages of the application will be more clear:

Figure 1 shows a cross-sectional view of a semiconductor device;

2 shows a cross-sectional view of a semiconductor device according to a first embodiment of the present application;

3a to 3i show cross-sectional views of various stages of the manufacturing method of the semiconductor device according to the first embodiment of the present application;

FIG. 4 shows a cross-sectional view of a semiconductor device according to a second embodiment of the present application.

Detailed ways

In the following figures, the same elements are denoted by similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may refer to being directly on another layer or another region, or between it and Other layers or regions are also included between another layer and another region. Also, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, or region.

If it is to describe the situation directly on another layer or another area, the expression "directly on" or "on and adjacent to" will be used herein.

Unless otherwise specified below, various parts of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors, such as silicon carbide (SiC), etc., II-VI compound semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and Group IV semiconductors, such as silicon (Si), germanium (Ge), etc. The gate conductor can be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN , HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni ₃ Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric layer may be made of SiO ₂ or a material with a dielectric constant greater than SiO ₂ , such as oxide, nitride, oxynitride, silicate, aluminate, titanate. Moreover, the gate dielectric layer may not only be formed of materials known to those skilled in the art, but also materials developed for the gate dielectric layer in the future may be used.

In the present application, the first doping type is one of N-type and P-type, and the second doping type is the other one of N-type and P-type. Implanting N-type dopants, such as P and As, into the semiconductor layer can form the N-type semiconductor layer. Doping a P-type dopant, such as B, into the semiconductor layer can form a P-type semiconductor layer.

FIG. 2 is a cross-sectional view of a semiconductor device according to a first embodiment of the present application. As shown in FIG. 2 , in this embodiment, the semiconductor device is a trench MOSFET (trench metal oxide semiconductor field effect transistor).

The semiconductor device 100 includes a substrate 101 and an epitaxial layer 111 thereon. The substrate 101 is of a first doping type, which is N-type heavily doped in one embodiment. The epitaxial layer 111 is located on the first surface of the substrate 101 , and the epitaxial layer 111 is lightly doped relative to the substrate 101 . A drain electrode 124 is formed on the second surface of the substrate 101 .

The semiconductor device 100 includes a trench 112 extending from the upper surface of the epitaxial layer 111 into its interior; a dielectric layer and an electrode conductor located inside the trench 112; a body region 119 located at the epitaxial layer 111 and adjacent to the trench 112, wherein the body Region 119 is of the second doping type. The trench 112 extends from the upper surface of the epitaxial layer 111 to the inside thereof, terminating in the epitaxial layer 111 .

The dielectric layers in the trench 112 include a first dielectric layer 1131 , a second dielectric layer 1132 and a third dielectric layer 1133 . The electrode conductors include a first conductor 115 and a second conductor 118 . The first dielectric layer 1131 covers the inner surface of the lower part of the trench 112 , and the first conductor 115 is located in a cavity formed by the first dielectric layer 1131 around the lower part of the trench. The first conductor 115 is isolated from the epitaxial layer 111 by the first dielectric layer 1131 . The second dielectric layer 1132 covers the upper surfaces of the first conductor 115 and the first dielectric layer 1131 and the inner surface of the middle part of the trench 112 . The third dielectric layer 1133 covers the upper inner surface of the trench, the second conductor 118 is isolated from the first conductor 115 by the second dielectric layer 1132 , and the second conductor 118 is isolated from the epitaxial layer 111 by the third dielectric layer 1133 .

In this embodiment, the first conductor 115 is a shield conductor, the second conductor 118 is a gate conductor, the third dielectric layer 1133 is a gate dielectric layer, and the second dielectric layer 1132 isolates the shield conductor and the gate conductor.

The semiconductor device 100 includes a source region 121 of a first doping type formed in the body region 119; a contact region 120 of a second doping type formed in the body region 119; a contact region 120 formed over the source region 121 and the gate conductor 118 The interlayer dielectric layer 122; the conductive channel 125 penetrating the interlayer dielectric layer 122, the source region 121 and the contact region 120 to the body region 119 is formed adjacent to the source region 121; the source electrode 123 formed above the interlayer dielectric layer 122 , the source electrode 123 is connected to the body region 119 via the conductive via 125 . Wherein, the interlayer dielectric layer 122 may be an oxide layer with a certain thickness, for example, silicon oxide.

In this embodiment, the sidewall of the conductive channel 125 is in contact with the contact region 120 and the source region 121 , and the bottom is located in the body region 119 with a lower doping concentration. In this embodiment, extending the conductive channel 125 to the inside of the body region 119 is equivalent to reducing the concentration of the P region of the body diode, and reducing the injection level of carriers (holes) from the P region to the N region (N-type epitaxial layer 111). , in its reverse recovery process, that is, the number of carriers stored in the N region (N-type epitaxial layer 111) is reduced, thereby reducing the reverse recovery charge (Qrr), further reducing the short-time and turn-off time of the diode loss. In addition, the rate of change of current (di/dt) is reduced, further reducing VDS peak stress.

3a to 3i show cross-sectional views of various stages of the manufacturing method of the semiconductor device according to the first embodiment of the present application.

As shown in FIG. 3 a , an epitaxial layer 111 is formed on a substrate 101 , and a trench 112 is formed in the epitaxial layer 111 .

In this step, an epitaxial layer 111 is formed on a semiconductor substrate 101, and the substrate 101 is used as a drain region of the device and has a first doping type. In an embodiment, the material of the substrate 101 may be a single crystal silicon substrate doped to N-type. Trenches 112 are formed in the epitaxial layer 111 by photolithography and etching processes.

As shown in FIG. 3 b , a first dielectric layer 1131 and a polysilicon layer 1141 are sequentially formed in the trench 112 .

In one embodiment, the first dielectric layer 1131 is formed inside the trench 112 and on the upper surface of the epitaxial layer 111 by means of thermal oxidation or chemical vapor deposition, that is, the first dielectric layer 1131 covers the bottom of the trench 112 and the sides wall, and the upper surface of the epitaxial layer 111. In an embodiment, the first dielectric layer 1131 may be composed of oxide or nitride, for example, silicon oxide or silicon nitride. Thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO (Selective ReactiveOxidation), chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or subatmospheric pressure chemical vapor deposition SACVD.

A polysilicon layer 1141 is formed inside the trench 112 and on the surface of the first dielectric layer 1131 above the epitaxial layer 111 by means of low pressure chemical vapor deposition. The first dielectric layer 1131 isolates the polysilicon layer 1141 from the epitaxial layer 111 .

As shown in FIG. 3c, the first dielectric layer 1131 and the polysilicon layer 1141 are etched back.

In this step, the polysilicon layer 1141 is chemically mechanically polished, and then the polysilicon layer 1141 is etched back, so that the surface of the first dielectric layer 1131 above the epitaxial layer 111 and the polysilicon layer 1141 on the upper part of the trench 112 are removed, and the remaining polysilicon layer 1141 Part becomes the first conductor 115 . In one embodiment, dry etching may be used for etching back.

Using an etching process, etch the first dielectric layer 1131 to remove the first dielectric layer 1131 located on the upper surface of the epitaxial layer 111 and the upper part of the trench 112, so that the first dielectric layer 1131 is located between the side wall of the trench 112 and the first conductor 115 space, and the first dielectric layer 1131 does not cover the top of the first conductor 115 . The surface of the first dielectric layer 1131 is lower than that of the first conductor 115; process, reduce light reflection, wet etching can use diluted HF or BOE (Buffered-Oxide-Etch, buffered oxide etching solution), etc.

As shown in FIG. 3d, a second dielectric layer 1132 is formed.

A conformal second dielectric layer is formed on top of the first conductor 115 and the first dielectric layer 1131 in the trench 112 respectively by plasma enhanced chemical vapor deposition. The second dielectric layer covers the tops of the first conductor 115 and the first dielectric layer 1131 , the upper sidewall of the trench 112 and the upper surface of the epitaxial layer 111 . The second dielectric layer may be composed of oxide or nitride, for example, silicon oxide or silicon nitride.

The second dielectric layer on the upper surface of the epitaxial layer 111 is removed by a chemical mechanical polishing process, and then the second dielectric layer in the trench 112 is etched back with a BOE (Buffered-Oxide-Etch) solution, so that the A certain thickness of the second dielectric layer 1132 remains on top of the first conductor 115 and the first dielectric layer 1131 in the trench 112 .

As shown in FIG. 3e, a third dielectric layer 1133 and a polysilicon layer 1142 are formed.

In this step, for example, a thermal oxidation technique is used to form an oxide layer located on the second dielectric layer 1132, the side walls of the trench on the second dielectric layer 1132 and the upper surface of the epitaxial layer 111. The oxide layer is the gate dielectric layer 1133, and the trench The sidewall of the groove 112 is covered by the gate dielectric layer 1133 . The thermal oxidation technology generally involves a chemical reaction between silicon and a gas containing oxidizing substances, such as water vapor and oxygen, at high temperature to form a dense silicon dioxide (SiO ₂ ) film on the surface of the silicon wafer.

The polysilicon layer 1142 is filled in the trench 112 covered with the gate dielectric layer 1133 by means of low pressure chemical vapor deposition. The polysilicon layer 1142 includes a first portion 1142 a located in the trench 112 and a second portion 1142 b located above the epitaxial layer 111 .

As shown in Figure 3f, a second conductor 118 is formed.

In this step, the second portion 1142b of the polysilicon layer 1142 above the epitaxial layer 111 is removed by etching back or chemical mechanical planarization, so that the upper end of the polysilicon layer 1142 terminates at the opening of the trench, and the upper surface of the polysilicon layer 1142 Level with the upper surface of the epitaxial layer 111 , a second conductor 118 is formed.

The second dielectric layer 1132 insulates the first conductor 115 and the second conductor 118 from each other, and the second dielectric layer 1132 has a certain mass and thickness to support potential differences that may exist between the first conductor 115 and the second conductor 118 .

As shown in FIG. 3 g , a body region 119 , a contact region 120 and a source region 121 are formed in a region of the epitaxial layer 111 adjacent to the trench 112 .

The body region 119 of the second doping type is formed by photolithography and the first ion implantation. Specifically, for example, a deposition process is used to form a first mask over the epitaxial layer 111 and the second conductor 118, a photolithography process is used to form a first opening on the first mask, and then the first opening is formed through the first mask. The first ion implantation. In an embodiment, the first mask may be a photoresist mask, and after the body region 119 is formed, the first mask is removed.

By controlling the width of the first opening on the first mask, the lateral dimension of the body region 119 is controlled. In this embodiment, the body region 119 is adjacent to the trench 112 and is isolated from the second conductor 118 by the third dielectric layer 1133 . By controlling the parameters of ion implantation, such as implantation energy and dose, the required depth and doping concentration can be achieved. In this embodiment, the depth of the body region 119 does not exceed the depth of the second conductor 118 in the trench 112. Extension depth.

A contact region 120 of the second doping type is formed in the body region 119 by using a photolithography process and a second ion implantation. Specifically, for example, a deposition process is used to form a second mask over the epitaxial layer 111 and the second conductor 118, and photolithography is performed on the second mask to form a second opening on the second mask, and then through the second mask The second opening for the second ion implantation. In an embodiment, the second mask may be a photoresist mask, and after the contact region 120 is formed, the second mask is removed.

By controlling the width and position of the second opening on the second mask, the lateral size of the contact region 120 is controlled. In this embodiment, the width of the contact region 120 is smaller than the width of the body region 119 and has a certain distance from the trench 112 . By controlling the parameters of ion implantation, such as implantation energy and dose, the required depth and the required doping concentration can be achieved, wherein the depth of the contact region 120 does not exceed the depth of the body region 119, and the doping concentration of the contact region 120 greater than the doping concentration of the body region 119 .

A source region 121 of the first doping type is formed in the body region 119 by photolithography and the third ion implantation. Specifically, for example, a deposition process is used to form a third mask over the epitaxial layer 111 and the second conductor 118, a photolithography process is used to form a third opening on the third mask, and then the process is performed through the third opening on the third mask. The third ion implantation. In an embodiment, the third mask may be a photoresist mask, and after the source region 121 is formed, the third mask is removed.

By controlling the width of the third opening on the third mask, the lateral size of the source region 121 is controlled. In this embodiment, the width of the source region 121 is equal to the width of the body region 119, and the source region 121 is adjacent to the trench 112. The third dielectric layer 1133 is isolated from the second conductor 118 . By controlling the parameters of ion implantation, such as implantation energy and dose, the desired depth and doping concentration can be achieved, wherein the depth of the source region 121 does not exceed the depth of the contact region 120 .

As shown in FIG. 3 h , an interlayer dielectric layer 122 located above the source region 121 is formed.

Through a deposition process, an interlayer dielectric layer 122 located above the source region 121 is formed, and chemical mechanical planarization is further performed to obtain a flat surface. The interlayer dielectric layer 122 covers the source region 121 and the top surface of the second conductor 118, and the part of the third dielectric layer 1133 above the epitaxial layer 111 may be removed by etching after the source region 121 is formed, or may not be removed. The interlayer dielectric layer 122 is conformal and located above the source region 121 .

As shown in Fig. 3i, conductive vias 125 are formed.

Form a fourth mask above the interlayer dielectric layer 122, perform photolithography on the fourth mask, and form a fourth opening on the second mask; through the fourth opening, the interlayer dielectric layer and the epitaxial Layer is etched to form a contact hole 125 a penetrating through the interlayer dielectric layer 122 , the source region 121 and the contact region 120 and reaching the body region 119 . A conductive material is filled in the contact hole 125 a to form a conductive channel 125 . Wherein, the bottom of the conductive channel 125 is located inside the body region 119 , and the sidewall of the conductive channel 125 is in contact with the contact region 120 .

Next, a source electrode 123 is formed on the interlayer dielectric layer 122 through a deposition process, and a drain electrode 124 is formed on the second surface of the substrate 101 through a deposition process, and the semiconductor device 100 shown in FIG. 2 is obtained. The source electrode 123 is connected to the body region 119 via a conductive via 125 .

In the present application, the source electrode 123, the second conductor (gate conductor) 118, the first conductor (shielding conductor) 114, and the drain electrode 124 can be formed of conductive materials, in one embodiment, aluminum alloy or metal materials such as copper.

In the semiconductor device and its manufacturing method provided by the present application, the contact region 120 is formed at the same time as the body region 119 and the source region 121 are formed. After the contact hole is formed, ion implantation is not required to form the contact region 120 . The contact region 120 is formed by performing ion implantation in the hole. The method in this application can extend the conductive channel to the body region, and can effectively reduce the reverse recovery charge of the diode without adding process steps.

Further, the mask for forming the contact region 120 can follow the original process for forming the mask for the contact hole, without additional design and fabrication of the mask, and no additional cost will be added.

FIG. 4 shows a schematic structural diagram of a semiconductor device according to the second embodiment of the present application. As shown in FIG. 4, the semiconductor device 200 includes a substrate 201 and an epitaxial layer 211 thereon, and the substrate 201 is of the first doping type, In one embodiment, it is N-type heavily doped. The epitaxial layer 211 is located on the first surface of the substrate 201 , and the epitaxial layer 211 is lightly doped relative to the substrate 201 . A drain electrode 224 is formed on the second surface of the substrate 201 .

The semiconductor device 200 includes a gate conductor 218 and a gate dielectric layer 2133, the gate conductor 218 is located above the epitaxial layer 211, and the gate dielectric layer 2133 is located between the gate conductor 218 and the epitaxial layer 211 to isolate the gate conductor 218 from the epitaxial layer 211 .

The semiconductor device 200 includes a body region 219 of the second doping type formed in the epitaxial layer 211, a contact region 220 of the second doping type formed in the body region 219, a contact region 220 of the first doping type formed in the body region 219 The source region 221, the interlayer dielectric layer 222 formed above the source region 221 and the gate conductor 218; The conductive channel 225 ; the source electrode 223 formed on the interlayer dielectric layer 222 , the source electrode 223 is connected to the body region 219 through the conductive channel 225 .

Wherein, in this embodiment, the method for forming the body region, the source region, the drain region, and the conductive channel is the same as that of the first embodiment, and will not be repeated in this embodiment.

It should be noted that in this application, the semiconductor device may also be a SiC MOSFET.

Embodiments according to the present application are described above, which do not describe all details in detail, nor do they limit the invention to the specific embodiments described. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. This application is to be limited only by the claims, along with their full scope and equivalents.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:

providing an epitaxial layer;

forming a gate dielectric layer and a gate conductor, wherein the gate conductor and the epitaxial layer are isolated through the gate dielectric layer;

forming a body region inside the epitaxial layer;

forming a contact region and a source region inside the body region; and

forming a conductive channel through the source region and the contact region to the body region;

the bottom of the conductive channel is positioned in the body region, and the side wall is in contact with the contact region and the source region.

2. The method of claim 1, wherein forming the contact region comprises:

forming a second mask over the epitaxial layer and the gate conductor;

photoetching the second mask, and forming a second opening on the second mask;

and performing ion implantation on the body region through the second opening of the second mask to form the contact region.

3. The method of claim 2, wherein the width of the contact region is smaller than the width of the body region by controlling the width and position of the second opening.

4. The method of claim 2, wherein the doping concentration of the contact region is greater than the doping concentration of the body region by controlling parameters of ion implantation such that the depth of the contact region does not exceed the depth of the body region.

5. The method of claim 2, wherein forming the conductive via comprises:

forming a fourth mask over the epitaxial layer and the gate conductor;

photoetching the fourth mask, and forming a fourth opening on the second mask;

etching the epitaxial layer through the fourth opening to form a contact hole penetrating through the source region and the contact region and reaching the body region; and

and filling conductive materials in the contact holes to form the conductive channels.

6. The method of claim 5, wherein forming the second opening on the second mask and forming the second opening on the fourth mask uses the same reticle.

7. A trench MOSFET, comprising:

an epitaxial layer of a first doping type;

the grid electrode conductor is isolated from the epitaxial layer through the grid dielectric layer;

a body region located inside the epitaxial layer and adjacent to the trench;

a contact region and a source region located inside the body region; and

a conductive path through the source region and the contact region to the body region;

the bottom of the conductive channel is positioned in the body region, and the side wall is in contact with the contact region and the source region.

8. The trench MOSFET of claim 9, wherein a width of the contact region is less than a width of the body region.

9. The trench MOSFET of claim 9, wherein a depth of the contact region does not exceed a depth of the body region, a doping concentration of the contact region being greater than a doping concentration of the body region.

10. The trench MOSFET of claim 9, wherein the gate dielectric layer is over the epitaxial layer, and the gate conductor is over the gate dielectric layer and isolated from the epitaxial layer by the gate dielectric layer.

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