CN116581963A - Error amplifier for improving DC-DC transient response - Google Patents
Error amplifier for improving DC-DC transient response Download PDFInfo
- Publication number
- CN116581963A CN116581963A CN202310856265.0A CN202310856265A CN116581963A CN 116581963 A CN116581963 A CN 116581963A CN 202310856265 A CN202310856265 A CN 202310856265A CN 116581963 A CN116581963 A CN 116581963A
- Authority
- CN
- China
- Prior art keywords
- twenty
- pmos
- tube
- nmos
- thirty
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/1566—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention relates to an error amplifier for improving DC-DC transient response, and belongs to the technical field of circuits. The error amplifier comprises an error amplifying circuit and a transient compensation circuit, wherein the transient compensation circuit is used for providing transient response compensation current to the output end of the error amplifying circuit when the output voltage of the error amplifying circuit drops sharply and the feedback voltage is lower than the reference voltage. Therefore, the current at the output end of the error amplifier is larger than the injection current of the traditional operational amplifier, the output voltage of the error amplifier can be raised faster, the larger the voltage of the error amplifier is, the larger the corresponding inductance peak current is, so that more current can be provided for output faster, and the output voltage can be raised to a set value in a shorter time.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to the technical field of error amplifiers, and specifically relates to an error amplifier for improving DC-DC transient response.
Background
In a conventional peak current mode direct current to direct current (DC-DC) circuit, when a load current suddenly jumps from a light load to a heavy load, in order to meet the output of the heavy load current, the output voltage of the error amplifier EA needs to rise from low to high to reach a value corresponding to the heavy load current. The faster the error amplifier output voltage rises, the better the DC-DC transient response. The circuit structure of the conventional error amplifier is shown in fig. 1, and the rising speed of the output value of the conventional error amplifier depends on the tail current of the error amplifier, the transconductance gm of the differential input pair transistor and the compensation capacitor C of the error amplifier. The tail current of the error amplifier, the transconductance gm of the differential input pair and the compensation capacitance C have typically been determined based on system stability considerations, so that there is limited space to optimize the transient response.
Therefore, how to provide an error amplifier that can rapidly provide transient response when the load current suddenly jumps from light load to heavy load is a problem in the art.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides the error amplifier which can accelerate the rising speed of the output voltage of the error amplifier and reach the corresponding value of the load current more quickly when the load current jumps from low to high, thereby improving the transient response speed of the system.
In order to achieve the above object, an error amplifier for improving a DC-DC transient response of the present invention has the following constitution:
the error amplifier comprises an error amplifying circuit and a transient compensation circuit, wherein the error amplifying circuit is used for generating output voltage according to feedback voltage and reference voltage; the transient compensation circuit is used for providing transient response compensation current for the output end of the error amplification circuit when the output voltage of the error amplification circuit drops sharply so that the feedback voltage is lower than the reference voltage.
In the error amplifier for improving DC-DC transient response, the error amplifying circuit comprises: the width-to-length ratios of the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5, the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3 and the fourth NMOS tube MN4 are respectively and correspondingly equal; the sources of the first, fourth and fifth PMOS transistors MP1, MP4 and MP5 are all connected to the power supply voltage VDD, the gate of the first PMOS transistor MP1 is connected to the bias voltage VBP, the drain of the first PMOS transistor MP1 is connected to the sources of the second and third PMOS transistors MP2 and MP3, the gate of the second PMOS transistor MP2 is connected to the feedback voltage FB, the gate of the third PMOS transistor MP3 is connected to the reference voltage VREF, the drain of the second PMOS transistor MP2 is connected to the gate and drain of the second NMOS transistor MN2 and the gate of the first NMOS transistor MN1, the drain of the third PMOS transistor MP3 is connected to the gate and drain of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4, the gate of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5, the gate of the fourth PMOS transistor MP4 is also connected to the gate of the fourth PMOS transistor MP4 and the gate of the fourth PMOS transistor MP3, and the drain of the fourth PMOS transistor MP1 is connected to the drain of the fourth PMOS transistor MP4, and the output current EA of the fourth NMOS transistor MN1 is provided as the output error amplifier circuit is provided EA_2 The transient response compensation current provided by the transient compensation circuit is connected to the output end EA_OUT, and the sources of the first NMOS tube MN1 to the fourth NMOS tube MN4 are grounded.
In the error amplifier for improving DC-DC transient response, the error amplifying circuit further comprises: the compensating resistor R is connected in series with the first capacitor C1 and then is connected between the output end EA_OUT and the ground, and the second capacitor C2 is connected between the output end EA_OUT and the ground.
In the error amplifier for improving DC-DC transient response, the transient compensation circuit comprises: the ratio of the width to the length of the sixth PMOS tube MP6 to the length of the eighth PMOS tube MP8 to the width to the length of the fifth NMOS tube MN5 to the length of the seventh NMOS tube MN7 is K:1, and the width to the length ratio of the sixth NMOS tube MN6 to the length of the seventh NMOS tube MN7 is equal; the sources of the sixth to eighth PMOS tubes MP6 to MP8 are all connected with the power supply voltage VDD, and the grid electrode of the sixth PMOS tube MP6 is connected with the grid electrodes of the fourth and fifth PMOS tubes MP4 and MP 5; the drain electrode of the sixth PMOS transistor MP6 is connected to the drain electrode of the fifth NMOS transistor MN5, the drain electrode and the gate electrode of the sixth NMOS transistor MN6, and the gate electrode of the seventh NMOS transistor MN7, the gate electrode of the fifth NMOS transistor MN5 is connected to the gate electrodes of the third and fourth NMOS transistors MN3 and MN4, the drain electrode of the seventh NMOS transistor MN7 is connected to the drain electrode and the gate electrode of the eighth PMOS transistor MP8, and the gate electrode of the seventh PMOS transistor MP7, the source electrodes of the fifth to seventh NMOS transistors MN5 to MN7 are grounded, and the drain electrode of the seventh PMOS transistor MP7 provides a transient response compensation current of the transient response compensation circuit and is connected to the output terminal ea_out.
The error amplifier for improving DC-DC transient response can adopt a cascode circuit structure.
Wherein the error amplifying circuit comprises: the error amplifying circuit includes: twenty-first to twenty-seventh PMOS transistors MP21 to MP27 and twenty-first to twenty-eighth NMOS transistors MN21 to MN28. The sources of the twenty-first, twenty-fourth and twenty-sixth PMOS pipes MP21, MP24 and MP26 are all connected with the power supply voltage VDD, the grid electrode of the twenty-first PMOS pipe MP21 is connected with the bias voltage VBP, the drain electrode of the twenty-first PMOS pipe MP21 is respectively connected with the sources of the twenty-second and twenty-third PMOS pipes MP22 and MP23, the grid electrode of the twenty-second PMOS pipe MP22 is connected with the feedback voltage FB, the grid electrode of the twenty-third PMOS pipe MP23 is connected with the reference voltage VREF, the drain electrode of the twenty-second PMOS pipe MP22 is connected with the drain electrode of the twenty-second NMOS pipe MN22 and the grid electrodes of the twenty-third and twenty-fourth NMOS pipes MN23 and MN24, the drain electrode of the twenty-third PMOS pipe MP23 is connected with the drain electrode of the twenty-fifth NMOS pipe MN25 and the grid electrodes of the twenty-seventh and twenty-eighth NMOS pipes MN27 and MN28, the twenty-eleventh, twenty-second, twenty-fifth and twenty-sixth NMOS pipes MP23 are connectedThe gates of the transistors MN21, MN22, MN25, MN26 are connected to each other and are connected to the second bias voltage VB2, the source of the twenty-first NMOS transistor MN21 is connected to the drain of the twenty-third NMOS transistor MN23, the source of the twenty-second NMOS transistor MN22 is connected to the drain of the twenty-fourth NMOS transistor MN24, the source of the twenty-fifth NMOS transistor MN25 is connected to the drain of the twenty-seventh NMOS transistor MN27, the source of the twenty-sixth NMOS transistor MN26 is connected to the drain of the twenty-eighth NMOS transistor MN28, the sources of the twenty-thirteenth, twenty-fourth, twenty-eighth NMOS transistors MN23, MN24, MN27, and MN28 are connected to the drain of the twenty-first NMOS transistor MN21, the drain of the twenty-fifth PMOS transistor MP25 and the gates of the twenty-fourth PMOS transistor MP24 and the twenty-sixth PMOS transistor MP26 are connected to the drain of the twenty-fifth PMOS transistor MP25, the drain of the twenty-fifth PMOS transistor MP26 is connected to the drain of the twenty-seventh PMOS transistor MP27, and the drain of the twenty-eighth NMOS transistor MP26 is connected to the drain of the twenty-first PMOS transistor 2, and the twenty-first PMOS transistor 2 is connected to the drain of the twenty-eighth NMOS transistor 2, and the drain of the twenty-eighth NMOS transistor 2 is connected to the drain of the twenty-eighth NMOS transistor MP27 is connected to the drain of the twenty-eighth NMOS transistor MN EA_2 The transient response compensation current provided by the transient compensation circuit is connected to the output end EA_OUT.
In the error amplifier for improving DC-DC transient response, the error amplifying circuit further comprises: the compensating resistor R is connected in series with the first capacitor C1 and then is connected between the output end EA_OUT and the ground, and the second capacitor C2 is connected between the output end EA_OUT and the ground.
In the error amplifier for improving DC-DC transient response, the transient compensation circuit comprises: twenty-eighth to thirty-third PMOS transistors MP28 to MP33 and twenty-ninth to thirty-third NMOS transistors MN29 to MN33. The sources of the twenty-eighth PMOS tube MP28, the thirty-eighth PMOS tube MP30 and the thirty-second PMOS tube MP32 are all connected with the power supply voltage VDD, and the grid electrode of the twenty-eighth PMOS tube MP28 is connected with the grid electrodes of the twenty-fourth PMOS tube MP24 and the twenty-sixth PMOS tube MP 26; the drain electrode of the twenty eighth PMOS tube MP28 is connected with the source electrode of the twenty ninth PMOS tube MP29, the drain electrode of the thirty second PMOS tube MP30 is connected with the source electrode of the thirty first PMOS tube MP31, the drain electrode of the thirty second PMOS tube MP32 is connected with the source electrode of the thirty third PMOS tube MP33, the grid electrodes of the thirty second PMOS tube MP30 and MP32 are connected with the drain electrodes of the thirty third PMOS tube MP33 and the thirty first NMOS tube MN31, and the grid electrodes of the twenty ninth, thirty first and thirty third PMOS tubes MP29, MP31 and MP33 are connected with the grid electrodes of the twenty fifth and twenty seventh PMOS tubes MP25 and MP 27; the drain electrodes of the twenty-ninth PMOS transistor MP29 are connected to the drain electrodes of the twenty-ninth and thirty-eighth NMOS transistors MN29, MN30 and the gate electrodes of the thirty-eighth and thirty-third NMOS transistors MN32, MN33, the gate electrodes of the thirty-eighth and thirty-first NMOS transistors MN30, MN31 are connected to the gate electrodes of the twenty-first, twenty-second, twenty-fifth, twenty-sixth NMOS transistors MN21, MN22, MN25, MN26, the source electrode of the thirty-first NMOS transistor MN30 is connected to the drain electrode of the thirty-second NMOS transistor MN32, the source electrode of the thirty-first NMOS transistor MN31 is connected to the drain electrode of the thirty-third NMOS transistor MN33, the gate electrodes of the twenty-ninth NMOS transistor MN29 are connected to the gate electrodes of the twenty-seventh and twenty-eighth NMOS transistors MN27, MN28, the source electrodes of the twenty-ninth, thirty-third NMOS transistors MN29, MN32, MN33 are grounded, and the drain electrode of the thirty-first PMOS transistor MP31 provides the transient response current compensation circuit and is connected to the transient response output end EA.
The error amplifier for improving DC-DC transient response comprises an error amplifying circuit and a transient compensation circuit, wherein the transient compensation circuit is used for providing transient response compensation current to the output end of the error amplifying circuit when the output voltage of the error amplifying circuit drops sharply to enable the feedback voltage to be lower than the reference voltage. Therefore, the current at the output end of the error amplifier is larger than the injection current of the traditional operational amplifier, the output voltage of the error amplifier can be raised faster, the larger the voltage of the error amplifier is, the larger the corresponding inductance peak current is, so that more current can be provided for output faster, and the output voltage can be raised to a set value in a shorter time.
Drawings
Fig. 1 is a schematic circuit diagram of a conventional error amplifier.
Fig. 2 is a schematic circuit diagram of an embodiment of an error amplifier for improving DC-DC transient response according to the present invention.
Fig. 3 is a schematic circuit diagram of another embodiment of an error amplifier for improving DC-DC transient response according to the present invention.
Detailed Description
In order to make the technical contents of the present invention more clearly understood, the following examples are specifically described.
The error amplifier of the invention is added with a transient compensation circuit on the basis of the traditional error amplifying circuit shown in figure 1, and the error amplifying circuit is used for generating output voltage according to feedback voltage and reference voltage; the transient compensation circuit is used for providing transient response compensation current for the output end of the error amplification circuit when the output voltage of the error amplification circuit drops sharply so that the feedback voltage is lower than the reference voltage.
Referring to fig. 2, a schematic circuit diagram of an embodiment of an error amplifier for improving DC-DC transient response according to the present invention is shown.
In this embodiment, the error amplifying circuit includes: first to fifth PMOS transistors MP1 to MP5 and first to fourth NMOS transistors MN1 to MN4.
The aspect ratios of the second PMOS transistor MP2 and the third PMOS transistor MP3, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5, the first NMOS transistor MN1 and the second NMOS transistor MN2, and the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are respectively equal.
Wherein the sources of the first, fourth and fifth PMOS tubes MP1, MP4, MP5 are connected with the power supply voltage VDD, the grid electrode of the first PMOS tube MP1 is connected with the bias voltage VBP, the drain electrode of the first PMOS tube MP1 is respectively connected with the sources of the second and third PMOS tubes MP2, MP3, the grid electrode of the second PMOS tube MP2 is connected with the feedback voltage FB, and the grid electrode of the third PMOS tube MP3 is connected with the reference voltageVREF, the drain electrode of the second PMOS tube MP2 is connected with the gate electrode and the drain electrode of the second NMOS tube MN2 and the gate electrode of the first NMOS tube MN1, the drain electrode of the third PMOS tube MP3 is connected with the gate electrode and the drain electrode of the third NMOS tube MN3 and the gate electrode of the fourth NMOS tube MN4, the gate electrode of the fourth PMOS tube MP4 is connected with the gate electrode of the fifth PMOS tube MP5, the gate electrode of the fourth PMOS tube MP4 is also connected with the drain electrodes of the fourth PMOS tube MP4 and the first NMOS tube MN1, the drain electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the fourth NMOS tube MN4 and is used as the output end EA_OUT of the error amplifying circuit to provide the output current I EA_2 The transient response compensation current provided by the transient compensation circuit is connected to the output end EA_OUT, and the sources of the first NMOS tube MN1 to the fourth NMOS tube MN4 are grounded.
The error amplifying circuit further includes: the compensating resistor R is connected in series with the first capacitor C1 and then is connected between the output end EA_OUT and the ground, and the second capacitor C2 is connected between the output end EA_OUT and the ground.
The transient compensation circuit includes: sixth to eighth PMOS transistors MP6 to MP8 and fifth to seventh NMOS transistors MN5 to MN7.
The width-to-length ratio of the sixth PMOS tube MP6 is smaller than that of the fifth PMOS tube MP5, the ratio relationship of the width-to-length ratio of the seventh PMOS tube MP7 to the eighth PMOS tube MP8 is K:1, and the width-to-length ratio of the sixth NMOS tube MN6 and the seventh NMOS tube MN7 is equal.
The sources of the sixth to eighth PMOS tubes MP6 to MP8 are all connected with the power supply voltage VDD, and the grid electrode of the sixth PMOS tube MP6 is connected with the grid electrodes of the fourth and fifth PMOS tubes MP4 and MP 5; the drain electrode of the sixth PMOS transistor MP6 is connected to the drain electrode of the fifth NMOS transistor MN5, the drain electrode and the gate electrode of the sixth NMOS transistor MN6, and the gate electrode of the seventh NMOS transistor MN7, the gate electrode of the fifth NMOS transistor MN5 is connected to the gate electrodes of the third and fourth NMOS transistors MN3 and MN4, the drain electrode of the seventh NMOS transistor MN7 is connected to the drain electrode and the gate electrode of the eighth PMOS transistor MP8, and the gate electrode of the seventh PMOS transistor MP7, the source electrodes of the fifth to seventh NMOS transistors MN5 to MN7 are grounded, and the drain electrode of the seventh PMOS transistor MP7 provides a transient response compensation current of the transient response compensation circuit and is connected to the output terminal ea_out.
Because the width-to-length ratio of the sixth PMOS tube MP6 is smaller than that of the fourth PMOS tube MP4 and the fifth PMOS tube MP5. Thus, in normal operation, the system feedback voltage FB is equal to the reference voltage VREF and the output terminal ea_out voltage is at an intermediate value between the power supply and ground. The width-to-length ratio of the sixth PMOS MP6 is smaller than that of the fifth PMOS MP5, so that the voltage of the node a in fig. 2 is pulled down to 0. The currents of the sixth NMOS tube MN6, the seventh NMOS tube MN7, the eighth PMOS tube MP8 and the seventh PMOS tube MP7 are all 0, so that the normal operation of the error amplifier is not affected.
When the output current of the system suddenly jumps from light load to heavy load, the output voltage drops sharply, and the feedback voltage FB drops sharply as the current provided to the output by the DC-DC system is insufficient to maintain the output voltage at the set value. After the feedback voltage FB drops to a certain value, the current of the second PMOS transistor MP2 is far greater than the current of the third PMOS transistor MP 3. Therefore, the current of the second PMOS transistor MN2 is far greater than that of the third NMOS transistor MN 3. Because of the current replication relationship of the current mirror, the current of the fourth PMOS transistor MP4 is far greater than the current of the fourth NMOS transistor MN4. Even if the width-to-length ratio of the sixth PMOS transistor MP6 is smaller than that of the fourth PMOS transistor MP4, that is, the current of the sixth PMOS transistor MP6 is smaller than that of the fourth PMOS transistor MP4, the current of the sixth PMOS transistor MP6 is still larger than that of the fourth NMOS transistor MN4.
Then the current of the sixth NMOS transistor MN6 is:
(1)
the width-to-length ratio of the sixth NMOS transistor MN6 is equal to that of the seventh NMOS transistor MN7, and the ratio relationship of the width-to-length ratio of the seventh NMOS transistor MP7 to that of the eighth NMOS transistor MP8 is K:1. The K value can be set according to the specific case, and thus can be obtained:
(2)
therefore, when the feedback voltage FB is low, the current injected by the error amplifier to the compensation resistor and capacitor is:
(3)
in the structure of the conventional operational amplifier, when the feedback voltage FB is low, the currents injected into the compensation resistor and the capacitor of the error amplifier are as follows:
(4)
comparing equations (3) and (4) it is readily apparent that the current injected by the circuit of the present invention ea_out is greater than the current injected by the conventional op-amp when the feedback voltage FB is lower than the reference voltage VREF. Therefore, the output voltage of the error amplifier can be raised faster, the larger the voltage of the error amplifier is, the larger the corresponding inductance peak current is, so that more current can be provided for the output faster, and the output voltage is raised to the set value in a shorter time.
In another embodiment, as shown in fig. 3, in order to increase the gain of the error amplifier EA, the error amplifier for improving DC-DC transient response of the present invention may also employ a cascode structure.
In this embodiment, the error amplifying circuit includes: twenty-first to twenty-seventh PMOS transistors MP21 to MP27 and twenty-first to twenty-eighth NMOS transistors MN21 to MN28.
The sources of the twenty-first, twenty-fourth and twenty-sixth PMOS pipes MP21, MP24 and MP26 are all connected with a power supply voltage VDD, the grid electrode of the twenty-first PMOS pipe MP21 is connected with a bias voltage VBP, the drain electrode of the twenty-first PMOS pipe MP21 is respectively connected with the sources of the twenty-second and twenty-third PMOS pipes MP22 and MP23, the grid electrode of the twenty-second PMOS pipe MP22 is connected with the feedback voltage FB, the grid electrode of the twenty-third PMOS pipe MP23 is connected with the reference voltage VREF, the drain electrode of the twenty-second PMOS pipe MP22 is connected with the drain electrode of the twenty-second NMOS pipe MN22 and the grid electrodes of the twenty-third and twenty-fourth NMOS pipes MN23 and MN24, the drain electrode of the twenty-third PMOS pipe MP23 is connected with the drain electrode of the twenty-fifth NMOS pipe MN25And gates of twenty-seventh and twenty-eighth NMOS transistors MN27, MN28, gates of the twenty-first, twenty-second, twenty-fifth and twenty-sixth NMOS transistors MN21, MN22, MN25, MN26 are connected and connected with a second bias voltage VB2, a source of the twenty-first NMOS transistor MN21 is connected with a drain of the twenty-third NMOS transistor MN23, a source of the twenty-second NMOS transistor MN22 is connected with a drain of the twenty-fourth NMOS transistor MN24, a source of the twenty-fifth NMOS transistor MN25 is connected with a drain of the twenty-seventh NMOS transistor MN27, a source of the twenty-sixth NMOS transistor MN26 is connected with a drain of the twenty-eighth NMOS transistor MN28, sources of the twenty-third, twenty-fourth, twenty-seventh and twenty-eighth NMOS transistors MN23, MN24, MN27, MN28 are grounded, the drain electrode of the twenty-first NMOS transistor MN21 is connected with the drain electrode of the twenty-fifth PMOS transistor MP25 and the gates of the twenty-fourth and twenty-sixth PMOS transistors MP24 and MP26, the drain electrode of the twenty-fourth PMOS transistor MP24 is connected with the source electrode of the twenty-fifth PMOS transistor MP25, the drain electrode of the twenty-sixth PMOS transistor MP26 is connected with the source electrode of the twenty-seventh PMOS transistor MP27, the gates of the twenty-fifth and twenty-seventh PMOS transistors MP25 and MP27 are connected with the first bias voltage VB1, the drain electrode of the twenty-seventh PMOS transistor MP27 is connected with the drain electrode of the twenty-sixth NMOS transistor MN26 and is used as the output end EA_OUT of the error amplifying circuit to provide the output current I EA_2 The transient response compensation current provided by the transient compensation circuit is connected to the output end EA_OUT.
The error amplifying circuit further includes: the compensating resistor R is connected in series with the first capacitor C1 and then is connected between the output end EA_OUT and the ground, and the second capacitor C2 is connected between the output end EA_OUT and the ground.
The transient compensation circuit includes: twenty-eighth to thirty-third PMOS transistors MP28 to MP33 and twenty-ninth to thirty-third NMOS transistors MN29 to MN33.
The sources of the twenty-eighth PMOS tube MP28, the thirty-eighth PMOS tube MP30 and the thirty-second PMOS tube MP32 are all connected with the power supply voltage VDD, and the grid electrode of the twenty-eighth PMOS tube MP28 is connected with the grid electrodes of the twenty-fourth PMOS tube MP24 and the twenty-sixth PMOS tube MP 26; the drain electrode of the twenty eighth PMOS tube MP28 is connected with the source electrode of the twenty ninth PMOS tube MP29, the drain electrode of the thirty second PMOS tube MP30 is connected with the source electrode of the thirty first PMOS tube MP31, the drain electrode of the thirty second PMOS tube MP32 is connected with the source electrode of the thirty third PMOS tube MP33, the grid electrodes of the thirty second PMOS tube MP30 and MP32 are connected with the drain electrodes of the thirty third PMOS tube MP33 and the thirty first NMOS tube MN31, and the grid electrodes of the twenty ninth, thirty first and thirty third PMOS tubes MP29, MP31 and MP33 are connected with the grid electrodes of the twenty fifth and twenty seventh PMOS tubes MP25 and MP 27; the drain electrodes of the twenty-ninth PMOS transistor MP29 are connected to the drain electrodes of the twenty-ninth and thirty-eighth NMOS transistors MN29, MN30 and the gate electrodes of the thirty-eighth and thirty-third NMOS transistors MN32, MN33, the gate electrodes of the thirty-eighth and thirty-first NMOS transistors MN30, MN31 are connected to the gate electrodes of the twenty-first, twenty-second, twenty-fifth, twenty-sixth NMOS transistors MN21, MN22, MN25, MN26, the source electrode of the thirty-first NMOS transistor MN30 is connected to the drain electrode of the thirty-second NMOS transistor MN32, the source electrode of the thirty-first NMOS transistor MN31 is connected to the drain electrode of the thirty-third NMOS transistor MN33, the gate electrodes of the twenty-ninth NMOS transistor MN29 are connected to the gate electrodes of the twenty-seventh and twenty-eighth NMOS transistors MN27, MN28, the source electrodes of the twenty-ninth, thirty-third NMOS transistors MN29, MN32, MN33 are grounded, and the drain electrode of the thirty-first PMOS transistor MP31 provides the transient response current compensation circuit and is connected to the transient response output end EA.
The aspect ratio of the MOS transistor elements in this embodiment is similar to that in the previous embodiment. The width-to-length ratio of the twenty eighth PMOS tube MP28 is smaller than that of the twenty sixth PMOS tube MP26, the width-to-length ratio of the twenty ninth PMOS tube MP29 is smaller than that of the twenty seventh PMOS tube MP27, the ratio relationship of the width-to-length ratio of the thirty first PMOS tube MP30 to the thirty second PMOS tube MP32 is K:1, the ratio relationship of the width-to-length ratio of the thirty first PMOS tube MP31 to the thirty third PMOS tube MP33 is K:1, the width-to-length ratio of the twenty eighth PMOS tube MP28 and the thirty first PMOS tube MP30 are equal, and the width-to-length ratio of the twenty ninth PMOS tube MP29 and the thirty first PMOS tube MP31 are equal.
In the DC-DC of the peak current mode, aiming at the limitation of the traditional error amplifier on improving the transient response of the DC-DC, the novel error amplifier provided by the invention improves the transient response of the DC-DC. When the output load suddenly changes from light load to heavy load, the output voltage will drop rapidly, and when the output voltage is lower than the set value by 2%, the error amplifier of the invention will have extra current injected into the output of the error amplifier, thereby raising the output voltage of the error amplifier faster, providing larger current for the load, and raising the output voltage to the set value rapidly.
The error amplifier for improving DC-DC transient response comprises an error amplifying circuit and a transient compensation circuit, wherein the transient compensation circuit is used for providing transient response compensation current to the output end of the error amplifying circuit when the output voltage of the error amplifying circuit drops sharply to enable the feedback voltage to be lower than the reference voltage. Therefore, the current at the output end of the error amplifier is larger than the injection current of the traditional operational amplifier, the output voltage of the error amplifier can be raised faster, the larger the voltage of the error amplifier is, the larger the corresponding inductance peak current is, so that more current can be provided for output faster, and the output voltage can be raised to a set value in a shorter time.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (7)
1. An error amplifier for improving DC-DC transient response is characterized by comprising an error amplifying circuit and a transient compensation circuit,
the error amplifying circuit is used for generating output voltage according to the feedback voltage and the reference voltage;
the transient compensation circuit is used for providing transient response compensation current to the output end of the error amplification circuit when the output voltage of the error amplification circuit drops sharply to enable the feedback voltage to be lower than the reference voltage,
the transient compensation circuit includes: sixth to eighth PMOS transistors (MP 6 to MP 8) and fifth to seventh NMOS transistors (MN 5 to MN 7),
the ratio relation of the width to length ratio of the seventh PMOS tube (MP 7) to the eighth PMOS tube (MP 8) is K:1, and the width to length ratio of the sixth NMOS tube (MN 6) to the seventh NMOS tube (MN 7) is equal;
the sources of the sixth to eighth PMOS tubes (MP 6-MP 8) are connected with a power supply Voltage (VDD), and the grid electrode of the sixth PMOS tube (MP 6) is connected with the error amplifying circuit; the drain electrode of the sixth PMOS tube (MP 6) is connected with the drain electrode of the fifth NMOS tube (MN 5), the drain electrode and the grid electrode of the sixth NMOS tube (MN 6) and the grid electrode of the seventh NMOS tube (MN 7), the grid electrode of the fifth NMOS tube (MN 5) is connected with the error amplifying circuit, the drain electrode of the seventh NMOS tube (MN 7) is connected with the drain electrode and the grid electrode of the eighth PMOS tube (MP 8) and the grid electrode of the seventh PMOS tube (MP 7), the source electrodes of the fifth to seventh NMOS tubes (MN 5-MN 7) are grounded, and the drain electrode of the seventh PMOS tube (MP 7) provides transient response compensation current of the transient response compensation circuit and is connected with the output end (EA_OUT).
2. The error amplifier for improving a DC-DC transient response of claim 1, wherein said error amplifying circuit comprises: first to fifth PMOS transistors (MP 1 to MP 5) and first to fourth NMOS transistors (MN 1 to MN 4),
the width-to-length ratios of the second PMOS tube (MP 2) and the third PMOS tube (MP 3), the fourth PMOS tube (MP 4) and the fifth PMOS tube (MP 5), the first NMOS tube (MN 1) and the second NMOS tube (MN 2), the third NMOS tube (MN 3) and the fourth NMOS tube (MN 4) are respectively and correspondingly equal, and the width-to-length ratio of the sixth PMOS tube (MP 6) is smaller than that of the fifth PMOS tube (MP 5); wherein the sources of the first, fourth and fifth PMOS tubes (MP 1, MP4, MP 5) are connected with the power supply Voltage (VDD), and the grid of the first PMOS tube (MP 1) is connected with biasSetting Voltage (VBP), wherein the drain electrode of the first PMOS tube (MP 1) is respectively connected with the source electrodes of the second PMOS tube (MP 2) and the third PMOS tube (MP 3), the grid electrode of the second PMOS tube (MP 2) is connected with the feedback voltage (FB), the grid electrode of the third PMOS tube (MP 3) is connected with the reference Voltage (VREF), the drain electrode of the second PMOS tube (MP 2) is connected with the grid electrode and the drain electrode of the second NMOS tube (MN 2) and the grid electrode of the first NMOS tube (MN 1), the drain electrode of the third PMOS tube (MP 3) is connected with the grid electrode and the drain electrode of the third NMOS tube (MN 3) and the grid electrodes of the fourth NMOS tube (MP 4) and the fifth NMOS tube (MN 4, MN 5), the grid electrode of the fourth PMOS tube (MP 4) is connected with the grid electrodes of the fifth PMOS tube (MP 5, MP 6), the grid electrode of the fourth PMOS tube (MP 4) is also connected with the grid electrode of the fourth PMOS tube (MP 4) and the drain electrode of the fourth PMOS tube (MP 1) is connected with the output end of the fourth NMOS tube (MP 4), and the output end of the output circuit (EA) is provided as the output end of the fourth amplifier circuit (drain Electrode (EA) EA_2 The transient response compensation current provided by the transient compensation circuit is connected to the output end (EA_OUT), and the sources of the first NMOS tube (MN 1) to the fourth NMOS tube (MN 4) are grounded.
3. The error amplifier for improving a DC-DC transient response of claim 2, wherein said error amplifying circuit further comprises: the compensating resistor (R) is connected in series with the first capacitor (C1) and then is connected between the output end (EA_OUT) and the ground, and the second capacitor (C2) is connected between the output end (EA_OUT) and the ground.
4. The error amplifier of claim 1, wherein the error amplifier has a cascode (cascode) configuration.
5. The error amplifier for improving a DC-DC transient response of claim 4, wherein said transient compensation circuit comprises: the twenty-eighth to thirty-third PMOS tubes (MP 28 to MP 33) of the sixth to eighth PMOS tubes (MP 6 to MP 8) are replaced, the twenty-ninth to thirty-third NMOS tubes (MN 29 to MN 33) of the fifth to seventh NMOS tubes (MN 5 to MN 7) are replaced,
the sources of the twenty-eighth PMOS tube (MP 28), the thirty-eighth PMOS tube (MP 30) and the thirty-second PMOS tube (MP 32) are connected with a power supply Voltage (VDD), and the grid electrode of the twenty-eighth PMOS tube (MP 28) is connected with the error amplifying circuit; the drain electrode of the twenty eighth PMOS tube (MP 28) is connected with the source electrode of the twenty ninth PMOS tube (MP 29), the drain electrode of the thirty second PMOS tube (MP 30) is connected with the source electrode of the thirty first PMOS tube (MP 31), the drain electrode of the thirty second PMOS tube (MP 32) is connected with the source electrode of the thirty third PMOS tube (MP 33), the grid electrodes of the thirty second PMOS tube (MP 30) and the thirty second PMOS tube (MP 32) are connected and connected with the drain electrodes of the thirty third PMOS tube (MP 33) and the thirty first NMOS tube (MN 31), and the grid electrodes of the twenty ninth, thirty eleventh and thirty third PMOS tubes (MP 29, MP31, MP 33) are connected with the error amplifying circuit; the drain electrode of the twenty-ninth PMOS tube (MP 29) is connected with the drain electrodes of the twenty-ninth NMOS tube (MN 29, MN 30) and the gate electrodes of the thirty-eighth NMOS tube (MN 32, MN 33), the gate electrodes of the thirty-eighth NMOS tube (MN 30, MN 31) are connected with the error amplifying circuit, the source electrode of the thirty-eighth NMOS tube (MN 30) is connected with the drain electrode of the thirty-second NMOS tube (MN 32), the source electrode of the thirty-eighth NMOS tube (MN 31) is connected with the drain electrode of the thirty-eighth NMOS tube (MN 33), the gate electrodes of the twenty-ninth NMOS tube (MN 29) are connected with the error amplifying circuit, the source electrodes of the twenty-eighth NMOS tube (MN 29, MN32, MN 33) are grounded, and the drain electrode of the thirty-eighth NMOS tube (MP 31) provides transient response compensation current of the transient compensation circuit and is connected with the output end (EA_OUT).
6. The error amplifier for improving a DC-DC transient response of claim 5, wherein said error amplifying circuit comprises: twenty-first to twenty-seventh PMOS transistors (MP 21 to MP 27) and twenty-first to twenty-eighth NMOS transistors (MN 21 to MN 28),
the sources of the twenty-first, twenty-fourth and twenty-sixth PMOS pipes (MP 21, MP24, MP 26) are all connected with a power supply Voltage (VDD), the grid electrode of the twenty-first PMOS pipe (MP 21) is connected with a bias Voltage (VBP), the drain electrode of the twenty-first PMOS pipe (MP 21) is respectively connected with the sources of the twenty-second and twenty-third PMOS pipes (MP 22, MP 23), the grid electrode of the twenty-second PMOS pipe (MP 22) is connected with the feedback voltage (FB), the grid electrode of the twenty-third PMOS pipe (MP 23) is connected with the reference Voltage (VREF), the drain electrode of the twenty-second PMOS pipe (MP 22) is connected with the drain electrode of the twenty-second NMOS pipe (MN 22) and the grid electrodes of the twenty-third and twenty-fourth NMOS pipes (MN 23, MN 24), the drain electrode of the twenty-third PMOS tube (MP 23) is connected with the drain electrode of the twenty-fifth NMOS tube (MN 25) and the grid electrodes of twenty-seventh, twenty-eighth and twenty-ninth NMOS tubes (MN 27, MN28, MN 29), the grid electrodes of the twenty-eleventh, twenty-second, twenty-fifth, twenty-sixth and thirty-first NMOS tubes (MN 21, MN22, MN25, MN26, MN30, MN 31) are connected and connected with a second bias voltage (VB 2), the source electrode of the twenty-first NMOS tube (MN 21) is connected with the drain electrode of the twenty-third NMOS tube (MN 23), the source electrode of the twenty-second NMOS tube (MN 22) is connected with the drain electrode of the twenty-fourth NMOS tube (MN 24), the source of the twenty-fifth NMOS tube (MN 25) is connected with the drain of the twenty-seventh NMOS tube (MN 27), the source of the twenty-sixth NMOS tube (MN 26) is connected with the drain of the twenty-eighth NMOS tube (MN 28), the sources of the twenty-third, twenty-fourth, twenty-seventh and twenty-eighth NMOS tubes (MN 23, MN24, MN27, MN 28) are grounded, the drain of the twenty-first NMOS tube (MN 21) is connected with the drain of the twenty-fifth PMOS tube (MP 25) and the gates of the twenty-fourth, twenty-sixth and twenty-eighth PMOS tubes (MP 24, MP26, MP 28), the drain of the twenty-fourth PMOS tube (MP 24) is connected with the source of the twenty-fifth PMOS tube (MP 25)The drain electrode of the twenty-sixth PMOS tube (MP 26) is connected with the source electrode of the twenty-seventh PMOS tube (MP 27), the grid electrodes of the twenty-fifth, twenty-seventh, twenty-ninth, thirty-eleventh and thirty-third PMOS tubes (MP 25, MP27, MP29, MP31, MP 33) are connected and connected with the first bias voltage (VB 1), the drain electrode of the twenty-seventh PMOS tube (MP 27) is connected with the drain electrode of the twenty-sixth NMOS tube (MN 26) and used as the output end (EA_OUT) of the error amplifying circuit to provide the output current I EA_2 The transient response compensation current provided by the transient compensation circuit is connected to the output terminal (EA_OUT).
7. The error amplifier for improving a DC-DC transient response of claim 6, wherein said error amplifying circuit further comprises: the compensating resistor (R) is connected in series with the first capacitor (C1) and then is connected between the output end (EA_OUT) and the ground, and the second capacitor (C2) is connected between the output end (EA_OUT) and the ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310856265.0A CN116581963B (en) | 2023-07-13 | 2023-07-13 | Error amplifier for improving DC-DC transient response |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310856265.0A CN116581963B (en) | 2023-07-13 | 2023-07-13 | Error amplifier for improving DC-DC transient response |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116581963A true CN116581963A (en) | 2023-08-11 |
| CN116581963B CN116581963B (en) | 2023-09-19 |
Family
ID=87534554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310856265.0A Active CN116581963B (en) | 2023-07-13 | 2023-07-13 | Error amplifier for improving DC-DC transient response |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116581963B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102778911A (en) * | 2012-07-19 | 2012-11-14 | 电子科技大学 | Voltage buffer circuit and low dropout regulator (LDO) integrated with voltage buffer circuit |
| WO2014079129A1 (en) * | 2012-11-21 | 2014-05-30 | 东南大学 | Fast transient response dc-dc switching converter with high load regulation rate |
| CN108445947A (en) * | 2018-05-21 | 2018-08-24 | 广州大学 | A kind of fast transient response circuit applied to DC-DC converter chip |
| CN111736652A (en) * | 2020-07-01 | 2020-10-02 | 上海艾为电子技术股份有限公司 | Capacitance multiplying circuit and linear voltage regulator |
-
2023
- 2023-07-13 CN CN202310856265.0A patent/CN116581963B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102778911A (en) * | 2012-07-19 | 2012-11-14 | 电子科技大学 | Voltage buffer circuit and low dropout regulator (LDO) integrated with voltage buffer circuit |
| WO2014079129A1 (en) * | 2012-11-21 | 2014-05-30 | 东南大学 | Fast transient response dc-dc switching converter with high load regulation rate |
| CN108445947A (en) * | 2018-05-21 | 2018-08-24 | 广州大学 | A kind of fast transient response circuit applied to DC-DC converter chip |
| CN111736652A (en) * | 2020-07-01 | 2020-10-02 | 上海艾为电子技术股份有限公司 | Capacitance multiplying circuit and linear voltage regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116581963B (en) | 2023-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101667046B (en) | Low-dropout voltage regulator | |
| CN113268102B (en) | An ultra-low power fast transient response low dropout linear regulator circuit | |
| CN106155162B (en) | A kind of low pressure difference linear voltage regulator | |
| CN111176358B (en) | Low-power-consumption low-dropout linear voltage regulator | |
| CN111338413A (en) | A Low Dropout Linear Regulator with High Power Supply Rejection Ratio | |
| US20020109547A1 (en) | Slew rate boost circuitry and method | |
| CN114610107A (en) | NMOS LDO based on hybrid modulation bias current generating circuit | |
| CN109742946B (en) | A DCR Sampling Circuit Applied to Buck Converters with Wide Output Voltage Range | |
| CN107092295A (en) | A High Slew Rate Fast Transient Response LDO Circuit | |
| CN112684844B (en) | Low dropout regulator | |
| CN115357078A (en) | LDO circuit for improving transient response capability | |
| CN115729301A (en) | A Linear Regulator Without Off-Chip Capacitor with Enhanced Transient Response | |
| CN116581963B (en) | Error amplifier for improving DC-DC transient response | |
| CN113377152B (en) | Quick response does not have external electric capacity type linear voltage regulator | |
| CN114967811A (en) | An LDO without Off-Chip Capacitor to Improve PSR Performance | |
| CN118232862B (en) | Fully Differential Class-AB Operational Amplifier Circuits and Systems | |
| CN116719382B (en) | High PSR's off-chip capacitor LDO circuit | |
| CN114564067A (en) | Low dropout regulator with high power supply rejection ratio | |
| CN110825157B (en) | Low dropout regulator based on heavy load compensation | |
| CN116126075B (en) | On-chip high-voltage linear voltage stabilizer circuit and voltage stabilizing method thereof | |
| CN114840046B (en) | A Linear Regulator Based on Current Miller Compensation | |
| CN113849033B (en) | Linear voltage stabilizer with impedance attenuation compensation | |
| CN114779866B (en) | A high-voltage multi-stage LDO circuit with optimized quality factor | |
| CN118466670A (en) | A bandgap reference circuit and its design method and chip | |
| CN116192071A (en) | Operational amplifier circuit, linear voltage regulator, chip and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |