CN116504646A - Multi-chip array packaging structure and method - Google Patents

Abstract

The invention relates to a multi-chip arrangement packaging structure and a method, wherein the method comprises the following steps: providing a copper plate; planting a plurality of copper columns on the provided copper plate; providing a substrate and connecting the copper column on the substrate; carrying out plastic package on the copper column between the substrate and the copper plate to form a plastic package layer for coating the copper column; removing the copper plate by using a grinding process to expose the copper columns; providing a plurality of chips, and mounting the provided chips on the copper columns; dispensing heat dissipation glue on the chip to form a heat dissipation glue layer; coating insulating glue on the side part of the chip to form an insulating glue layer which is positioned on the corresponding plastic sealing layer and is adhered to the chip; and (5) planting solder balls on the back surface of the substrate, thereby completing packaging. The packaging method of the invention arranges a plurality of chips on the copper column, can effectively reduce the volume of the product, and has the advantages of short production lead time, low manufacturing cost, low power consumption, high data transmission rate, small occupied space and the like.

Description

Multi-chip array packaging structure and method

technical field

The invention relates to the technical field of semiconductor packaging, in particular to a multi-chip array packaging structure and method.

Background technique

The flip-chip packaging structure is only suitable for the case where the bump pitch (Bump pitch) is greater than 60um. For the case where the bump pitch is less than 60um, the existing packaging method can only use TCB (Thermal Compression Bonding) packaging way, but the TCB packaging method has the problems of poor yield and high cost. Therefore, it is urgent to provide a new packaging method to adapt to the situation that the pitch of the bumps is less than 60um.

Contents of the invention

The purpose of the present invention is to overcome the defects of the prior art, provide a multi-chip array packaging structure and method, solve the problem that the existing flip-chip packaging structure cannot be applied to the bump pitch less than 60um and the yield rate of TCB packaging Poor and high cost issues.

The technical scheme for realizing the above-mentioned purpose is:

The invention provides a multi-chip array packaging method, comprising the following steps:

provide a copper plate;

Plant multiple copper pillars on the copper plate provided;

providing a substrate, and connecting the copper pillars to the substrate;

performing plastic sealing on the copper pillars between the substrate and the copper plate to form a plastic sealing layer covering the copper pillars;

removing the copper plate by a grinding process to expose the copper pillar;

providing a plurality of chips, and mounting the provided chips on the copper pillar;

Dot heat dissipation glue on the chip to form a heat dissipation glue layer;

Coating insulating glue on the side of the chip to form an insulating glue layer on the corresponding plastic sealing layer and attached to the chip;

Planting solder balls on the back of the substrate to complete the package.

The packaging method of the present invention arranges multiple chips on the copper pillars, which can effectively reduce the volume of the product, and can package chips of different specifications and sizes such as DRAM, flash memory, and SRAM in a single module. On the basis of low cost, the 8-chip stack has the advantages of short production lead time, low manufacturing cost, low power consumption, high data transfer rate and small footprint.

The further improvement of the multi-chip array packaging method of the present invention is that a heat sink is provided, and the heat sink is covered on the insulating adhesive layer and the heat dissipation adhesive layer, and is connected with the insulating adhesive layer and the heat dissipation adhesive layer. Layer paste is fixed.

A further improvement of the multi-chip array packaging method of the present invention is that the provided heat sink includes a top plate covered on the insulating adhesive layer and the heat dissipation adhesive layer and four side plates connected to the top plate;

When setting the heat sink, the heat sink cover is buckled on the insulating adhesive layer and the heat dissipation adhesive layer, and the four side plates of the heat sink are attached to the insulating adhesive layer and the heat dissipation adhesive layer. on the side corresponding to the plastic sealing layer.

A further improvement of the multi-chip array packaging method of the present invention lies in that, when planting copper pillars on the copper plate, the distance between two adjacent copper pillars should be less than 60 um.

A further improvement of the multi-chip array packaging method of the present invention is that, after the chips are mounted, wire bonding is performed on the chips.

The present invention also provides a multi-chip array packaging structure, including:

Substrate;

A plurality of copper pillars connected to the substrate, the tops of the copper pillars are connected with a removable copper plate;

Plastic sealing a plastic sealing layer formed between the substrate and the copper plate and wrapping the copper pillar;

Multiple chips mounted on copper pillars exposed by grinding to remove the copper plate;

A heat dissipation glue layer arranged on the chip;

an insulating adhesive layer disposed on the side of the chip and on the corresponding plastic encapsulation layer;

Solder balls arranged on the back of the substrate.

A further improvement of the multi-chip array packaging structure of the present invention is that it further includes a heat sink covering the insulating adhesive layer.

The further improvement of the multi-chip arrangement package structure of the present invention is that the heat sink includes a top plate covered on the insulating adhesive layer and the heat dissipation adhesive layer and four side plates vertically connected to the top plate, the The four side panels are attached to the insulating glue layer and the corresponding sides of the plastic sealing layer.

The further improvement of the multi-chip array packaging structure of the present invention lies in that the distance between two adjacent copper pillars is less than 60um.

A further improvement of the multi-chip array package structure of the present invention is that it further includes welding wires connected to the chips.

Description of drawings

FIG. 1 is a structural schematic diagram of a copper plate in the multi-chip array packaging structure and method of the present invention.

FIG. 2 is a structural schematic diagram of planting copper pillars on a copper plate in the multi-chip array packaging method of the present invention.

FIG. 3 is a schematic structural diagram of connecting copper pillars to a substrate in the multi-chip array packaging method of the present invention.

FIG. 4 is a schematic structural view of plastic-encapsulating copper pillars in the multi-chip array packaging method of the present invention.

FIG. 5 is a schematic diagram of the structure after grinding and removing the copper plate in the multi-chip array packaging method of the present invention.

FIG. 6 is a schematic structural diagram of mounting chips in the multi-chip array packaging method of the present invention.

FIG. 7 is a schematic structural diagram of a heat sink provided in the multi-chip array packaging method of the present invention.

FIG. 8 is a schematic structural diagram of planting solder balls on the substrate in the multi-chip array packaging method of the present invention.

Explanation of reference signs:

21-copper plate; 22-copper column; 23-substrate; solder ball-231; 24-plastic sealing layer; 25-chip;

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

Referring to FIG. 8 , the present invention provides a multi-chip array packaging structure and method, which are used to solve the problems of poor yield and high cost in the existing TCB packaging method. In the present invention, copper pillars with a spacing of less than 60um are planted on the copper plate, and the chip arrangement is used to effectively reduce the volume of electronic products, and multiple chips are packaged together, which has the advantages of short production lead time, low manufacturing cost, and low power consumption. The advantages of power consumption, high data transfer rate and small footprint. The multi-chip array packaging structure and method of the present invention will be described below with reference to the accompanying drawings.

Referring to FIG. 8 , it shows a cross-sectional view of the multi-chip array package structure of the present invention. The multi-chip array packaging structure of the present invention will be described below with reference to FIG. 8 .

As shown in Figure 8, the multi-chip arrangement packaging structure of the present invention includes a substrate 23, a copper column 22, a copper plate 21, a plastic sealing layer 24, a chip 25, a heat dissipation adhesive layer 26, an insulating adhesive layer 28, and a solder ball 231; the copper column 22 has Multiple, connected between the substrate 23 and the copper plate 21, preferably, as shown in FIG. 1 and FIG. One end is connected to the substrate 23, and the copper plate 21 can be removed by grinding later. As shown in FIG. 4 , the plastic sealing layer 24 is formed between the substrate 23 and the copper plate 21 and wraps the copper pillars 22 . The plastic sealing layer 24 is preferably formed by insulating glue. There are multiple chips 25, and the chips 25 are mounted on the copper pillars 22 exposed after the copper plate 21 is ground and removed. As shown in FIG. 5 and FIG. mounted on the copper pillar 22. As shown in FIG. 7 , the heat dissipation adhesive layer 26 is disposed on the chip 25 , the insulating adhesive layer 28 is disposed on the side of the chip 25 and on the corresponding plastic packaging layer 24 ; the solder balls 231 are disposed on the back of the substrate 23 .

Further, as shown in FIG. 7 and FIG. 8 , a heat sink 27 covered on the insulating glue layer 28 is also included.

Still further, the heat sink 27 includes a top plate covered on the insulating adhesive layer 28 and the heat dissipation adhesive layer 26 and four side plates vertically connected to the top plate, and the four side plates are attached to the insulating adhesive layer 28 and the plastic sealing layer. 24 on the corresponding side.

Still further, the distance between two adjacent copper pillars 22 is less than 60um.

Still further, it also includes bonding wires connected to the chip 25 .

The chip array packaging structure of the present invention focuses on arranging multiple chips in one package, mainly referring to the stack of multiple memory chips. This package contains a memory subsystem, which can integrate DRAM, flash memory, and SRAM with different specifications and sizes. The chip is packaged in a single module and uses hybrid technology to stack 2 to 8 chips on a low-cost substrate, which has short production lead time, low manufacturing cost, low power consumption, high data transmission rate and small footprint, etc. Advantage.

The present invention also provides a multi-chip array packaging method, which will be described below.

As shown in Figures 1 to 8, the packaging method of the present invention includes the following steps:

providing a copper plate 21;

Plant a plurality of copper pillars 22 on the provided copper plate 21;

providing a substrate 23, and connecting the copper column 22 to the substrate 23;

Plastic sealing the copper pillars 22 between the substrate 23 and the copper plate 21 to form a plastic sealing layer 24 covering the copper pillars 22;

removing the copper plate 21 by a grinding process to expose the copper post 22;

Provide a plurality of chips 25, and mount the provided chips 25 on the copper pillars 22;

Dot heat dissipating glue on the chip 25 to form a heat dissipating glue layer 26;

Coating insulating glue on the side of the chip 25 to form an insulating glue layer 28 on the corresponding plastic sealing layer 24 and attached to the chip 25;

Solder balls 231 are planted on the back of the substrate 23 to complete the package.

When mounting the chip 25 , the chip 25 is placed on the corresponding copper pillar 22 and the plastic encapsulation layer 24 , and the pins on the chip 25 are electrically connected to the corresponding copper pillar 22 .

Further, it also includes: providing a heat sink 27 , covering the heat sink 27 on the insulating adhesive layer 28 and the heat dissipation adhesive layer 26 , and pasting and fixing the insulating adhesive layer 28 and the heat dissipation adhesive layer 26 .

Still further, the provided heat sink 27 includes a top plate covered on the insulating adhesive layer 28 and the heat dissipation adhesive layer 26 and four side plates connected to the top plate;

When disposing the heat sink 27, the heat sink 27 is covered and fastened on the insulating adhesive layer 28 and the heat dissipation adhesive layer 26, and the four side plates of the heat sink 27 are pasted on the corresponding sides of the insulating adhesive layer and the plastic sealing layer.

Still further, when planting the copper pillars 22 on the copper plate 21 , the distance between two adjacent copper pillars 22 should be less than 60 um.

Still further, after the chip 25 is mounted, wire bonding is performed on the chip 25 .

The present invention has been described in detail above with reference to the embodiments of the accompanying drawings, and those skilled in the art can make various changes to the present invention according to the above description. Therefore, some details in the embodiments should not be construed as limiting the present invention, and the present invention will take the scope defined by the appended claims as the protection scope of the present invention.

Claims (10)

1. A multi-chip arrangement packaging method is characterized by comprising the following steps:

providing a copper plate;

planting a plurality of copper columns on the provided copper plate;

providing a substrate and connecting the copper column on the substrate;

carrying out plastic packaging on the copper column between the substrate and the copper plate to form a plastic packaging layer for coating the copper column;

removing the copper plate by using a grinding process to expose the copper pillars;

providing a plurality of chips, and mounting the provided chips on the copper columns;

dispensing heat dissipation glue on the chip to form a heat dissipation glue layer;

coating insulating glue on the side part of the chip to form an insulating glue layer which is positioned on the corresponding plastic sealing layer and is attached to the chip;

and (5) planting solder balls on the back surface of the substrate, thereby completing packaging.

2. The multi-chip arrangement package method of claim 1, further comprising:

and providing a radiating fin, and covering the radiating fin on the insulating adhesive layer and the radiating adhesive layer, and adhering and fixing the radiating fin and the insulating adhesive layer and the radiating adhesive layer.

3. The multi-chip arrangement package method of claim 2 wherein the heat sink provided includes a top plate overlying the insulating glue layer and the heat sink glue layer and four side plates connected to the top plate;

when the radiating fins are arranged, the radiating fins are covered and buckled on the insulating adhesive layer and the radiating adhesive layer, and the four side plates of the radiating fins are attached to the side parts corresponding to the insulating adhesive layer and the plastic sealing layer.

4. The multi-chip arrangement package method of claim 1, wherein when copper pillars are planted on the copper plate, a spacing between two adjacent copper pillars is smaller than 60um.

5. The multi-chip arrangement package method of claim 1, wherein after the chips are mounted, wire bonding is performed on the chips.

6. A multi-chip arrangement package structure, comprising:

a substrate;

the copper columns are connected to the substrate, and copper plates capable of being removed through grinding are connected to the tops of the copper columns;

a plastic package layer which is formed between the substrate and the copper plate and wraps the copper column;

a plurality of chips mounted on the copper pillars exposed by polishing the copper plate;

a heat dissipation adhesive layer arranged on the chip;

the insulating adhesive layer is arranged on the side part of the chip and positioned above the corresponding plastic sealing layer;

and the solder balls are arranged on the back surface of the substrate.

7. The multi-chip arrangement package structure of claim 6 further comprising a heat sink overlying the insulating glue layer.

8. The multi-chip arrangement package structure of claim 7, wherein the heat sink comprises a top plate covering the insulating glue layer and the heat sink glue layer, and four side plates vertically connected to the top plate, and the four side plates are attached to the corresponding side portions of the insulating glue layer and the plastic layer.

9. The multi-chip arrangement package of claim 8 wherein a spacing between two adjacent copper pillars is less than 60um.

10. The multi-chip arrangement package structure of claim 6, further comprising bond wires connected to the chip.