CN116489063A - Method, device, equipment and medium for monitoring switch hardware reset - Google Patents
Method, device, equipment and medium for monitoring switch hardware reset Download PDFInfo
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- CN116489063A CN116489063A CN202310561298.2A CN202310561298A CN116489063A CN 116489063 A CN116489063 A CN 116489063A CN 202310561298 A CN202310561298 A CN 202310561298A CN 116489063 A CN116489063 A CN 116489063A
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- 238000012544 monitoring process Methods 0.000 title claims abstract 4
- 230000002159 abnormal effect Effects 0.000 claims 1
- 230000000977 initiatory effect Effects 0.000 claims 1
- 238000012806 monitoring device Methods 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0631—Management of faults, events, alarms or notifications using root cause analysis; using analysis of correlation between notifications, alarms or events based on decision criteria, e.g. hierarchy, tree or time analysis
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/085—Retrieval of network configuration; Tracking network configuration history
- H04L41/0859—Retrieval of network configuration; Tracking network configuration history by keeping history of different configuration generations or by rolling back to previous configuration versions
- H04L41/0863—Retrieval of network configuration; Tracking network configuration history by keeping history of different configuration generations or by rolling back to previous configuration versions by rolling back to previous configuration versions
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Debugging And Monitoring (AREA)
Abstract
The embodiment of the specification discloses a method, a device, equipment and a medium for monitoring switch hardware reset, which comprise the following steps: when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device; reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal; and judging the reset condition of the switch hardware according to the state result. The embodiment of the specification is based on the existing programmable logic device, and can monitor and record the reset condition of the hardware of the switch with low cost and high reliability.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a medium for monitoring hardware reset of a switch.
Background
Switch hardware reset is a method of restoring a switch to factory default settings. Executing the switch hardware reset will delete all configuration information and revert to factory defaults.
During operation, the switch hardware is reset because of active or passive conditions. There are many cases of hardware reset of the switch, and the operating system is usually required to acquire the hardware reset. The prior art lacks an effective scheme for monitoring the hardware reset of the switch to determine the relevant condition of the hardware reset of the switch.
Disclosure of Invention
One or more embodiments of the present disclosure provide a method, an apparatus, a device, and a medium for monitoring hardware reset of a switch, which are used to solve the technical problems set forth in the background art.
One or more embodiments of the present disclosure adopt the following technical solutions:
one or more embodiments of the present disclosure provide a method for monitoring hardware reset of a switch, including:
when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device;
reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and judging the reset condition of the switch hardware according to the state result.
Optionally, before the specified input signal of the switch is accessed to a preset programmable logic device, the method further includes:
acquiring a reset state of the switch;
and determining the appointed input signal according to the reset state.
Optionally, the specified input signal includes one or more of a power-on signal generated by a power supply chip of the switch, a watchdog reset signal generated by a watchdog chip outside the switch, and a CPU reset signal generated by a CPU of the switch; wherein,,
the power-on signal of the power supply is connected to the programmable logic device, the power-on signal is low level when the power-on of the power supply chip of the switch is not completed, the reset condition is power-on reset, and the power-on signal is high level when the power-on of the power supply chip of the switch is completed;
the watchdog reset signal is accessed to the programmable logic device, the watchdog chip outside the switch is at a high level when normally running, the watchdog chip outside the switch is at a low level when abnormal, and the reset condition is that the watchdog is reset overtime;
and accessing the CPU reset signal into the programmable logic device, wherein the CPU reset signal is at a low level when the CPU of the switch actively initiates reset, the reset condition is CPU reset, and the CPU of the switch does not actively initiate reset, the reset condition is at a high level.
Optionally, the programmable logic device includes a first register;
after the reset condition of the switch hardware is determined according to the state result, the method further comprises:
and storing the reset condition through the first register.
Optionally, the method further comprises:
and inquiring the first register through a preset I2C bus when the CPU of the switch requests to inquire about the reset condition of the hardware of the switch.
Optionally, the programmable logic device includes a second register, where the second register is configured to store a reset reason corresponding to the reset condition.
Optionally, before the CPU of the switch initiates the reset, the method further includes:
writing a specified reset reason to the second register by a CPU of the switch;
after the switch hardware reset, the method further comprises:
judging whether the reset condition of the first register is CPU reset or not;
if yes, acquiring the appointed reset reason by reading the second register.
One or more embodiments of the present disclosure provide a device for monitoring hardware reset of a switch, the device including:
the access unit is used for accessing a specified input signal of the switch into a preset programmable logic device when the hardware of the switch is reset;
a state result unit, which reads the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and the judging unit judges the reset condition of the switch hardware according to the state result.
One or more embodiments of the present disclosure provide a switch hardware reset monitoring device, including:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device;
reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and judging the reset condition of the switch hardware according to the state result.
One or more embodiments of the present description provide a non-volatile computer storage medium storing computer-executable instructions that, when executed by a computer, enable:
when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device;
reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and judging the reset condition of the switch hardware according to the state result.
The above-mentioned at least one technical scheme that this description embodiment adopted can reach following beneficial effect:
the embodiment of the specification is based on the existing programmable logic device, and can monitor and record the reset condition of the hardware of the switch with low cost and high reliability.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some of the embodiments described in the present description, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:
fig. 1 is a flow diagram of a method for monitoring hardware reset of a switch according to one or more embodiments of the present disclosure;
fig. 2 is a schematic structural diagram of a hardware reset monitoring system of a switch according to one or more embodiments of the present disclosure;
fig. 3 is a schematic structural diagram of a hardware reset monitoring device of a switch according to one or more embodiments of the present disclosure;
fig. 4 is a schematic structural diagram of a hardware reset monitoring device of a switch according to one or more embodiments of the present disclosure.
Detailed Description
The embodiment of the specification provides a method, a device, equipment and a medium for monitoring switch hardware reset.
The monitoring of the hardware reset of the switch is not realized by a special chip, and the common practice is to judge the reset condition by a plurality of external logic devices and record the reset condition by software through a file system.
It should be noted that, the method of judging the reset condition by using a plurality of external logic devices and recording the reset condition by using the file system, on the one hand, the use of the external logic devices increases the PCB area, on the other hand, the method of recording the reset condition by software through the file system has limitations, and the hardware reset caused by the power failure of the device or the timeout of the external watchdog is hard to distinguish by the operating system.
Aiming at the defects of the existing scheme, the method for monitoring the replacement hardware reset based on the programmable logic device is provided, the function of monitoring and recording the switch reset can be added based on the existing programmable logic device, the cost is low, and the reliability is high.
In order to make the technical solutions in the present specification better understood by those skilled in the art, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present disclosure.
Fig. 1 is a schematic flow diagram of a method for monitoring switch hardware reset according to one or more embodiments of the present disclosure, where the flow may be performed by a switch hardware reset monitoring system. Some input parameters or intermediate results in the flow allow for manual intervention adjustments to help improve accuracy.
The method flow steps of the embodiment of the present specification are as follows:
s102, when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device.
S104, reading the state of the specified input signal through the programmable logic device to obtain a state result of the specified input signal.
S106, judging the reset condition of the switch hardware according to the state result.
In the embodiment of the present specification, the specified input signal may include one or more of a power-on signal generated by a power supply chip of the switch, a watchdog reset signal generated by a watchdog chip external to the switch, and a CPU reset signal generated by a CPU of the switch.
Reset of switch hardware is generally divided into three types: (1) a power-on reset generated by first powering up the device; (2) When the operating system is abnormal such as kernel crash, process deadlock and the like, the watchdog feeding monitoring process stops feeding dogs, and a watchdog chip initiates watchdog timeout reset; (3) hardware reset initiated actively by CPU.
It should be noted that when the switch hardware is reset, some symptoms and signs may appear, and the specific situation depends on the type and situation of the reset. For example:
and (5) power-on reset: when the switch is first powered on, the switch will perform a self-test and start-up procedure. During this time, the indicator light may flash and the switch may take several minutes to fully activate;
watchdog timeout reset: if the software or hardware of the switch fails, the watchdog timer may time out and trigger a reset, in which case it may see an indicator light flashing or hear signs of increased fan noise;
hardware reset initiated actively by CPU: if the administrator decides to restore the device to its factory default setting, a hardware reset may be performed manually, and before starting the reset, a confirmation dialog may be popped up to ask if this is indeed to be performed.
In this embodiment of the present disclosure, before a specified input signal of the switch is connected to a preset programmable logic device, a reset state of the switch may be obtained first; and determining the appointed input signal according to the reset state, for example, when the indicator light flashes, the appointed input signal can be determined to be a power-on signal.
It should be noted that, in the embodiment of the present disclosure, the power-on signal is connected to the programmable logic device, when the power-on of the power supply chip of the switch is not completed, the power-on reset is performed, and when the power-on of the power supply chip of the switch is completed, the power-on reset is performed.
It should be noted that, in the embodiment of the present disclosure, the watchdog reset signal is connected to the programmable logic device, and is at a high level when the watchdog chip outside the switch operates normally, and is at a low level when the watchdog chip outside the switch is abnormal, and the reset condition is that the watchdog resets overtime.
It should be noted that, in the embodiment of the present disclosure, the CPU reset signal is connected to the programmable logic device, where the level is low when the CPU of the switch actively initiates the reset, the reset condition is the CPU reset, and the level is high when the CPU of the switch does not actively initiate the reset.
According to the embodiment of the specification, the appointed input signal of the switch is connected to the programmable logic device, and the reset condition is further verified and determined, for example, the appointed input signal is a power-on signal, the power-on signal is connected to the programmable logic device, and if the power supply chip of the switch is at a low level, the reset condition can be determined to be power-on reset; if the power supply chip of the switch is at a high level, other input signals of the switch are required to be connected into the programmable logic device, and the reset condition is determined again.
It should be noted that, the specified input signal of the switch is connected to the programmable logic device, so that the reset condition can be determined more accurately, and more time is saved.
In addition, the embodiment of the specification can also directly connect the power-on signal, the watchdog reset signal and the CPU reset signal into the programmable logic device at the same time, and directly judge the level state of the corresponding hardware of the switch so as to determine the reset condition. For example, a power-on signal, a watchdog reset signal and a CPU reset signal are simultaneously connected into a programmable logic device, a power supply chip of the switch is at a high level, the watchdog chip is at a low level, a CPU of the switch is at a high level, and the reset condition of the switch is watchdog timeout reset.
In the embodiment of the present specification, the programmable logic device may include a first register; after the reset condition of the switch hardware is judged according to the state result, the reset condition can be stored through the first register.
Further, in the embodiment of the present disclosure, when the CPU of the switch requests to query the reset condition of the switch hardware, the first register may be queried through a preset I2C bus, so that the corresponding reset condition may be obtained.
In the embodiment of the present specification, the programmable logic device may further include a second register, where the second register is configured to store a reset reason corresponding to the reset condition. Before the CPU of the switch initiates reset, a specified reset reason can be written into the second register through the CPU of the switch, wherein the specified reset reason can comprise command line restart and high-temperature protection restart; after the hardware of the switch is reset, whether the reset condition of the first register is CPU reset or not can be judged; if yes, the second register is read to obtain the appointed reset reason, if not, the reset condition of the switch hardware is not CPU reset, and the reset condition needs to be determined again.
Further, the second register of the embodiment of the present specification may also store a reset reason other than the CPU reset.
It should be noted that fig. 2 is a schematic structural diagram of a hardware reset monitoring system of a switch provided in the embodiment of the present disclosure, and specifically:
1. the power Pgood signal is connected into a programmable logic device, the signal is generated by a power supply chip of the switch, the signal is low level when the power on of the switch is incomplete, and the signal is high level when the power on of the switch is completed, wherein the power Pgood signal is the power on signal;
2. the method comprises the steps that a watchdog Reset signal is connected into a programmable logic device, the signal is generated by an external watchdog chip, the signal is in a high level when a switch normally operates, when an operation system is abnormal and leads to a watchdog feeding process breakdown, the watchdog chip generates overtime Reset, the signal becomes low, and the watchdog Reset signal is a watchdog Reset signal;
3. the CPU Reset signal is generated by the CPU, and becomes low when the operating system actively initiates hardware Reset, wherein the CPU Reset signal is a CPU Reset signal;
4. the method comprises the steps of connecting three input signals of a power supply Pgood signal, a watchdog Reset signal and a CPU Reset signal into a programmable logic device;
5. an I2C slave device is realized in the programmable logic device and is connected to the CPU through an I2C bus, wherein the I2C slave device comprises a register A and a register B in the figure;
6. the programmable logic device reads the states of three input signals, judges the reset condition of the hardware of the switch, and stores the reset condition in a register A;
it should be noted that the above reset conditions include the following cases:
(1) If the power Pgood signal is low, register a is recorded as 0, i.e. the current switch is powered off and powered on, and a power-on reset is generated.
(2) If the power Pgood signal is high level and the watchdog Reset is low level, judging that the external watchdog has overtime Reset, and recording a register A as 1, namely, judging that the switch has overtime Reset of the watchdog;
(3) If the power Pgood signal is high level, the watchdog Reset is high level, the CPU Reset signal is low level, the register A is recorded as 2, namely the CPU actively initiates hardware Reset;
(4) In other cases, the value of register a remains unchanged;
7. after each time the operating system is started, the CPU queries the value of the register A through the I2C interface, and the last hardware reset condition can be obtained.
8. The programmable logic device provides a register B for recording specific reasons for actively initiating reset by the CPU, such as command line restart, high-temperature protection restart and the like, and the method is as follows:
(1) The default value of the register B is set to 0 after the programmable logic device is powered on;
(2) Before the CPU actively initiates the reset, writing a specific value into the register B, namely actively restarting the reason code;
(3) After the reset is completed, the software firstly reads the value of the register A, and if A is 2, then reads the value of the register B;
(4) And according to the value of the register B, searching the reason for the active reset of the system by comparing with the active reset reason code.
It should be noted that I2C is a communication protocol for transmitting data between Integrated Circuits (ICs). In I2C communication, each device is considered a master or slave. The master is responsible for issuing clock signals and initiating communications, while the slaves only respond to the commands of the master.
Fig. 3 is a schematic structural diagram of a hardware reset monitoring device of a switch according to one or more embodiments of the present disclosure, where the device includes: an access unit 302, a state result unit 304 and a decision unit 306.
An access unit 302, when the hardware of the switch is reset, accessing the specified input signal of the switch into a preset programmable logic device;
a state result unit 304, configured to read, by using the programmable logic device, a state of the specified input signal, and obtain a state result of the specified input signal;
and a determining unit 306 for determining the reset condition of the switch hardware according to the state result.
Fig. 4 is a schematic structural diagram of a hardware reset monitoring device of a switch according to one or more embodiments of the present disclosure, including:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device;
reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and judging the reset condition of the switch hardware according to the state result.
One or more embodiments of the present description provide a non-volatile computer storage medium storing computer-executable instructions that, when executed by a computer, enable:
when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device;
reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and judging the reset condition of the switch hardware according to the state result.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for apparatus, devices, non-volatile computer storage medium embodiments, the description is relatively simple, as it is substantially similar to method embodiments, with reference to the section of the method embodiments being relevant.
The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
The foregoing is merely one or more embodiments of the present description and is not intended to limit the present description. Various modifications and alterations to one or more embodiments of this description will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present description, is intended to be included within the scope of the claims of the present description.
Claims (10)
1. A method for monitoring hardware reset of a switch, the method comprising:
when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device;
reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and judging the reset condition of the switch hardware according to the state result.
2. The method of claim 1, wherein before said accessing the switch's designated input signal to a pre-set programmable logic device, the method further comprises:
acquiring a reset state of the switch;
and determining the appointed input signal according to the reset state.
3. The method of claim 1, wherein the specified input signal comprises one or more of a power-on signal generated by a power chip of the switch, a watchdog reset signal generated by a watchdog chip external to the switch, a CPU reset signal generated by a CPU of the switch; wherein,,
the power-on signal of the power supply is connected to the programmable logic device, the power-on signal is low level when the power-on of the power supply chip of the switch is not completed, the reset condition is power-on reset, and the power-on signal is high level when the power-on of the power supply chip of the switch is completed;
the watchdog reset signal is accessed to the programmable logic device, the watchdog chip outside the switch is at a high level when normally running, the watchdog chip outside the switch is at a low level when abnormal, and the reset condition is that the watchdog is reset overtime;
and accessing the CPU reset signal into the programmable logic device, wherein the CPU reset signal is at a low level when the CPU of the switch actively initiates reset, the reset condition is CPU reset, and the CPU of the switch does not actively initiate reset, the reset condition is at a high level.
4. The method of claim 3, wherein the programmable logic device comprises a first register;
after the reset condition of the switch hardware is determined according to the state result, the method further comprises:
and storing the reset condition through the first register.
5. The method according to claim 4, wherein the method further comprises:
and inquiring the first register through a preset I2C bus when the CPU of the switch requests to inquire about the reset condition of the hardware of the switch.
6. The method of claim 4, wherein the programmable logic device comprises a second register for storing a reset reason corresponding to the reset condition.
7. The method of claim 6, wherein prior to the CPU of the switch initiating a reset, the method further comprises:
writing a specified reset reason to the second register by a CPU of the switch;
after the switch hardware reset, the method further comprises:
judging whether the reset condition of the first register is CPU reset or not;
if yes, acquiring the appointed reset reason by reading the second register.
8. A switch hardware reset monitoring apparatus, the apparatus comprising:
the access unit is used for accessing a specified input signal of the switch into a preset programmable logic device when the hardware of the switch is reset;
a state result unit, which reads the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and the judging unit judges the reset condition of the switch hardware according to the state result.
9. A switch hardware reset monitoring device, comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device;
reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and judging the reset condition of the switch hardware according to the state result.
10. A non-transitory computer storage medium storing computer executable instructions that when executed by a computer enable:
when the hardware of the switch is reset, the appointed input signal of the switch is accessed to a preset programmable logic device;
reading the state of the appointed input signal through the programmable logic device to obtain a state result of the appointed input signal;
and judging the reset condition of the switch hardware according to the state result.
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| CN202310561298.2A CN116489063A (en) | 2023-05-16 | 2023-05-16 | Method, device, equipment and medium for monitoring switch hardware reset |
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