CN114443544B

CN114443544B - I2C module-based master-slave mode switching method and device

Info

Publication number: CN114443544B
Application number: CN202210340008.7A
Authority: CN
Inventors: 朱珂; 王盼; 刘长江; 姜海斌
Original assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Current assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Priority date: 2022-04-02
Filing date: 2022-04-02
Publication date: 2022-06-28
Anticipated expiration: 2042-04-02
Also published as: CN114443544A

Abstract

The invention provides a method and equipment for switching master-slave modes based on an I2C module, wherein the equipment comprises an I2C module, a master mode driving controller, a slave mode driving controller and a chip internal register which are integrated on a chip; the chip is connected with the slave equipment on the I2C bus through an I2C module; the chip at least comprises an IDLE state, a BOOT mode, a MASTER mode, an ARB _ WAIT state and a slave mode; based on an I2C interface, the I2C module is enabled to enter a MASTER mode or a BOOT mode, and accesses the slave device in the state of entering the MASTER mode or the BOOT mode, so that information interaction with the slave device is realized. This scheme possesses good performance and succinct structure, and the situation on probation of tape-out is good for the user can conveniently monitor the chip state more simply, and need not borrow other software drive and main mouthful equipment again, greatly reduced operating cost, improved the convenience of chip state control.

Description

I2C module-based master-slave mode switching method and device

Technical Field

The invention relates to the field of integrated circuit control, in particular to a method and equipment for controlling master-slave mode switching based on an I2C module, aiming at the electric digital data processing and control mode switching of a specific digital circuit.

Background

An I2C bus (Inter-Integrated Circuit bus) is used as a basic module of a chip and plays a very important role in chip applications. In order to facilitate the operation of the chip by the user, the I2C bus function point should be more robust and more convenient for the application of the chip.

In a conventional integrated circuit, the I2C module normally works in a slave mode, and an external host can monitor the chip through an I2C interface; in the chip power-on initialization stage, the I2C module can work in Boot mode, and load data in the EEPROM on the I2C bus to initialize the chip. In the prior art, when individual data in the EEPROM is to be modified, the EEPROM needs to be re-burned by software driver, and the I2C module cannot enter the master mode to read and write the EEPROM (or other slave devices) on the I2C bus by configuring the I2C module register through the I2C interface or other master ports.

At present, the I2C module does not implement any switching between master and slave modes and access the function of the slave device on the I2C bus through the configuration of the I2C interface, which greatly reduces the experience of using the chip by the user and increases unnecessary redundant operations for the user to monitor the chip.

Disclosure of Invention

In view of this, the present invention provides a method and an apparatus for switching between master mode and slave mode based on I2C module, which can enable the I2C module on the chip to enter the master mode and access the slave devices (such as a temperature sensor and an EEPROM) on the I2C bus only by using the I2C interface.

Specifically, the invention discloses the following technical scheme:

in one aspect, the invention provides a method for switching MASTER-slave modes based on an I2C module, which is applied to a chip, wherein the chip at least comprises an IDLE state, a BOOT mode, a MASTER mode, an ARB _ WAIT state and a slave mode; the IDLE state represents that the chip is in a slave mode and does not determine a next mode to be entered;

the method comprises the following steps:

after power-on or restarting, the chip enters an IDLE state and determines a next step mode to be entered, wherein the next step mode comprises a MASTER mode and a BOOT mode; the way to determine the next mode to enter is: the BOOT mode is selected to enter through the pin setting, and the slave mode after the IDLE state enters into the MASTER mode or the BOOT mode through the register data configuration mode; at the moment, the chip enters a state of selecting two modes after being started; when the module register of the chip I2C is configured to switch the master mode and the slave mode of the I2C module, the configuration may be performed by, for example, JTAG, PCIE, or the like, or the mode is selected as the BOOT mode through the external pin of the chip, and when the configuration is not performed similarly, a person skilled in the art knows that the slave mode will be entered after the IDLE state;

When entering a BOOT mode, if in a stage of sending a slave device address, comparing the sent slave device address data with data on an I2C bus, if the data are the same, then successfully arbitrating, and continuing BOOT operation, otherwise, if the arbitration fails, entering an ARB _ WAIT state, and performing arbitration waiting; if the peripheral address and/or data of the slave equipment to be accessed are/is compared with the data on the I2C bus after the slave equipment address sending stage, if the data are the same, the arbitration is successful, the BOOT operation is continued, otherwise, the BOOT loading transaction is aborted, and the IDLE state is entered; if the arbitration does not occur, entering an IDLE state after the BOOT loading is finished;

when entering a MASTER mode, if the slave equipment address data is transmitted in a stage of transmitting the slave equipment address, comparing the transmitted slave equipment address data with data on an I2C bus, if the data are the same, successfully arbitrating, and continuing to perform MASTER operation, otherwise, if the arbitration fails, entering an ARB _ WAIT state; if the peripheral address and/or data of the slave device to be accessed are/is compared with the data on the I2C bus after the slave device address sending stage, if the peripheral address and/or data of the slave device to be accessed are the same, arbitration is successful, and MASTER operation is continued, otherwise, if the arbitration fails, the transaction is aborted, and an IDLE state is entered; if the arbitration does not occur, entering an IDLE state after the transaction is finished;

When entering an ARB _ WAIT state, if entering from a BOOT mode, entering the BOOT mode again for retransmission after detecting a STOP signal; if entering from the MASTER mode, the STOP signal is detected and then the MASTER mode is entered again for retransmission; if the ARB _ WAIT state is overtime, the transaction is aborted and the IDLE state is entered;

when the system or the device runs, the STOP signal is sent on the I2C bus because other devices hung on the bus work or operate normally, therefore, in the ARB _ WAIT state, we can further control the waiting state by detecting the STOP signal on the I2C bus to ensure the effective sending of the retransmission data.

The STOP signal is a STOP signal on the I2C bus, namely a STOP signal; the ARB _ WAIT state is an arbitration waiting state; the MASTER mode corresponds to the main mode.

Preferably, in the IDLE state, when the chip is in the slave mode, the chip may perform the next selection to enter the MASTER mode or the BOOT mode, or perform no next selection to perform the subsequent operation when the chip is in the slave mode.

In the slave mode, an external master device operates the internal register of the chip through an I2C module, so that the state of the chip is monitored conveniently.

Preferably, the MASTER mode and the BOOT mode are implemented based on an on-chip I2C module to access a slave device through an I2C bus;

the slave offset address is 0 byte or 1 byte or 2 bytes; the data written and read in the MASTER mode and the BOOT mode can be controlled. The byte length of the written data and the read data may be set in advance, and may be, for example, 0, 1, 2, or the like.

Preferably, the slave device address, the slave device offset address, the control signal and the written data of the write operation in the MASTER mode are all stored in a chip internal register in advance, and then the chip internal register is configured to start a write transaction;

and the slave device address, the slave device offset address and the control signal of the read operation in the MASTER mode and the BOOT mode are stored in a chip internal register in advance, and then the chip internal register is configured to start a read transaction.

Preferably, in a MASTER mode or a BOOT mode, in order to further facilitate the implementation of the scheme of the present invention and implement the interaction of data between the MASTER device and the slave device, the driving between the I2C module and the I2C bus is implemented by a MASTER mode driving controller;

the master mode drive controller includes START, RESTART, SEND, ACK, REC, STOP states;

When there is a main mode transaction, entering a START state from an IDLE state;

in the START state, if the establishment and holding time conditions of the START state are met, entering a SEND state, otherwise, entering a STOP state;

in the SEND state, peripheral addresses and/or data of slave equipment to be accessed are sent and compared with data on an I2C bus, if the data are the same, arbitration is successful, the original mode operation is continued, otherwise, the STOP state is entered if the arbitration fails; if the preset amount of data is sent, entering an ACK state;

in the ACK state, if data transmission is completed or FF verification fails or NACK information is received or a timeout error occurs, entering a STOP state; based on the associated state condition control, entering into RESTART, REC or SEND state;

directly entering a SEND state after entering a RESTART state;

in the REC state, after receiving the preset amount of data, entering an ACK state;

when the STOP signal is detected, the STOP state is entered, and then the IDLE state is entered directly.

Preferably, the above-mentioned associated state condition control specifically includes:

after the MASTER mode read time sequence sends the peripheral address of the slave device, the slave device enters an ACK state, and then enters a RESTART state after a START signal is generated; sending the equipment address and the reading and writing zone bit, then entering an ACK state, and selecting to enter an REC or SEND state according to the reading and writing zone bit; and in the sending or receiving state, entering an ACK state after sending or receiving the preset amount of data, and continuing entering an REC or SEND state according to the sending or receiving state indication signal if the data is not sent or received.

Preferably, in the MASTER mode, the write operation timing sequence is:

after entering the corresponding mode, starting a time sequence in a START state;

then sending a slave equipment address and a writing flag bit, handshaking with the slave equipment, if matching is successful, returning an acknowledgement ack by the slave equipment, otherwise, entering a STOP state and ending the time sequence;

after matching is successful, sending a peripheral address of the slave equipment to be accessed; then sending the written data;

entering a STOP state after the data transmission is finished, and finishing the time sequence;

in the time sequence, after each preset amount of data is sent, the corresponding equipment returns a response ack, and the corresponding equipment is the master equipment or the slave equipment.

Preferably, in the MASTER mode or the BOOT mode, the read operation timing sequence is:

then sending the slave equipment address and the write flag bit, handshaking with the slave equipment, if matching is successful, returning an acknowledgement ack by the slave equipment, otherwise, entering a STOP state and ending the time sequence;

after matching is successful, sending a peripheral address of the slave equipment to be accessed; then sending a slave device address and a reading zone bit to the slave device, if matching is successful, returning an acknowledgement ack by the slave device, otherwise, entering a STOP state and ending the time sequence; after matching is successful and a response ack returned by the slave equipment is received, receiving data returned by the slave equipment;

After the data is received, the slave equipment sends a response nack, enters a STOP state after receiving the response nack, and ends the time sequence;

Preferably, in the slave mode, in order to further facilitate the implementation of the scheme of the present invention, and to implement the interaction of data between the master device and the slave device, the driving between the I2C module and the I2C bus is implemented by a slave mode driving controller;

the slave mode drive controller includes REC _ DEVICE, SEND _ DEVICE _ ACK, SEND _ DATA, REC _ ACK, REC _ DATA, SEND _ ACK states;

after entering the slave mode, when the START signal is detected, entering an REC _ DEVICE state;

in REC _ DEVICE state, after receiving slave address and read/write control bit, entering SEND _ DEVICE _ ACK state;

in the SEND _ DEVICE _ ACK state, if the slave DEVICE address is correct, replying to the response ACK; entering a SEND _ DATA state if the read enable is valid, and entering an REC _ DATA state if the write enable is valid;

entering an REC _ ACK state after transmitting a predetermined amount of DATA in a SEND _ DATA state;

in the REC _ ACK state, if receiving the response nack or sending the data completion, entering an IDLE state; if the DATA is continuously sent, the SEND _ DATA state is entered again;

In the REC _ DATA state, the SEND _ ACK state is entered after receiving a predetermined amount of DATA;

in the SEND _ ACK state, if an acknowledgement ACK is returned, the REC _ DATA state is entered again.

Preferably, in the slave mode, the write operation timing sequence is:

after the time sequence is started, the I2C module receives the address and the write flag bit of the slave device, handshakes with the master device, if matching is successful, the slave device sends a response ack, otherwise, the slave device sends a response nack;

after matching is successful and the slave equipment sends an acknowledgement ack, receiving a chip internal storage address to be accessed by the master equipment;

then, the slave device receives the data to be written by the master device, and the sequence is ended after the STOP signal of the master device is received;

in this time sequence, the slave device returns a response ack to the master device every time it receives a predetermined amount of data.

Preferably, in the slave mode, the read operation timing is:

after the time sequence is started, the slave equipment receives the address and the writing zone bit of the slave equipment, handshake with the master equipment is carried out, if matching is successful, the slave equipment sends a response ack, and if not, the slave equipment sends a response nack;

if the matching is successful and the slave equipment sends the response ack, receiving the internal storage address of the chip to be accessed by the master equipment;

secondly, receiving the address and the reading zone bit of the slave equipment sent by the master equipment again, if the matching is successful, sending a response ack by the slave equipment, sending internal storage data of the slave equipment to the master equipment, and if the matching is failed, reporting an error;

Sending data to a STOP signal of the received master device, and ending the time sequence;

In yet another aspect, the present invention further provides an I2C module-based device for master-slave mode switching, the device including an I2C module, a master mode driver controller, a slave mode driver controller, and an on-chip register, which are integrated on a chip;

the chip is connected with the slave device on the I2C bus through an I2C module; the chip at least comprises an IDLE state, an ARB _ WAIT state, a slave mode, a BOOT mode and a MASTER mode;

and based on the I2C interface, the I2C module is made to enter a slave mode or a MASTER mode or a BOOT mode, and accesses the slave device to realize information interaction with the slave device.

Preferably, the slave device address, the slave device offset address, the control signal and the written data of the MASTER mode write operation are all prestored in the internal register of the chip, and then the internal register of the chip is configured to start the write transaction in the MASTER mode;

the slave device address, the slave device offset address and the control signal of the read operation in the MASTER mode or the BOOT mode are pre-stored in an internal register of the chip, and then the internal register of the chip is configured to start the read transaction in the MASTER mode or the BOOT mode; the read data is stored in the internal register of the chip.

Preferably, the jump modes of the IDLE state, the BOOT mode, the MASTER mode, and the ARB _ WAIT state are as follows:

after power-on or restarting, the chip enters an IDLE state and determines a next step mode to be entered, wherein the next step mode comprises a MASTER mode and a BOOT mode; at the moment, the chip enters a state of selecting two modes after being started; the way to determine the next mode to enter is: the BOOT mode is selected to enter through the pin setting, and the slave mode after the IDLE state enters into the MASTER mode or the BOOT mode through the register data configuration mode; at this time, when the module register of the configuration chip I2C switches the master mode and the slave mode of the I2C module, the configuration can be performed in a manner of JTAG, PCIE, or the like, or the mode is selected as the BOOT mode through an external pin of the chip;

when entering a BOOT mode, if the slave device address data is transmitted in a stage of transmitting the slave device address, comparing the transmitted slave device address data with data on an I2C bus, if the data are the same, arbitrating successfully, and continuing BOOT operation, otherwise, if the arbitrating fails, entering an ARB _ WAIT state and arbitrating for waiting; if the peripheral address and/or data of the slave device to be accessed are/is compared with the data on the I2C bus after the slave device address sending stage, if the peripheral address and/or data of the slave device to be accessed are/is the same, arbitration is successful, BOOT operation is continued, otherwise, if the arbitration fails, BOOT loading transaction is aborted, and an IDLE state is entered; if the arbitration does not occur, entering an IDLE state after the BOOT loading is finished;

When entering a MASTER mode, if the slave equipment address data is transmitted in a stage of transmitting the slave equipment address, comparing the transmitted slave equipment address data with data on an I2C bus, if the data are the same, successfully arbitrating, and continuing to perform MASTER operation, otherwise, if the arbitration fails, entering an ARB _ WAIT state; if the slave equipment address is sent, comparing the peripheral address and/or data of the slave equipment to be sent and accessed with the data on the I2C bus, if the data are the same, the arbitration is successful, and the MASTER operation is continued, otherwise, if the arbitration fails, the transaction is aborted, and the IDLE state is entered; if the arbitration does not occur, the transaction enters an IDLE state after being completed;

when entering an ARB _ WAIT state, if entering from a BOOT mode, detecting a STOP signal and then entering the BOOT mode again for retransmission; if entering from the MASTER mode, the STOP signal is detected and then enters into the MASTER mode again for retransmission; if the ARB _ WAIT state is overtime, the transaction is aborted and an IDLE state is entered;

the STOP signal is a STOP signal; the ARB _ WAIT state is an arbitration waiting state; the MASTER mode corresponds to the MASTER mode.

Compared with the prior art, the technical scheme of the invention can realize that the I2C module can randomly switch master-slave modes, and research and development teams are already implemented on the FPGA in an engineering way, so that the scheme has good performance and a simple structure, and the condition of the tapestry trial is good; according to the scheme, the user experience is improved by a method of randomly switching the master-slave mode of the I2C interface configuration register, so that a user can monitor the state of the chip more conveniently and simply without other software drivers and main port equipment, the cost of daily operation is greatly reduced, and the convenience of monitoring the state of the chip is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a main state machine according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a master mode bottom drive controller according to an embodiment of the present invention;

FIG. 3 is a timing diagram illustrating the operation of the main mode write operation according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating the operation of the master mode read operation according to an embodiment of the present invention;

FIG. 5 is a timing diagram illustrating the operation of the slave device reading peripheral address 0 bytes in the master mode according to an embodiment of the present invention;

FIG. 6 is a slave mode bottom drive controller of an embodiment of the present invention;

FIG. 7 is a slave mode write operation timing sequence according to an embodiment of the present invention;

FIG. 8 is a timing diagram illustrating a slave mode read operation according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be appreciated by those of skill in the art that the following specific examples or embodiments are a series of presently preferred arrangements of the invention to further explain the principles of the invention, and that such arrangements may be used in conjunction or association with one another, unless it is expressly stated that some or all of the specific examples or embodiments are not in association or association with other examples or embodiments. Meanwhile, the following specific examples or embodiments are merely provided as the best mode for setting, and are not to be construed as limiting the scope of the present invention.

In a specific embodiment, as shown in fig. 1, the controller state machines of the MASTER mode and the Boot mode of the I2C module on the chip are also a mode of the MASTER mode, the MASTER Mode (MASTER) is a read-write operation timing sequence for starting the MASTER mode through manual configuration after the chip is powered on, and the Boot mode is a power-on self-start for automatically loading external storage data without manual configuration, and only a pin needs to be selected before the power on, that is, only a read operation timing sequence. The invention realizes the two modes together during the design of the scheme so as to realize the basic multiplexing of logic. The SLAVE mode (SLAVE) is that an external master device operates the internal registers of the chip through an I2C module, thereby being convenient for monitoring the state of the chip.

In this embodiment, in conjunction with fig. 1, the state machine jump conditions are as follows:

IDLE: the IDLE state is entered after power-up/restart of the chip, at which point it is further determined which of the different modes is selected to be entered: if the mode is selected to be the Boot mode through the external pins of the chip, entering the Boot mode; entering a MASTER mode (i.e., MASTER mode) if the chip registers are configured to enter the MASTER mode via the I2C interface; in summary, the manner in which the next mode to be entered is determined can be by the following method: the BOOT mode is selected to enter through the pin setting, and the slave mode after the IDLE state enters into the MASTER mode or the BOOT mode through the register data configuration mode;

the IDLE state may be understood as an initial state in the slave mode state without entering the master mode and the BOOT mode, and the state is truncated and maintained in this state, and at this time, the external device may also operate the internal register of the chip through the I2C module to monitor the state of the chip, so as to enter the slave mode state through the control of the external device to perform subsequent operations, which is not described herein again.

BOOT: when entering a BOOT mode, if the slave device address data is transmitted in a stage of transmitting the slave device address, the transmitted slave device address data is compared with the data on the I2C bus, if the data is the same, arbitration is successful, BOOT operation is continued, otherwise, arbitration fails, an arbitration waiting state (namely an ARB _ WAIT state) is entered, and arbitration waiting is performed; if the peripheral address and/or data of the slave device to be accessed are/is compared with the data on the I2C bus after the slave device address sending stage, if the peripheral address and/or data of the slave device to be accessed are/is the same, arbitration is successful, BOOT operation is continued, otherwise, if the arbitration fails, BOOT loading transaction is aborted, and an IDLE state is entered; if the arbitration does not occur, entering an IDLE state after the BOOT loading is finished;

MASTER: when entering a MASTER mode, if the slave equipment address data is transmitted in a stage of transmitting the slave equipment address, comparing the transmitted slave equipment address data with data on an I2C bus, if the data are the same, the arbitration is successful, the MASTER operation is continued, otherwise, the arbitration is failed, and an arbitration waiting state (namely an ARB _ WAIT state) is entered; if the peripheral address and/or data of the slave device to be accessed are/is compared with the data on the I2C bus after the slave device address sending stage, if the peripheral address and/or data of the slave device to be accessed are the same, arbitration is successful, and MASTER operation is continued, otherwise, if the arbitration fails, the transaction is aborted, and an IDLE state is entered; if the arbitration does not occur, the transaction enters an IDLE state after being completed;

ARB _ WAIT: in the ARB _ WAIT state, if the STOP signal enters from the BOOT state, the STOP signal enters the BOOT state again after being detected for retransmission; if the STOP signal enters the MASTER state, the STOP signal is detected and then enters the MASTER state again for retransmission; if the arbitration WAIT state (i.e., the ARB _ WAIT state) times out, the transaction is aborted and the IDLE state is entered.

For the STOP signal, in the ARB _ WAIT state of the present invention, the STOP signal on the I2C bus is detected, and when the system or the device is running, the transmission of the STOP signal on the I2C bus will be generated due to the normal operation or operation of other devices connected to the bus, so that in the ARB _ WAIT state, we can perform further control of the WAIT state by detecting the STOP signal on the I2C bus to ensure the effective transmission of the retransmitted data.

In a more preferred embodiment, the design of the main mode (i.e. MASTER mode) and the BOOT mode in the present invention is implemented based on the I2C module on the chip, and can be designed in the following preferred manner:

when the module I2C on the chip operates in the MASTER mode (i.e., MASTER mode), it has a function of accessing the slave devices on the I2C bus, and more specifically, in our design, the offset addresses of the slave devices may be 0, 1, or 2 bytes, the data written in the MASTER mode is controllable in 0-4 bytes, and the data read in the MASTER mode is controllable in 1-4 bytes.

The slave device address, the slave device offset address, the control signal and the written data of the write operation in the MASTER mode (namely, the MASTER mode) can be stored in a register in the chip in advance, and then the register in the chip is configured to start the write transaction in the MASTER mode; the slave device address, the slave device offset address and the control signal of the master mode read operation may also be stored in the chip internal register in advance, then the chip internal register is reconfigured to start the master mode read transaction, and the read data is also stored in the chip internal register.

The data processed in the logic of the I2C module is parallel data, while the data processed by the I2C bus is serial data, so that the data conversion is required for the interaction between the two, and the interaction with the data on the I2C bus needs the bottom layer drive controller to complete, as shown in fig. 2.

In connection with the preferred drive controller shown in fig. 2, the corresponding state machine jump condition can be set as follows:

IDLE: when a master mode transaction exists, entering a START state; in this scenario, the IDLE state may be considered as an initial state of the main mode;

START: if the establishment and the holding time of the START are met, entering a SEND state, and if the arbitration fails, entering a STOP state;

RESTART: after entering the RESTERT state, directly entering the SEND state;

SEND: in the state, peripheral addresses and/or data of slave equipment to be accessed are sent and compared with data on an I2C bus, if the data are the same, arbitration is successful, the original mode operation is continued, otherwise, if the arbitration is lost, the slave equipment directly enters a STOP state; if 8bit data is sent, entering an ACK state; the arbitration here is to arbitrate the state of the data bus, and if the output data is inconsistent with the I2C data bus, it indicates that the current transmission is not the present device, and it is considered as arbitration failure;

And ACK: if the data transmission is completed, the FF check fails, and NACK or overtime error is received, entering a STOP state; in the ACK state, the state can correspondingly enter a RESTART state, a REC state or a SEND state under the control of the conditions of other associated states;

here, the control by other relevant state conditions specifically includes: after a master mode reads a time sequence and sends a peripheral address of the slave equipment, the slave equipment enters an ACK state, a START signal exists, and then the slave equipment enters a RESTART state; sending the equipment address and the reading and writing zone bit, then entering an ACK state, and selecting to enter an REC or SEND state according to the reading and writing zone bit; and entering an ACK state after the preset amount of data is sent or received in a sending or receiving state, and continuing to enter an REC or SEND state according to a sending or receiving state indication signal if the data is not sent or received.

And (C) REC: in the state, after 8-bit data is received, an ACK state is entered;

STOP: when the STOP signal is detected, an IDLE state is entered.

In the above state machine design manner, the working timing of the master mode is shown in fig. 3 to 5, and may specifically be set as follows:

for the write operation timing sequence of the MASTER mode (i.e. MASTER mode), with reference to fig. 3, taking an example that 1-bit response is returned every time 8-bit data unit is sent, in the MASTER mode, in the START state, the timing sequence is started, then 7-bit slave device address and 1-bit write flag bit are sent to handshake with the slave device, and if matching is successful, the slave device returns response ack; then sending a peripheral address of the slave equipment to be accessed, wherein the peripheral address can be 0 byte, 1 byte or 2 bytes, and every 8-bit opposite side can return a 1-bit response ack; and finally, sending data to be written into the slave equipment, wherein the data can be set to be controllable in 0-4 bytes, and when the data is sent, the slave equipment returns a 1-bit response ack mode every time 8 bits of data are sent, and the time sequence is ended in a STOP state after the data is sent.

For the same read operation timing sequence of the MASTER mode (i.e., MASTER mode) or the BOOT mode, and with reference to fig. 4, similarly, taking an example that a 1-bit response is returned every time an 8-bit data unit is sent as an example, in the MASTER mode, in the START state, a read operation is started, then a 7-bit device address and a 1-bit write flag are sent to handshake with the slave device, if matching is successful, the slave device gives a response ack, and then sends a peripheral address of the slave device to be accessed, where the peripheral address may be 1 or 2 bytes; then, the 7-bit device address and the 1-bit reading flag bit are sent to the slave device again, if matching is successful, the slave device returns a response ack, and finally data returned by the slave device is received, wherein the data can be controlled by 1-4 bytes, and the master device sends the 1-bit response ack to the slave device every 8 bits sent to the master device; when the data reception is completed, the slave device ends the sequence in the STOP state after sending the response nack. In the BOOT mode, the timing of the read operation is the same as the master mode, but in the BOOT mode, the data returned by the slave device is received, and the byte number of the data can exceed 4 bytes, namely the number of the read bytes can be more than that in the master mode.

In a special scenario, as shown in fig. 5, when reading a slave device with a peripheral address of 0 byte in the master mode, the working timing sequence STARTs a read operation in the START state, then directly sends a 7-bit slave device address and a 1-bit read flag bit to handshake with the slave device, if matching succeeds, the slave device gives a response ack, and finally receives data returned by the slave device, where the data may be controllable with 1-4 bytes, and the slave device sends a 1-bit response ack every 8 bits, and after receiving, the slave device sends a response nack and then ends the timing sequence in the STOP state.

It should be noted that, in the above example, in a manner that each time 8bit data units are transmitted, the other party returns 1bit ack response, on the basis of this design, a person skilled in the art may perform other manners or settings on the length of the transmitted data unit and/or the length of the returned ack response, and these conventional adjustments should be regarded as falling within the protection scope of the present invention.

In a more preferred embodiment, a corresponding slave mode design is shown with reference to FIG. 6. The I2C module on the chip works in the slave mode, and the external host device can access the internal registers of the chip through the I2C module to complete the monitoring, configuration and debugging of the chip. The I2C module enters the slave mode, which is a mode that an external master device operates a register inside a chip through the I2C module, and the slave mode can be directly entered after power-on or restart through the selection of an external pin of the chip, so that the state of the chip is conveniently monitored.

The I2C module is used as a device address supporting 7 bits when in a slave mode, more chips can be mounted on the I2C bus, and different chips can be accessed through different device addresses. Similarly, the data processed by the I2C module from the mode logic is parallel data, and the interaction with the data on the I2C bus needs the underlying drive controller to complete.

In the embodiment shown in fig. 6, the corresponding state machine jump condition may be set as follows:

IDLE: detecting that the STOP signal enters an IDLE state; detecting that the START signal enters an REC _ DEVICE state;

REC _ DEVICE: after receiving a 7-bit DEVICE address and a 1-bit read-write control bit, entering a SEND _ DEVICE _ ACK state;

SEND _ DEVICE _ ACK: if the equipment address is correct, an ACK is replied; entering a SEND _ DATA state if the read enable is valid, and entering an REC _ DATA state if the write enable is valid;

SEND _ DATA: after 8bit data is sent, the REC _ ACK state is entered;

REC _ ACK: entering an IDLE state when receiving NACK or finishing data sending; if the DATA is continuously sent, the SEND _ DATA state is entered again;

REC _ DATA: after 8bit data is received, the state of SEND _ ACK is entered;

SEND _ ACK: if an ACK is replied, the REC _ DATA state is entered again.

The corresponding slave mode operation sequence, as shown in fig. 7-8, includes the following steps:

for the write operation sequence in the slave mode, as shown in fig. 7, the procedure is as follows: the method comprises the steps of receiving a START signal sent by a master device, starting a time sequence, receiving a 7-bit slave device address and a 1-bit writing flag bit by the slave device to handshake with the master device, if matching is successful, sending a response ack to the master device by the slave device, then receiving an internal storage address of a chip to be accessed by the master device, wherein the byte number of the internal storage address is determined by the master device, sending the 1-bit response ack by the slave device after every 8 bits, finally receiving data to be written by the master device, determining the byte number of the written data by the master device, and then receiving the data to be written by the slave device until the STOP signal of the master device finishes the time sequence.

For the read operation sequence in the slave mode, as shown in fig. 8, the process is: the slave device receives a START signal sent by the master device, STARTs a time sequence, then receives a 7-bit device address and a 1-bit writing flag bit sent by the master device, carries out handshake with the master device, if the matching is successful, the slave device sends an acknowledgement ack to the master device and then receives the chip internal storage address to be accessed by the master device, the byte number of the internal storage address is determined by the master device, the slave device sends 1-bit acknowledgement ack to the master device when receiving 8-bit data, and then receives the 7-bit device address and 1-bit reading flag bit sent by the master device again, if so, the slave device sends an acknowledgement ack to the master device, and finally the slave device sends the internally stored data, the number of bytes of the data is determined by the master device, the slave device receives 1-bit acknowledgement ack from the master device when sending every 8-bit data, and the data is sent until the STOP signal of the master device finishes the time sequence.

It should be noted that, in the above example, in a manner that each time 8bit data units are transmitted, the other party returns a 1bit ack response, and those skilled in the art may perform other manners or settings of the data length on the basis of this design on the length of the transmitted data units and/or the length of the returned ack response, and these conventional adjustments should all be regarded as falling within the protection scope of the present invention.

Furthermore, it should be further noted that the method for switching between master mode and slave mode based on the on-chip I2C module provided in the above embodiments of the present invention is not limited to be implemented in a chip or a conventional integrated circuit, but the chip of the present invention encompasses a conventional integrated circuit, a system on a chip or an integrated circuit assembly, or a circuit device capable of implementing the specific method of the present invention, and therefore, the use of the method in other types of circuit devices should be considered to fall within the scope of the present invention.

In yet another embodiment, the present solution may be implemented by a device, that is, a device for switching between master mode and slave mode based on an I2C module, where the device includes an I2C module, a master mode driver controller, a slave mode driver controller, and an on-chip register, which are integrated on a chip;

the chip is connected with the slave equipment on the I2C bus through an I2C module; the chip at least comprises an IDLE state, an ARB _ WAIT state, a slave mode, a BOOT mode and a MASTER mode;

In order to implement the device functions of the present invention more conveniently, in a further optimized embodiment, the slave device address, the slave device offset address, the control signal, and the written data of the MASTER mode write operation are all pre-stored in the internal register of the chip, and then the internal register of the chip is configured to start the write transaction in the MASTER mode; the slave device address, the slave device offset address and the control signal of the read operation in the MASTER mode and the BOOT mode are pre-stored in an internal register of the chip, and then the internal register of the chip is configured to start the read transaction in the MASTER mode and the BOOT mode; the read data is stored in the internal register of the chip. The reading operation of the BOOT mode is controlled by a pin, and the power is automatically started.

after power-on or restarting, the chip enters an IDLE state and determines a next step mode to be entered, wherein the next step mode comprises a MASTER mode and a BOOT mode; at the moment, the chip enters a state of selecting two modes after being started; when the module register of the configuration chip I2C switches the master mode and the slave mode of the I2C module, the configuration can be performed in a JTAG mode, a PCIE mode and other modes, or the mode is selected as a BOOT mode through an external pin of the chip;

When entering a BOOT mode, if the arbitration fails in a slave device address sending stage, entering an ARB _ WAIT state and performing arbitration waiting; if the arbitration fails after the slave equipment address sending stage, the BOOT loading transaction is aborted and the IDLE state is entered; if the arbitration does not exist, entering an IDLE state after the BOOT loading is finished;

when entering a MASTER mode, if the arbitration fails in a slave equipment address sending stage, entering an ARB _ WAIT state; if the arbitration fails after the slave equipment address sending stage, the transaction is aborted and an IDLE state is entered; if not, the transaction enters an IDLE state after being completed;

when entering an ARB _ WAIT state, if entering from a BOOT mode, detecting a STOP signal and then entering the BOOT mode again for retransmission; if entering from the MASTER mode, the STOP signal is detected and then enters into the MASTER mode again for retransmission; if the arbitration is overtime, the transaction is aborted and an IDLE state is entered;

In different states of each mode, in a specific implementation of data interaction operations such as reading and writing between the master device and the slave device, the device may perform a method for switching between master and slave modes based on the I2C module as provided in this specification, and details are not described here.

Furthermore, in a more preferred embodiment, the device may comprise respective modules to perform each or several steps of the above-described method of on-chip I2C module master-slave mode switching. Thus, each step or several steps of the above described embodiments may be performed by a respective module, and the device may comprise one or more of these modules. The modules may be one or more hardware modules specifically configured to perform the respective steps, or implemented by a processor configured to perform the respective steps, or stored within a computer-readable medium for implementation by a processor, or by some combination.

The device utilizes the I2C bus architecture to enable data interaction with the slave device. The bus architecture may include any number of interconnecting buses and bridges depending on the specific application of the hardware and the overall design constraints. The bus connects together various circuits including one or more processors, memories, and/or hardware modules. The bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, external antennas, and the like.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present disclosure includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of implementation of the present disclosure. The processor performs the various methods and processes described above. For example, method embodiments in the present scheme may be implemented as a software program tangibly embodied in a machine-readable medium, such as a memory. In some embodiments, some or all of the software program may be loaded and/or installed via memory and/or a communication interface. When the software program is loaded into memory and executed by a processor, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform one of the methods described above by any other suitable means (e.g., by means of firmware).

The logic and/or steps represented in the flowcharts or otherwise described herein may be embodied in any readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for switching MASTER-slave mode based on I2C module is applied to chip, and is characterized in that the chip at least comprises IDLE state, BOOT mode, MASTER mode, ARB _ WAIT state, slave mode; the IDLE state represents that the chip is in a slave mode and does not determine a next mode to be entered; the method comprises the following steps:

After the chip is powered on or restarted, the chip enters an IDLE state and determines a next step mode to be entered, wherein the next step mode comprises a MASTER mode and a BOOT mode;

the way to determine the next mode to enter is: directly selecting to enter a BOOT mode through pin setting, or entering a MASTER mode or a BOOT mode from a slave mode after an IDLE state through a register data configuration mode;

when entering a MASTER mode, if the slave equipment address data is transmitted in a stage of transmitting the slave equipment address, comparing the transmitted slave equipment address data with data on an I2C bus, if the data are the same, arbitrating successfully, and continuing to perform MASTER operation, otherwise, entering an ARB _ WAIT state if the arbitration fails; if the peripheral address and/or data of the slave device to be accessed are/is compared with the data on the I2C bus after the slave device address sending stage, if the peripheral address and/or data of the slave device to be accessed are the same, arbitration is successful, and MASTER operation is continued, otherwise, if the arbitration fails, the transaction is aborted, and an IDLE state is entered; if the arbitration does not occur, the transaction enters an IDLE state after being completed;

the STOP signal is a STOP signal on an I2C bus; the ARB _ WAIT state is an arbitration waiting state; the MASTER mode corresponds to a main mode;

the MASTER mode and BOOT mode are implemented based on an on-chip I2C module to access slave devices over an I2C bus;

the slave offset address is 0 byte or 1 byte or 2 bytes; the data written in and read out in the MASTER mode can be controlled; the data read by the BOOT mode is controllable;

in a MASTER mode or a BOOT mode, the driving between the I2C module and the I2C bus is realized by a MASTER mode driving controller;

In the SEND state, peripheral addresses and/or data of slave equipment to be accessed are sent and compared with data on an I2C bus, if the data are the same, arbitration is successful, the original mode operation is continued, otherwise, arbitration fails, and the slave equipment enters the STOP state; if the preset amount of data is sent, entering an ACK state;

in the ACK state, if data transmission is completed or FF verification fails or NACK information is received or a timeout error occurs, entering a STOP state; based on the associated state condition control, entering a RESTART state, a REC state or a SEND state;

after entering the RESTART state, directly entering a SEND state;

when the STOP signal is detected, entering a STOP state, and then directly entering an IDLE state;

in the slave mode, the drive between the I2C module and the I2C bus is realized by a slave mode drive controller;

after entering the slave mode, when a START signal is detected, entering an REC _ DEVICE state;

In the SEND _ DEVICE _ ACK state, if the slave DEVICE address is correct, replying an acknowledgement ACK; entering a SEND _ DATA state if the read enable is valid, and entering a REC _ DATA state if the write enable is valid;

in the SEND _ DATA state, after a predetermined amount of DATA is transmitted, entering the REC _ ACK state;

in the REC _ ACK state, if receiving the response nack or sending the data is completed, entering an IDLE state; if the DATA is continuously sent, the SEND _ DATA state is entered again;

2. The method according to claim 1, wherein the slave device address, the slave device offset address, the control signal, and the written data of the write operation in the MASTER mode are all stored in a chip internal register in advance, and then the chip internal register is configured to start a write transaction;

3. The method of claim 1, wherein in MASTER mode, the write operation timing is:

entering a STOP state after the data transmission is finished, and ending the time sequence;

in the time sequence, after each preset amount of data is sent, the corresponding equipment returns a response ack, and the corresponding equipment is slave equipment.

4. The method of claim 1, wherein in MASTER mode or BOOT mode, the read timing is:

in the time sequence, after each preset amount of data is sent, the corresponding equipment returns a response ack, and the corresponding equipment is the main equipment.

5. The method of claim 1, wherein in the slave mode, the write operation timing is:

then, the slave receives the data to be written by the master, and finishes the time sequence after receiving the STOP signal of the master;

6. The method of claim 1, wherein in the slave mode, the read operation timing is:

receiving the slave equipment address and the reading zone bit sent by the master equipment again, if the matching is successful, sending an acknowledgement ack by the slave equipment, sending internal storage data of the slave equipment to the master equipment, and if the matching is failed, reporting an error;

sending data to a received STOP signal of the master equipment, and ending the time sequence;

7. The device for switching the master-slave mode based on the I2C module is characterized by comprising an I2C module, a master mode driving controller, a slave mode driving controller and an on-chip register which are integrated on a chip;

the method for switching the MASTER-slave mode based on the I2C module according to any one of claims 1 to 6 is executed in a state that the I2C module enters the slave mode or the MASTER mode or the BOOT mode based on the I2C interface, the slave device is accessed, and information interaction with the slave device is realized.