CN116449245A - Burr detector - Google Patents

Abstract

The present invention provides a glitch detector, which includes a first logic circuit, a second logic circuit, a first capacitor and a second capacitor. A first logic circuit is connected between a supply voltage and a ground voltage and is configured to receive a first signal at a first node to generate a second signal to a second node. The second logic circuit is connected between the supply voltage and the ground voltage, and is used to receive the second signal at the second node to generate the first signal to the first node. A first pole of the first capacitor is coupled to the supply voltage, and a second pole of the first capacitor is coupled to the first node. A first electrode of the second capacitor is coupled to the ground voltage, and a second electrode of the second capacitor is coupled to the second node. The invention can improve the accuracy of burr detection.

Description

glitch detector

technical field

Embodiments of the invention generally relate to detection techniques, and more particularly, to glitch detectors with high reliability.

Background technique

Hackers inject power glitches into a chip to disrupt its operation, thereby implanting malware to gain control of the chip. In order to prevent the chip from being damaged due to fault injection such as power glitches, one or more glitch detectors are designed inside the chip to detect whether the chip has power glitches. If a power glitch is detected, the chip can take appropriate actions to avoid implanted with malware. However, conventional glitch detectors cannot accurately detect glitches.

Contents of the invention

In view of this, the following summary is illustrative only and not intended to be limiting in any way. That is, the following overview is provided to introduce the concepts, highlights, benefits and advantages of the novel and non-obvious technologies described herein. Selected embodiments are further described in the detailed description below. Accordingly, the following Summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used in determining the scope of the claimed subject matter.

The object of the present invention is to provide a glitch detector, which can improve the accuracy of glitch detection.

In a first aspect, the present invention provides a glitch detector, comprising: a first logic circuit, coupled between a power supply voltage and a ground voltage, for receiving a first signal at a first node to generate a second signal to a first Two nodes; a second logic circuit, coupled between the power supply voltage and the ground voltage, for receiving the second signal at the second node to generate the first signal to the first node; a first capacitor, The first pole of the first capacitor is coupled to the power supply voltage, the second pole of the first capacitor is coupled to the first node; and, the second capacitor, the first pole of the second capacitor is coupled to the ground voltage, the The second pole of the second capacitor is coupled to the second node.

In some embodiments, the glitch detector further includes: a warning signal generator, coupled to the first node or the second node, for according to the voltage level of the first signal or the voltage level of the second signal Determine whether an undervoltage glitch occurs on the power supply voltage to determine whether to output a warning signal.

In some embodiments, when no undervoltage glitch occurs on the power supply voltage, the first signal has a first logic value, and the second signal has a second logic value different from the first logic value; and, in the power supply After the voltage undervoltage spike passes, the warning signal generator determines whether the power supply voltage has overvoltage or undervoltage by detecting whether the first signal changes to the second logic value or whether the second signal changes to the first logic value glitch.

In some embodiments, the glitch detector further includes: at least one first discharge path, coupled to the first node, for selectively charging/discharging the charge of the first node; and, at least one second The discharge path, coupled to the second node, is used for selectively charging/discharging the charges of the second node.

In some embodiments, when an undervoltage spike occurs on the power supply voltage, the at least one first discharge path charges/discharges the charge on the first node, and the at least one second discharge path charges/discharges the charge on the second node. The charge is charged/discharged.

In some embodiments, the at least one first discharge path includes a first P-type transistor and a first N-type transistor, the first P-type transistor is used to selectively provide current between the supply voltage and the first node path, and the first N-type transistor is used to selectively provide a current path between the ground voltage and the first node.

In some embodiments, the at least one second discharge path includes a second P-type transistor and a second N-type transistor, the second P-type transistor is used to selectively provide current between the supply voltage and the second node path, and the second N-type transistor is used to selectively provide a current path between the ground voltage and the second node.

In some embodiments, each of the first P-type transistor, the first N-type transistor, the second P-type transistor, and the second N-type transistor is a diode-connected transistor.

In some embodiments, the first logic circuit and the second logic circuit include inverters, NAND gates, and/or, NOR gates.

In a second aspect, the present invention provides a glitch detector, comprising: a first logic circuit, coupled between a power supply voltage and a ground voltage, for receiving a first signal at a first node to generate a second signal to the first Two nodes; a second logic circuit, coupled between the power supply voltage and the ground voltage, for receiving the second signal at the second node to generate the first signal to the first node; at least one first a discharge path, coupled to the first node, for selectively charging/discharging the charge of the first node; and at least one second discharge path, coupled to the second node, for selectively charging The charge of the second node is charged/discharged.

In some embodiments, the glitch detector further includes: a warning signal generator, coupled to the first node or the second node, for according to the voltage level of the first signal or the voltage level of the second signal Determine whether an undervoltage glitch occurs on the power supply voltage to determine whether to output a warning signal.

In some embodiments, when no undervoltage glitch occurs on the power supply voltage, the first signal has a first logic value, and the second signal has a second logic value different from the first logic value; and, in the power supply After the voltage undervoltage spike passes, the warning signal generator determines whether the power supply voltage has overvoltage or undervoltage by detecting whether the first signal changes to the second logic value or whether the second signal changes to the first logic value glitch.

In some embodiments, when an undervoltage spike occurs on the power supply voltage, the at least one first discharge path charges/discharges the charge on the first node, and the at least one second discharge path charges/discharges the charge on the second node. The charge is charged/discharged.

In some embodiments, the at least one first discharge path includes a first P-type transistor and a first N-type transistor, the first P-type transistor is used to selectively provide current between the supply voltage and the first node path, and the first N-type transistor is used to selectively provide a current path between the ground voltage and the first node.

In some embodiments, the at least one second discharge path includes a second P-type transistor and a second N-type transistor, the second P-type transistor is used to selectively provide current between the supply voltage and the second node path, and the second N-type transistor is used to selectively provide a current path between the ground voltage and the second node.

In some embodiments, each of the first P-type transistor, the first N-type transistor, the second P-type transistor, and the second N-type transistor is a diode-connected transistor.

In some embodiments, the first logic circuit and the second logic circuit include inverters, NAND gates, and/or, NOR gates.

These and other objects of the present invention will become apparent to those skilled in the art after reading the following detailed description of the preferred embodiment shown in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the drawings.

Description of drawings

The drawings (where like numerals indicate like components) illustrate embodiments of the invention. The accompanying drawings are included to provide a further understanding of the embodiments of the present disclosure and are incorporated in and constitute a part of the embodiments of the present disclosure. The drawings illustrate implementations of the embodiments of the disclosure and, together with the description, serve to explain principles of the embodiments of the disclosure. It is to be understood that the drawings are not necessarily to scale as some components may be shown out of scale from actual implementation to clearly illustrate the concepts of the disclosed embodiments.

FIG. 1A is a schematic diagram of a glitch detector according to an embodiment of the present invention.

FIG. 1B is a schematic diagram of a glitch detector according to an embodiment of the present invention.

Fig. 1C is a schematic diagram of a glitch detector according to an embodiment of the present invention.

Figure 2 shows that the discharge path of the glitch detector can shorten the reset time when a brown-out glitch occurs.

Fig. 3 is a schematic diagram of a glitch detector according to an embodiment of the present invention.

FIG. 4 illustrates that a capacitor can pull signal Vm high and signal Vmb low after a brown-out glitch, according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a glitch detector according to an embodiment of the present invention.

In the following detailed description, for the purpose of illustration, many specific details are set forth so that those skilled in the art can more thoroughly understand the embodiments of the present invention. It should be apparent, however, that one or more embodiments may be practiced without these specific details, that different embodiments may be combined as desired, and that the embodiments should not be limited to those illustrated in the figures.

Detailed ways

The following description is a preferred embodiment of the present invention, which is only used to illustrate the technical features of the present invention, but not to limit the scope of the present invention. While certain terms are used throughout the specification and claims to refer to specific elements, those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, the specification and claims do not use the difference in name as the way to distinguish components, but use the difference in function of the components as the basis for the difference. The terms "element", "system" and "apparatus" used in the present invention may be a computer-related entity, where the computer may be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" mentioned in the following description and claims are open terms, so they should be interpreted as "including, but not limited to...". Also, the term "coupled" means an indirect or direct electrical connection. Therefore, if it is described that a device is coupled to another device, it means that the device may be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

Wherein, unless otherwise indicated, corresponding numerals and symbols in different figures of each figure generally refer to corresponding parts. The drawings are drawn to clearly illustrate relevant parts of the embodiments and are not necessarily drawn to scale.

The term "basically" or "approximately" used herein means that within an acceptable range, those skilled in the art can solve the technical problem to be solved and basically achieve the technical effect to be achieved. For example, "approximately equal to" refers to a method acceptable to technicians with a certain error from "exactly equal to" without affecting the correctness of the result.

FIG. 1A is a schematic diagram of a glitch detector 100 according to an embodiment of the present invention. As shown in FIG. 1A, a glitch detector (for example, a latch-type glitch detector) 100 includes a latch, wherein the latch generates signals Vm and Vmb at nodes N1 and N2, respectively. The present invention Whether a power glitch has occurred can be determined according to the signals Vm and/or Vmb at the nodes N1 and/or N2 of the latch, that is, the latch is used to present a detection result indicating a power glitch. For example (see FIG. 2), the signal Vm has a low level and the signal Vmb has a high level before a power glitch occurs, and after a power glitch occurs (for example, the glitch causes the power supply voltage VDD to drop to the ground voltage VSS, such as 0V) , the signal Vmb will decrease, and when the signal Vmb decreases to close to Vm (that is, Vmb and Vm are basically the same/equal), if the power supply voltage VDD returns to normal, the inverters 310 and 320 will work normally, and Vm will probabilistically (for example , 50%) becomes a high level, correspondingly, if Vm is a high level, then Vmb is a low level, thus, when the power supply voltage VDD returns to normal, it can be known whether a power glitch has just occurred according to the signals Vm and Vmb . In one example, the latch includes two logic circuits (eg, inverters 110 and 120 connected in a latch-type fashion), which in this embodiment are connected as inverters (NOT gates) , NOT gate) 110 and 120 are described as examples, but the present invention is not limited thereto. For example, as shown in FIG. 1B and FIG. 1C, the latch may also be realized by logic circuits such as a NAND gate (NAND) and a NOR gate (NOR). In the example of FIG. 1B and FIG. 1C, it can be understood that The signals SET and RESET are reset/set signals. In the exemplary embodiment of FIG. 1A , each of the inverter 110 and the inverter 120 can be connected between a supply voltage (supply voltage, which can also be described as "supply voltage") VDD and a ground voltage (ground voltage) by using The P-type transistor and the N-type transistor between VSS are realized, and the inverter 110 is used for (isconfigured to, can also be described as " being configured to ") Receive the signal Vm at the node N1 to generate the signal Vmb at the node N2, The inverter 120 is used to receive the signal Vmb at the node N2 to generate the signal Vm at the node N1. In addition, the glitch detector 100 also includes multiple (eg, "four" shown in FIG. 1A ) discharging paths, and the discharging paths can be controlled by using (eg, diode-connected, ie, transistors) terminal (such as gate terminal) and source terminal coupled together) P-type transistors MP1, MP2 and (for example, diode-connected) N-type transistors MN1 and MN2, wherein the P-type transistor MP1 is used for power supply voltage A current path (current path, which can also be described as a "current path") is selectively provided between VDD and the node N1. The P-type transistor MP2 is used to selectively provide a current path between the power supply voltage VDD and the node N2. The N-type The transistor MN1 is used to selectively provide a current path between the node N1 and the ground voltage, and the N-type transistor MN2 is used to selectively provide a current path between the node N2 and the ground voltage. For example, in normal conditions (eg, when no power glitches occur on the supply and ground voltages), transistors MP1, MP2, MN1, and MN2 are off, and the parasitic diodes (also described as "body diodes") within these transistors are off. ”) are also non-conductive, so that transistors MP1, MP2, MN1 and MN2 do not provide a current path between the corresponding nodes. When a power glitch occurs at the supply voltage VDD and/or the ground voltage VSS (eg, an undervoltage glitch at the supply voltage VDD causes the supply voltage VDD to drop, specifically, eg, drop below the threshold voltage Vth of the turn-on transistor and below) , at this time, on the one hand, the voltage of the signal Vmb at the node N2 is reduced due to the effect of the parasitic diode in the latch (for example, the parasitic diode/body diode of the transistor in the inverter), on the other hand, the voltage at the node N2 The voltage of the signal Vmb also forms a discharge path/current path/current from the second node to the power supply voltage VDD due to the effect of the parasitic diode/body diode between the drain (drain) and the source (source) of the P-type transistor MP2 path, so that the voltage of the second node N2 is lowered faster (it can be seen from the graph shown in FIG. , the voltage of the signal Vmb drops faster), that is, it can reach the potential substantially the same as Vm in a shorter time, so that the reset time is shorter, and the occurrence of the glitch can be detected more accurately. It should be noted that the present invention is not limited to detecting power supply glitches on the power supply voltage VDD, and can also be used to detect glitches appearing on the ground voltage VSS (for example, glitches that cause the voltage of the ground voltage VSS to rise). In some cases, The glitch may even cause the potential of the ground voltage VSS to be higher than the potential of the power supply voltage VDD, or the undervoltage glitch may cause the power supply voltage VDD to drop a lot or even drop below the ground voltage VSS. Understandably, as shown in FIG. 2, Vm=0 at the beginning, therefore, the parasitic capacitance between VDD and Vm has the voltage of VDD, and the voltage of the parasitic capacitance between Vm and VSS is 0; when a glitch occurs, VSS is higher than VDD , the voltage of Cvdd-vm (the parasitic capacitance between VDD and Vm) will decrease, and the voltage of Cvss-Vm (the parasitic capacitance between Vm and VSS) will increase. Therefore, the voltage increase can be expressed as charging, and the voltage decrease can be expressed as charging. Appears as discharge. For example, in some embodiments, when a power supply glitch occurs at the supply voltage VDD causing the supply voltage VDD to drop and/or a glitch occurs at the ground voltage VSS causing the ground voltage VSS to rise (e.g., these glitches cause the voltage level at the supply voltage VDD to lower than the voltage level of the ground voltage VSS), on the one hand, the voltage of the signal Vmb at the node N2 is reduced due to the effect of the parasitic diode in the latch (for example, the parasitic diode/body diode of the transistor in the inverter), and on the other hand On the one hand, the voltage of the signal Vmb at the node N2 is also lowered faster due to the parasitic diode/body diode between the drain and the source of the P-type transistor MP2, and the voltage level of the ground voltage VSS is lowered due to the glitch. The level is higher than the voltage level of the power supply voltage VDD, so that the transistor MP2 is turned on (at this time, the voltage of the terminal connected to the node N2 of the transistor MP2 is higher than the voltage of its control terminal, thus, the MP2 is turned on, that is, the transistor MP2 is turned on On-resistance), so the voltage of the signal Vmb at the node N2 can be lowered faster; at the same time, because the glitch makes the voltage of the ground voltage VSS higher than the voltage of the power supply voltage VDD at this time, the transistor MN2 is turned on (that is, the transistor MN2 MN2 presents as an on-resistance), thereby forming a discharge path from the ground voltage VSS to the power supply voltage VDD via the second node N2, so that the signal Vmb of the second node N2 can be approached to the signal Vm of the first node N1 faster; similar Ground, due to the glitch, the voltage of the ground voltage VSS is higher than the voltage of the power supply voltage VDD, so that the transistors MN1 and MP1 are both turned on, that is, a current path from the ground voltage VSS to the power supply voltage VDD via the first node N1 is formed, and finally, Vm and Vmb will reach essentially the same potential. It can be seen that the transistors MP1/MP2/MN1/MN2 behave as open or provide a current path during circuit operation depending on the actual voltage conditions of the circuit (for example, parasitic diodes in the transistors are turned on and/or the transistors are turned on) , that is, the current path can be selectively provided autonomously, and the reset time can be shortened without additional control by the control signal and/or the control circuit, so that the glitch can be detected more accurately. For example, when no power glitch occurs, the current path is not connected; when a power glitch occurs, at least one current path (such as the current path where MP2 is located) is automatically connected, for example, when a power glitch occurs but the power voltage In the example where the potential of VDD is still higher than the ground voltage VSS, the current path where MP2 is located is automatically turned on (for example, the current path from node N2 to the power supply voltage VDD is formed through the parasitic diode in MP2), and for another example, when the power supply In an example where the potential of the ground voltage VSS becomes higher than the power supply voltage VDD despite the glitch, the current paths where MP1 , MP2 , MN1 , and MN2 are located are all automatically turned on. Therefore, in the embodiment of the present invention, the diode-connected transistors MP1, MN1 and MP2, MN2 as shown in FIG. Nodes N1 and N2 are charged/discharged. It should be noted that the embodiments of the present invention should not be limited to the four discharge paths shown in the figure. For example, in some embodiments, only P-type transistor MP2 may be included, and in other embodiments, P-type transistor MP2 may be included. Transistor MP2 and N-type transistor MN2 and so on.

The glitch detector 100 is used to detect under-voltage glitches according to the voltage level (voltage level, which can also be described as “voltage level”) of the signal Vm or the signal Vmb, that is, the glitches that cause the power supply voltage VDD to drop A glitch, for example, is a power supply glitch that makes the power supply voltage VDD lower than the threshold voltage Vth that turns on the transistor (it can also be described as "the threshold voltage Vth of the transistor"). Specifically, when the power supply voltage VDD has a normal (normal) voltage level (ie, logic value "1") (ie, when there is no glitch on the power supply voltage VDD), the signal Vm is controlled to have a low voltage level (ie, logic value "0"), while the signal Vmb is controlled to have a high voltage level (ie, logic value "1"). Then, when the glitch detector 100 encounters (suffer, can also be described as "appear", "suffer", "encounter", etc.) an undervoltage glitch (for example, when a glitch occurs on the power supply voltage VDD so that the power supply voltage drops), the signal Vmb The voltage level will drop. Finally, when the power supply voltage VDD returns to the original (original) voltage level (that is, the normal voltage level under normal conditions, logic value "1"), the signal Vm has a certain probability (for example, 50%) to be high voltage level. Therefore, once the signal Vm has a high voltage level, the glitch detector 100 can determine that an undervoltage glitch occurs on the chip, and optionally, can further trigger a warning signal generator (warning signal generator) 130 to notify the processing circuit that the power supply voltage VDD occurs Undervoltage glitches, which in turn facilitate the processing circuitry to take some appropriate action. After the warning signal generator 130 notifies the processing circuit, a reset circuit (not shown) can control the signals Vm and Vmb to have a low voltage level and a high voltage level respectively, so as to determine the next under-voltage glitch.

In another embodiment, the warning signal generator 130 can be connected to the node N2, and when the signal Vmb becomes logic value “0”, the warning signal generator 130 is triggered to output the warning signal. Such alternative designs should fall within the scope of the present invention. It can be understood that when the power supply voltage VDD drops to a logic value "0" due to a power glitch, ideally, the signal Vmb will become a logic value "0" (that is, the same voltage as Vm), and at this time, due to the glitch, the The power supply voltage VDD is a logic value 0. Generally, the alarm signal generator 130 cannot work normally during the duration of the glitch. After the glitch has occurred"), the alarm signal generator 130 can know whether a glitch has just occurred according to the signal Vm and/or Vmb. For example, a glitch may be considered to have occurred if signal Vm is detected to be at a high level and/or Vmb is detected to be at a low level.

The accuracy of traditional glitch detectors in detecting glitches is not high, for example, they cannot detect short glitches (short glitches, that is, glitches with a short duration, eg, glitches at the level of nanoseconds (10 ⁻⁹ S)). In order to solve this problem, P-type transistors MP1, MP2 and N-type transistors MN1, MN2 are used in the glitch detector 100, so that the voltage of the second node and the first node can be closer to the same faster, that is, to reduce the response undervoltage The reset time of the glitch enables the glitch detector 100 to detect short glitches. In particular, referring to FIG. 2, if the glitch detector 100 does not have P-type transistors MP1, MP2 and N-type transistors MN1, MN2, when an undervoltage glitch occurs on the power supply voltage VDD, the glitch detector 100 needs a longer reset time to Make the voltage level of the signal Vmb close to/substantially equal to the voltage level of the signal Vm (assuming that the power supply voltage VDD drops to the ground voltage), and then, when the power supply voltage VDD returns to the original voltage level, the signal Vm can have a certain probability (such as , 50%) appear as a high voltage level. On the other hand, if the glitch detector 100 has P-type transistors MP1, MP2 and N-type transistors MN1, MN2 (these transistors are used to selectively control the nodes N1, N2 when a glitch occurs (such as an undervoltage glitch on the supply voltage VDD) charge/discharge, or described as "selectively forming a current path through the nodes N1, N2"), only a short reset time is required to make the voltage level of the signal Vmb close to the voltage level of the signal Vm. Therefore, the glitch detector 100 can detect short glitches, thereby improving the accuracy of glitch detection.

FIG. 3 is a schematic diagram of a glitch detector 300 according to an embodiment of the present invention. As shown in FIG. 3 , the glitch detector 300 includes a latch, and the latch includes two logic circuits (for example, two inverters connected in a latch type), and in this embodiment, the two logic circuits are inverters 310 and 320 . Each of the inverter 310 and the inverter 320 can be implemented by using a P-type transistor and an N-type transistor connected between a power supply voltage VDD and a ground voltage, and the inverter 310 is used to receive the signal Vm at the node N1. To generate the signal Vmb at the node N2, the inverter 320 is used to receive the signal Vmb at the node N2 to generate the signal Vm at the node N1. In addition, the glitch detector 300 further includes capacitors C1 and C2. The capacitor C1 is coupled between the power supply voltage VDD and the node N1, that is, one electrode of the capacitor C1 (one electrode, which can also be described as "one end") is coupled to the power supply voltage VDD, and the other pole (the other end) of the capacitor C1 is coupled to the Node N1. The capacitor C2 is coupled between the node N2 and the ground voltage, that is, one pole of the capacitor C2 is coupled to the ground voltage, and the other pole of the capacitor C2 is coupled to the node N2, wherein the capacitors C1 and C2 are intentionally set in the glitch detection In the device 300, the capacitors C1 and C2 are not parasitic capacitances.

In an example embodiment, the glitch detector 300 is used to detect the undervoltage glitch according to the voltage level of the signal Vm or the signal Vmb. Specifically, when the power supply voltage VDD has a normal voltage level (eg, in a normal situation where no glitch occurs), the signal Vm is controlled to have a low voltage level (ie, logic value "0"), and the signal Vmb is controlled to have a low voltage level (ie, logic value "0"). has a high voltage level (ie, logic value "1"). Then, when an undervoltage glitch occurs in glitch detector 300 (e.g., an undervoltage glitch occurs at supply voltage VDD), signal Vmb will drop to a voltage level close to supply voltage VDD (in the case of a glitch at supply voltage VDD) . Finally, when the power supply voltage VDD returns to the original voltage level, the signal Vm will have a high voltage level, and the signal Vmb will have a low voltage level. Therefore, once the signal Vm has a high voltage level, the glitch detector 300 can determine that the chip has an undervoltage glitch and trigger the alarm signal generator 330 to notify the processing circuit that the power supply voltage VDD has an undervoltage glitch. After the warning signal generator 330 notifies the processing circuit, the reset circuit (not shown) can respectively control the signals Vm and Vmb to have a low voltage level and a high voltage level to determine the next under-voltage glitch.

In another embodiment, the warning signal generator 330 can be connected to the node N2, and when the signal Vmb becomes logic value “0”, the warning signal generator 330 is triggered to output the warning signal. Such alternative designs should fall within the scope of the present invention.

As described in the Background of the Invention, conventional glitch detectors do not always output a warning signal when a power glitch occurs, that is, the signal Vm may still have a low voltage level after an undervoltage glitch passes, that is, the accuracy of detecting a power glitch not tall. In the embodiment of the present invention, if the undervoltage spike makes the power supply voltage lower than VDD/2, for example, more specifically, as long as the undervoltage spike makes the power supply voltage lower than the threshold voltage of the transistor in the inverter 310/320 (ie, the The inverter cannot work normally, that is, the undervoltage glitch will change the logic value of the inverter output), the capacitors C1 and C2 can ensure that the signal Vm always has a high voltage level after the undervoltage glitch. In particular, referring to FIG. 4, initially, the power supply voltage VDD is a normal level (for example, 1V, it should be noted that 1V is only an example description, and the present invention is not limited thereto), and the signal Vm is a low voltage level (for example, VSS, 0V), the signal Vmb is at a high voltage level (eg, 1V), at this time, the cross voltage of each of the capacitors C1 and C2 is approximately VDD (eg, 1V). When an undervoltage glitch occurs on the power supply voltage VDD, for example, the power supply voltage drops to (1/3)*VDD (for example, 0.3V), the voltage level of the signal Vmb is also due to the P-type transistor in the inverter 310. down to (1/3)*VDD (eg, 0.3V). At this time, the voltage across each of the capacitors C1 and C2 is approximately (1/3)*VDD (eg, 0.3V). Then, when the power supply voltage VDD returns to the original voltage level (for example, 1V), since the voltage across the capacitor cannot be changed suddenly, that is, the power supply voltage VDD changes from the reduced voltage (for example, (1/3)*VDD, such as 0.3V ) to a normal voltage (for example, VDD, such as 1V), the voltage across capacitor C1 is (1/3)*VDD (for example, 0.3V), therefore, capacitor C1 pulls signal Vm high (for example, from 0V pull up to VDD minus the voltage across the capacitor C1), so that the voltage level of the signal Vm is about (2/3)*VDD (for example, VDD-(1/3)*VDD), at this time, the voltage of the signal Vmb The level is still (1/3)*VDD. In addition, when the power supply voltage VDD returns to normal (the inverters 310 and 320 can work normally), since the voltage level of the signal Vm is higher than the voltage level of the signal Vmb, the inverters 310 and 320 form a positive feedback loop. Therefore, When the power voltage VDD returns to the original voltage level, the signal Vm is pulled high (eg, pulled up close to the power voltage VDD) and the signal Vmb is pulled low (eg, pulled down close to the ground voltage VSS). That is, after the undervoltage glitch disappears/disappears, the signal Vm is equal to a logic value “1”, and the signal Vmb is equal to a logic value “0”. However, in the absence of capacitors C1 and C2, before the glitch occurs and the power supply voltage VDD returns to normal, the voltage level of the signal Vm is a low voltage level (for example, VSS, 0V), and the voltage level of the signal Vmb is ( 1/3)*VDD (for example, 0.3V), when the power supply voltage VDD returns to normal, since the inverters 310 and 320 form a positive feedback structure, the higher potential of the signals Vm and Vmb quickly approaches the power supply voltage VDD, and the other is close to the ground voltage VSS, that is, when the power supply voltage VDD returns to normal, the signal Vmb is at a high voltage level (for example, VDD), and the signal Vm is at a low voltage level (for example, VSS), thereby The occurrence of the glitch cannot be detected by the signals Vmb and Vm. It can be seen that by deliberately setting capacitors C1 and C2, the glitches that appear at the power supply voltage VDD can be accurately detected, that is, the accuracy of glitch detection is improved, and it is also more accurate than the solution without capacitors C1 and C2. Short glitches are detected.

Referring to the embodiment shown in FIG. 3 and FIG. 4, when a significant (meaningful) under-voltage glitch occurs on the power supply voltage VDD (for example, a glitch that makes the power supply voltage VDD lower than the threshold voltage Vth), the signal Vm will always be at a high voltage Level, to trigger the warning signal generator 330 to notify the processing circuit, so that the glitch detector 300 will not miss any important undervoltage glitches, thereby improving the reliability.

In an alternative embodiment, the glitch detector 100 shown in FIG. 1A can be combined with the glitch detector 300 shown in FIG. 3 so that the glitch detector can detect shorter glitches without missing any important power supply glitches. That is, glitch detector 100 can be modified to: add capacitors C1 and C2 shown in FIG. 3; or, glitch detector 300 can be modified to: add transistors MP1, MP2, MN1 and MN2 shown in FIG. 1A . FIG. 5 is a schematic diagram of a glitch detector 500 according to an embodiment of the present invention. As shown in FIG. 5 , the glitch detector 500 includes a latch, for example, two latch-type connected logic circuits. In this embodiment, the two logic circuits are inverters 510 and 520 . Each of the inverter 510 and the inverter 520 may be implemented by a P-type transistor and an N-type transistor connected between a power supply voltage VDD and a ground voltage, and the inverter 510 is used to receive a signal Vm at a node N1 to The signal Vmb is generated at the node N2, and the inverter 520 is used to receive the signal Vmb at the node N2 to generate the signal Vm at the node N1. In addition, the glitch detector 500 also includes four discharge paths, and these discharge paths are realized by using P-type transistors MP1, MP2 and N-type transistors MN1, MN2, wherein the P-type transistor MP1 is used for power supply voltage VDD and node A current path is selectively provided between N1, a P-type transistor MP2 is used to selectively provide a current path between the power supply voltage VDD and the node N2, and an N-type transistor MN1 is used to selectively provide a current path between the node N1 and the ground voltage. A current path, and the N-type transistor MN2 is used to selectively provide a current path between the node N2 and the ground voltage. Glitch detector 500 also includes capacitors C1 and C2. The capacitor C1 is coupled between the power supply voltage VDD and the node N1, and the capacitor C2 is coupled between the node N2 and the ground voltage, wherein the capacitors C1 and C2 are intentionally provided in the glitch detector 500, that is, the capacitors C1 and C2 not parasitic capacitance. The glitch detector 500 may further include an alarm signal generator 530, wherein when the signal Vm changes from a low voltage level to a high voltage level, the alarm signal generator 530 will output an alarm signal. For similar descriptions, please refer to the embodiments shown in FIG. 1A and FIG. 3 , and for the sake of brevity, the same parts are not repeated here.

In this embodiment, some or all of the P-type transistors MP1, MP2 and N-type transistors MN1, MN2 are used to charge/discharge the charges of the nodes N1, N2 when a glitch (such as an undervoltage glitch) occurs, and, Capacitors C1 and C2 are used to pull up the signal Vm and pull down the signal Vmb when the glitch (such as an undervoltage glitch) disappears. Therefore, the glitch detector 500 is able to detect short glitches, and the accuracy of detecting glitches is improved without missing any important undervoltage glitches.

The use of ordinal terms such as "first," "second," "third," etc. in a claim to modify a claim element does not, by itself, indicate any priority of one claim element over another , priority or order, or chronological order in which method actions are performed, but are used only as markers to distinguish one claim element having the same name from another claim element having the same name using ordinal numbers.

While the present invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar constructions as will be apparent to those skilled in the art, eg combinations or substitutions of different features in different embodiments. Accordingly, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar constructions.

Claims (17)

1. A glitch detector, comprising: a first logic circuit, coupled between a supply voltage and a ground voltage, for receiving a first signal at a first node to generate a second signal to a second node; a second logic circuit, coupled between the supply voltage and the ground voltage, for receiving the second signal at the second node to generate the first signal to the first node; a first capacitor, the first pole of the first capacitor is coupled to the power supply voltage, and the second pole of the first capacitor is coupled to the first node; and, A second capacitor, the first pole of the second capacitor is coupled to the ground voltage, and the second pole of the second capacitor is coupled to the second node. 2. glitch detector as claimed in claim 1, is characterized in that, this glitch detector also comprises: A warning signal generator, coupled to the first node or the second node, is used to determine whether an undervoltage glitch occurs in the power supply voltage according to the voltage level of the first signal or the voltage level of the second signal, so as to determine whether Output warning signal. 3. The glitch detector according to claim 2, wherein when no undervoltage glitch occurs on the supply voltage, the first signal has a first logic value, and the second signal has a value different from the first logic value and, after an undervoltage glitch occurs on the power supply voltage, the warning signal generator detects whether the first signal changes to the second logic value or detects whether the second signal changes to the first logic value value to determine if an undervoltage glitch has occurred on that supply voltage. 4. glitch detector as claimed in claim 1, is characterized in that, this glitch detector also comprises: at least one first discharge path, coupled to the first node, for selectively charging/discharging the charge of the first node; and, At least one second discharge path is coupled to the second node for selectively charging/discharging the charge of the second node. 5. The glitch detector according to claim 4, wherein when an undervoltage glitch occurs on the power supply voltage, the at least one first discharge path charges/discharges the charge on the first node, and the at least one discharge path A second discharge path charges/discharges the charge of the second node. 6. The glitch detector according to claim 4, wherein the at least one first discharge path comprises a first P-type transistor and a first N-type transistor, and the first P-type transistor is used for the power supply voltage and the first N-type transistor. A current path is selectively provided between the first nodes, and the first N-type transistor is used for selectively providing a current path between the ground voltage and the first node. 7. The glitch detector according to claim 6, wherein the at least one second discharge path comprises a second P-type transistor and a second N-type transistor, and the second P-type transistor is used for the power supply voltage and the second N-type transistor. A current path is selectively provided between the second nodes, and the second N-type transistor is used for selectively providing a current path between the ground voltage and the second node. 8. The glitch detector according to claim 7, wherein each of the first P-type transistor, the first N-type transistor, the second P-type transistor and the second N-type transistor is a diode connected transistors. 9. The glitch detector as claimed in claim 1, wherein the first logic circuit and the second logic circuit comprise inverters, NAND gates or NOR gates. 10. A glitch detector, comprising: a first logic circuit, coupled between a supply voltage and a ground voltage, for receiving a first signal at a first node to generate a second signal to a second node; a second logic circuit, coupled between the supply voltage and the ground voltage, for receiving the second signal at the second node to generate the first signal to the first node; at least one first discharge path, coupled to the first node, for selectively charging/discharging the charge of the first node; and, At least one second discharge path is coupled to the second node for selectively charging/discharging the charge of the second node. 11. The glitch detector according to claim 10, further comprising: A warning signal generator, coupled to the first node or the second node, is used to determine whether an undervoltage glitch occurs in the power supply voltage according to the voltage level of the first signal or the voltage level of the second signal, so as to determine whether Output warning signal. 12. The glitch detector according to claim 11, wherein when no undervoltage glitch occurs on the supply voltage, the first signal has a first logic value, and the second signal has a logic value different from the first logic value and, after an undervoltage glitch occurs on the power supply voltage, the warning signal generator detects whether the first signal changes to the second logic value or detects whether the second signal changes to the first logic value value to determine if an undervoltage glitch has occurred on that supply voltage. 13. The glitch detector according to claim 10, wherein when an undervoltage glitch occurs on the power supply voltage, the at least one first discharge path charges/discharges the charge of the first node, and the at least one A second discharge path charges/discharges the charge of the second node. 14. The glitch detector according to claim 10, wherein the at least one first discharge path comprises a first P-type transistor and a first N-type transistor, and the first P-type transistor is used to operate between the power supply voltage and A current path is selectively provided between the first nodes, and the first N-type transistor is used for selectively providing a current path between the ground voltage and the first node. 15. The glitch detector according to claim 14, wherein the at least one second discharge path comprises a second P-type transistor and a second N-type transistor, and the second P-type transistor is used to operate between the supply voltage and A current path is selectively provided between the second nodes, and the second N-type transistor is used for selectively providing a current path between the ground voltage and the second node. 16. The glitch detector of claim 15, wherein each of the first P-type transistor, the first N-type transistor, the second P-type transistor, and the second N-type transistor is a diode connected transistors. 17. The glitch detector according to claim 10, wherein the first logic circuit and the second logic circuit comprise inverters, NAND gates, and/or, NOR gates.