CN116414212B - Core particle and control method for core particle - Google Patents

Abstract

The present disclosure relates to a core particle and a method for controlling the core particle. The core particle includes a physical layer function module and a first physical layer interface module. The physical layer function module includes a sending state machine sub-module, a data message sending sub-module and a control message sending sub-module. The data message sending sub-module is configured to provide the first data message, the control message sending sub-module is configured to provide the first state entry message, and the sending state machine sub-module is configured to control the physical layer function module to the first physical layer interface module Providing the first data message is switched to providing the first state entry message to the first physical layer interface module, so that the first physical layer interface module switches from providing the first data message to another core through the physical link to providing the first data message through the physical link. The link provides a first state entry message to another core particle, and controls the first physical layer interface module to enter a low power consumption state from a working state. The chip does not require the use of additional pins to control the first physical layer interface module into a low-power state.

Description

Core particles and core particle control methods

Technical field

Embodiments of the present disclosure relate to a core particle and a method for controlling the core particle.

Background technique

Chiplet is also called "core particle" or "small chip". Chip technology is to split a feature-rich and large-area chip die into multiple chips. These pre-produced core chips that can achieve specific functions are combined and integrated and packaged through advanced packaging (such as 3D packaging) to form a system chip.

High-speed interconnection between core particles is a key technology for the implementation of core particle technology. When designing the interconnection interface between chips, chip design companies need to consider improving data throughput, reducing latency and bit rate, and at the same time, they need to reduce the overall power consumption of the chip interconnection.

Contents of the invention

At least one embodiment of the present disclosure provides a core chip, including a physical layer functional module and a first physical layer interface module. The first physical layer interface module is used to electrically communicate with a second physical layer interface module of another core chip through a physical link. connection, the physical layer function module includes a sending state machine sub-module, a data message sending sub-module and a control message sending sub-module, the data message sending sub-module is configured to provide the first physical layer interface module with the first data message, the control message sending sub-module is configured to provide a first state entry message to the first physical layer interface module, and the sending state machine sub-module is configured to: receive the first control signal; respond to the The first control signal switches from the second mode to the first mode, controlling the physical layer function module to switch from providing the first data message to the first physical layer interface module to providing the first data packet to the first physical layer interface module. Providing a first state entry message causes the first physical layer interface module to switch from providing the first data message to the other core through the physical link to providing the first data message to the other core through the physical link. Another core particle provides the first state entry message; and after the first physical layer interface module provides the first state entry message to the other core particle, control the first physical layer interface The module enters the low power consumption state from the working state. The first state entry message is used to notify the other core to enter the low power consumption state. The first physical layer interface module is in the low power consumption state. The power consumption is less than the power consumption in the working state.

For example, in the core chip provided by an embodiment of the present disclosure, the first physical layer interface module includes a sending sub-module, the sending sub-module is electrically connected to the sending state machine sub-module, and the sending state machine sub-module is configured as In response to the first mode of the first control signal, the sending sub-module is controlled to enter the low power consumption state from the working state.

For example, in the core provided by an embodiment of the present disclosure, the control message sending sub-module is further configured to provide a wake-up message and an exit message to the sending sub-module, and the sending state machine sub-module is further configured to: respond to The first control signal switches from the first mode to the second mode, controls the sending sub-module to exit the low power consumption state and enters the working state; controls the control message sending sub-module to The sending sub-module provides the wake-up message, so that the sending sub-module provides the wake-up message to the other core particle to notify the second physical layer interface module to enter the working state; control the control The message sending sub-module provides the status exit message to the sending sub-module, so that the sending sub-module provides the status exit message to another core particle to notify the other core particle to resume the next clock cycle. Describes the reception of the first data message.

For example, in the core chip provided by an embodiment of the present disclosure, the sending state machine sub-module is further configured to: provide a third control signal to the sending sub-module, so that the sending sub-module enters the low state from the working state. In the power consumption state, in response to the third control signal being in the first control mode, the sending sub-module is in the working state, in response to the third control signal being in the second control mode, the sending sub-module is in the Describe the low power state.

For example, in the core chip provided by an embodiment of the present disclosure, the second control mode causes at least part of the circuit structure in the sending sub-module to be turned off, so that the sending sub-module is in the low power consumption state, and the The first control mode enables the at least part of the circuit structure to be turned on, so that the sending sub-module is in the working state.

For example, in the core chip provided by an embodiment of the present disclosure, the sending sub-module includes multiple data sending channels for transmitting the data message, a phase-locked loop, a clock phase control unit and a clock switch unit. Each of the multiple data transmission channels includes a data drive buffer and a parallel-to-serial conversion unit, the parallel-to-serial conversion unit is connected to the data drive buffer, and the parallel-to-serial conversion unit is configured to convert parallel data into serial data, The serial data is provided to the data drive buffers, each data drive buffer being connected to the physical link. The phase-locked loop is connected to the clock phase control unit, the clock switch unit is connected to the clock phase control unit, and is connected to the parallel-to-serial conversion unit, and the phase-locked loop is configured to generate a clock signal, so The clock phase control unit is configured to control the phase of the clock signal, and after the phase control of the clock signal, provides the clock signal to the clock switch unit, the clock switch unit is configured to provide the clock signal to the parallel The serial conversion unit provides the clock signal, and the at least part of the circuit structure includes: a data driving buffer in at least one data transmission channel among the plurality of data transmission channels and the clock switch unit.

For example, in the core provided by an embodiment of the present disclosure, the data driving buffer in the target transmission channel among the multiple data transmission channels of the transmission sub-module is in the open state in the low power consumption state, so The sending state machine sub-module is configured to provide the wake-up message to the other core through a data-driven buffer in the target sending channel; or the sending sub-module further includes a sideband signal path, and the sending state The machine sub-module is configured to provide the wake-up message to the other core chip through the sideband signal path.

For example, in the core particle provided by an embodiment of the present disclosure, the physical layer functional module further includes a selector, the selector includes a first input terminal, a second input terminal, a third input terminal and an output terminal, and the datagram The message sending sub-module is connected to the first input terminal, the control message sending sub-module is connected to the second input terminal, the output terminal is connected to the physical layer interface module, and the sending state machine sub-module further The selector is configured to provide a second control signal to the third input terminal, and the selector is configured to select the output terminal to provide the data message transmission to the first physical layer interface module according to the second control signal. The data message or the control message provided by the sub-module sends the control message provided by the sub-module.

For example, in the core particle provided by an embodiment of the present disclosure, the sending state machine submodule is also configured as:

In response to the first mode of the first control signal, a message stop receiving signal is provided to the data message sending sub-module; the data message sending sub-module is configured to: in response to the message stopping receiving signal, Stop receiving the first data message.

For example, the core provided by an embodiment of the present disclosure further includes: a data bus module configured to provide the first data message and the first control signal to the physical layer functional module.

For example, in the core chip provided by an embodiment of the present disclosure, the data bus module is further configured to: count the number of invalid data; and in response to the number of invalid data being greater than the first preset threshold, trigger the The first control signal switches to the first mode.

For example, in the core provided by an embodiment of the present disclosure, the data bus module includes a data buffer for storing the first data message provided to the physical layer function module, and the data bus module is further configured to : Counting the number of valid data in the data buffer; and in response to the number of valid data reaching the second preset threshold, triggering the first control signal to switch to the second mode to provide the required The physical layer interface module provides the first data message.

For example, in the core provided by an embodiment of the present disclosure, the physical layer function module also includes a receiving state machine sub-module, a data message receiving sub-module and a control message receiving sub-module, and the first physical layer interface module is also configured as : Receive the communication message provided from the other core particle, and provide the communication message to the data message receiving sub-module and the control message receiving sub-module, the data message receiving sub-module Configured to: receive the communication message, the control message receiving sub-module is configured to: receive the communication message, and in response to the communication message being a second state entry message, to the receiving state machine sub-module The module provides the second state entry message, and the receiving state machine module is configured to: in response to the second state entry message, control the data message receiving sub-module to stop receiving the second data message, and control The first physical layer interface module switches from a working state to a low power consumption state.

For example, in the core particle provided by an embodiment of the present disclosure, it further includes: in response to the communication message being the second data message, the data message receiving sub-module provides the data bus module with the The second data message.

For example, in the core provided by an embodiment of the present disclosure, the first physical layer interface module includes a receiving sub-module, the receiving sub-module is connected to the receiving state machine sub-module, and the receiving state machine sub-module is configured as: Control the receiving sub-module to switch from the working state to the low power consumption state.

For example, in the core chip provided by an embodiment of the present disclosure, the receiving state machine sub-module is further configured to: provide a fourth control signal to the receiving sub-module, so that the receiving sub-module enters the low state from the working state. In the power consumption state, in response to the fourth control signal being in the first control mode, the receiving sub-module is in the working state, in response to the fourth control signal being in the second control mode, the receiving sub-module is in the Describe the low power state.

For example, in the core provided by an embodiment of the present disclosure, the second control mode causes at least part of the circuit structure in the receiving sub-module to be turned off, so that the receiving sub-module is in the low power consumption state, and the first The control mode enables at least part of the circuit structure to be turned on, so that the receiving sub-module is in the working state.

For example, in the core chip provided by an embodiment of the present disclosure, the receiving sub-module includes multiple data receiving channels for transmitting the data message, a clock phase control unit and a clock switch unit. Each of the multiple data receiving channels is The strip includes a data receiving buffer and a serial-to-parallel conversion unit, each data receiving buffer is connected to the physical link, the serial-to-parallel conversion unit is connected to the data receiving buffer, and the serial-to-parallel conversion unit is configured to receive The data receives serial data provided by the buffer and converts the serial data into parallel data. The clock switch unit is connected to the clock phase control unit and to the serial-to-parallel conversion unit. The clock phase The control unit is configured to receive a clock signal, control the phase of the clock signal, and after controlling the phase of the clock signal, provide the clock signal to the clock switch unit, the clock switch unit is configured to provide the clock signal to the clock switch unit. The serial-to-parallel conversion unit provides the clock signal, and the at least part of the circuit structure includes: a data receiving buffer in at least one data receiving channel among the plurality of data receiving channels and the clock switch unit.

For example, in the core provided by an embodiment of the present disclosure, the control message receiving sub-module is further configured to: in response to the communication message being the wake-up message, send the wake-up message to the receiving state machine sub-module. Text, the receiving state machine sub-module is configured to: in response to receiving the wake-up message, switch the fourth control signal to the first control mode to control the receiving sub-module to enter the working state; The control message receiving sub-module is further configured to: in response to the communication message being the status exit message, provide the exit message to the receiving state machine sub-module, and the receiving state machine sub-module is further configured to : In response to the status exit message, control the data message receiving sub-module to start receiving the second data message.

At least one embodiment of the present disclosure provides a control method for a core particle. The core particle includes a physical layer functional module and a first physical layer interface module. The first physical layer interface module is used to communicate with a second physical layer of another core particle. The layer interface module is electrically connected through a physical link, and the method includes: in response to a first pattern of the first control signal, controlling the physical layer function module by providing the first physical layer interface module with the first The data message switching is to provide the first state entry message to the first physical layer interface module, so that the first physical layer interface module provides the first state entry message to the other core through the physical link. The data message switching is to provide the first state entry message to the other core particle through the physical link, and provide the first state entry message to the other core particle in the first physical layer interface module. After the state entry message, the first physical layer interface module is controlled to enter the low power consumption state from the working state. The first state entry message is used to notify the other core chip to enter the low power consumption state, so The power consumption of the first physical layer interface module in the low power consumption state is less than the power consumption in the working state.

Description of the drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure. .

Figure 1A shows a schematic diagram of the circuit structure of a gated clock;

Figure 1B shows a timing diagram of a gated clock;

Figure 1C shows a flow chart for entering and exiting the L1 state;

Figure 2 shows an architectural diagram of a chip that quickly enters a low power consumption state provided by at least one embodiment of the present disclosure;

Figure 3 shows a schematic diagram of part of the internal circuit structure of the physical layer interface module provided by at least one embodiment of the present disclosure;

Figure 4A shows a schematic circuit diagram of a data bus module generating a txFastPM_Entry signal provided by at least one embodiment of the present disclosure;

Figure 4B shows a schematic circuit diagram of a data bus module generating a txFastPM_Exit signal provided by at least one embodiment of the present disclosure;

Figure 4C shows a schematic diagram of independent control of the core particle in the two transmission directions of receiving and sending provided by at least one embodiment of the present disclosure;

Figure 5 shows a block diagram of a physical layer coding module PCS or adaptation layer provided by at least one embodiment of the present disclosure;

Figure 6A shows a schematic diagram of a state machine of a sending submodule provided by at least one embodiment of the present disclosure;

Figure 6B shows a schematic diagram of a state machine of a receiving submodule provided by at least one embodiment of the present disclosure.

Figure 7A shows a flow chart of a method for a transmitter and a receiver to quickly enter a low power consumption state provided by at least one embodiment of the present disclosure;

Figure 7B shows a timing diagram for a sending end to quickly enter a low power consumption state provided by at least one embodiment of the present disclosure;

Figure 7C shows a timing diagram for a receiving end to quickly enter a low power consumption state provided by at least one embodiment of the present disclosure;

Figure 8A shows a flow chart of a method for a sending end and a receiving end to quickly exit a low power consumption state provided by at least one embodiment of the present disclosure;

Figure 8B shows a timing diagram for a sending end to quickly exit a low power consumption state provided by at least one embodiment of the present disclosure;

Figure 8C shows a timing diagram for a receiving end to quickly exit a low power consumption state provided by at least one embodiment of the present disclosure;

Figure 9A shows a flow chart of a state jump of a sending state machine provided by at least one embodiment of the present disclosure; and

FIG. 9B shows a flow chart of state transition of a receiving state machine provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the usual meaning understood by a person with ordinary skill in the art to which this disclosure belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, similar words such as "a", "an" or "the" do not indicate a quantitative limitation but rather indicate the presence of at least one. Words such as "include" or "comprising" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

The UCIe standard defines interconnection technical specifications between dies or chiplets within a package to create an open die ecosystem. The physical layer of the Ucle standard specifies two different physical layer interface modules (Physical layer, PHY), which use 64 lanes (lane) for advanced packaging and 16 lanes (lane) for ordinary packaging. Ucle's PHY has a large number of parallel channels and consumes more power if it is always in working mode. When the system needs to transmit less data, the PHY can be put into low-power mode to reduce system power consumption.

Three power management methods are defined in UCIe, namely gated clock management, L1 power management and L2 power management.

FIG. 1A shows a schematic diagram of the circuit structure of a gated clock. Figure 1B shows a timing diagram of a gated clock. The following describes gated clock management with reference to Figures 1A and 1B.

As shown in Figure 1A, the left side is the sending end and the right side is the receiving end.

The gated clock scheme uses a valid (Valid) signal to indicate whether the data is valid or invalid.

When the sender has no valid data to send, the valid signal is set to 0. The sender can turn off the clock of the sender according to the valid signal, and the clock sent to the receiver is also turned off, thereby saving the power consumption of the sender.

When the receiving end receives a valid signal, it uses the valid signal to turn the receiving clock on or off. When the valid signal is 0, the clock of the receiving end is turned off, thereby saving the power consumption of the receiving end.

The data at the transmitter comes from the Physical Coding Sublayer (PCS) module. The data provided by the PCS to the PHY will first pass through a cache 101, and then pass through a parallel-to-serial converter 102. The parallel-to-serial converter 102 converts the parallel data into The serial data is then sent to the physical link through a data driver buffer (buffer) 103.

The clock at the sending end is generated by a phase locked loop (Phase Locked Loop, PLL) 104, and the clock output by the PLL 104 is controlled by a valid signal to a clock switch control circuit (Clock gater) 105. The clock switch control circuit 105 outputs a clock when the valid signal is 1. When the valid signal is 0, the output of the clock switch control circuit 105 is 0. The clock passing through the clock switch control circuit 105 will pass through the clock phase controller 106 to control the phase of the sending clock. The clock output by the phase control is used by the cache 101 and the parallel-to-serial converter 102 . At the same time, the clock output by the clock phase controller 106 will be sent to the physical link through the clock driving buffer 107.

The valid signal at the sending end comes from the PCS. The valid signal is 1, which means the data sent to the PHY is valid. A valid signal of =0 indicates that the data sent to the PHY is invalid. At this time, the PHY can turn off the clock of the sending end.

At the receiving end, it is judged whether valid data is received based on the valid signal received. When the valid signal is 1, the output clock of the clock switch control circuit 116 is turned on, and the clock switch control circuit 116 supplies the output clock to the register (Digital Flip-Flop, DFF) in the receiving end digital circuit. So that the data can be received normally. When the valid signal is 0, the output of the clock switch control circuit 116 is 0, and no valid data is received.

As shown in Figure 1B, data is sent and received on both the rising and falling edges of the clock. For a byte of data, the valid signal is defined as a high level lasting for 2 clock cycles and a low level lasting for 2 clock cycles, indicating that valid data is sent. When the valid signal remains low for 8 clock cycles, it means that no valid data is sent and the clock can be turned off.

When the valid signal is pulled high, it means that the data and clock have recovered, and data needs to be received normally.

Gated clock management: When there is no valid data transmission during the transmission process, the gated clock can quickly shut down the PHY clock to save power consumption. Gating clock management achieves the effect of saving power consumption by turning off the PHY clock. The entry and exit time is about 0.5 nanoseconds, but the power saving effect is the worst and requires additional valid pins (Valid PAD).

Gated clock management requires an additional pin (PAD) to tell the other party whether the data is valid. The PAD of high-performance chips is often limited, and increasing PAD may lead to an increase in the area of the chip. At the same time, adding additional PAD itself will also increase power consumption. Gating clock management can reduce power consumption by turning off the clock of some logic. But the power consumption reduction of just turning off the clock is limited. The gated clock needs to keep the data channel, clock channel and Valid channel always open. The analog circuitry in the PHY is always on and the power consumption is still very high.

L1 power management allows the link to enter the L1 state when there is no valid data transmission in both the receiving and sending directions for a long time. L1 power management is used when the link has no valid data transmission in both the receiving and sending directions for a long time. In the case of valid data transmission, the L2 state can be entered. The L1 state and the L2 state are two low-power states of UCIe. Both states are controlled by the physical coding sublayer (PCS) or the adaptation layer (Adapter Layer) defined in UCIe to control the PHY to enter the low-power state. The difference is that the PHY sleeps shallowly in the L1 state, and the PHY will enter the retraining state after exiting the L1 state. In the L2 state, the PHY sleeps deeply. After exiting L2, the PHY will enter the reset state.

The entry and exit processes of L1 power management and L2 power management are similar. In this disclosure, entering and exiting the L1 state are taken as an example to illustrate the L1 power management. Since L2 power consumption management is similar to L1 power consumption management, details will not be described in this disclosure.

Figure 1C shows a flow chart for entering and exiting the L1 state.

As shown in Figure 1C, the method of entering the state includes steps S201 to S206.

Step S201: The adaptation layer of the sending end DIE0 sends Lp_state_req=L1 to the physical layer. Lp_state_req is the adaptation layer that initiates a state change request to the physical layer, and L1 indicates that the physical layer is controlled to enter the L1 state.

Step S202: The physical layer of the sending end DIE0 sends the request message L1.Req to enter the L1 state to the receiving end DIE1 through the sideband signal (SB_MSG).

Step S203: The adaptation layer of the receiving end DIE1 responds to the request message L1.Req of the sending end DIE0 and controls the physical layer Lp_state_req=L1 of the receiving end DIE1.

Step S204: The physical layer of the receiving end DIE1 returns the feedback signal L1.Rsp to the sending end DIE0. At the same time, the physical layer of the receiving end DIE1 also sends the request message L1.Req to the sending end DIE0.

Step S205: After receiving the feedback signal L1.Rsp from the receiving end DIE1, the physical layer of the sending end DIE0 sets Pl_state_sts=PM to enter the PM state, and simultaneously sends the feedback signal L1.Rsp to the receiving end DIE1. The PM state refers to the L1 state or the L2 state. If Pl_state_req=L1, the PM state refers to the L1 state; if Pl_state_req=L2, the PM state refers to the L2 state. For example, the physical layer of the sending end DIE0 sends the state indication signal Pl_state_sts=PM to the adaptation layer, so that the sending end DIE0 enters the PM state.

Step S206: The physical layer of the receiving end DIE1 enters the PM state after receiving the feedback signal L1.Rsp of the transmitting end DIE0.

As shown in Figure 1C, the method of exiting the low power consumption state includes steps S301 to S306.

Step S301: The adaptation layer of the sending end DIE0 controls the physical layer Lp_state_req=Active. Active means controlling the physical layer to enter the working state to control the physical layer to exit the L1 state.

Step S302: The physical layer of the sending end DIE0 sends the request message Active.Req to enter the working state to the receiving end DIE1 through the sideband signal.

Step S303: After receiving the Active.Req, the physical layer of the receiving end DIE1 sends an Active.Rsp message to the sending end DIE0, and notifies the adaptation layer to re-do the link training. For example, the physical layer of the sending end DIE0 sends the status indication signal Pl_state_sts=Retrain to the adaptation layer, so that the adaptation layer re-does link training.

Step S304: The adaptation layer of the receiving end DIE1 controls the physical layer Lp_state_req=Active and controls exiting the L1 state. The physical layer of the receiving end DIE1 sends an Active.Req message to the sending end DIE0.

Step S305: The physical layer of the sending end DIE0 returns Active.Rsp after receiving Active.Req. Wait for the training to be completed before entering the working state.

Step S306: After receiving Active.Rsp, the physical layer of the receiving end DIE1 waits for training reception and then enters the working state.

L1 power management can turn off the PHY phase-locked loop to save more power consumption. The PHY needs to be retrained when the L1 state exits, so the exit time is longer at the microsecond or millisecond level. L2 power management can shut down the entire PHY, which is the most power-saving state. However, when exiting the L2 state, it needs to re-enter the reset state, and it takes the longest time to return to the working state.

Whether it is L1 power management or L2 power management, the entire link must be disconnected. When reconnecting, the PHY needs to be retrained, and the exit time is very long. Once entering the L1 state or L2 state, the PHY's transmission and reception will completely stop. The analog circuit of the PLL, PLL, etc. will be turned off. If data transmission is to be resumed, the PHY will need to be retrained. Moreover, L1 power management and L2 power management use sideband signals to transmit additional control signals, requiring additional PADs and consuming additional power. The Sideband signal requires two signals, SB_Clock and SB_Message, as well as additional sending and receiving circuits, which require additional power consumption.

The present disclosure proposes a chip that can quickly enter and exit a low-power consumption mode without using additional pins (for example, the entry and exit time is only a few clock cycles). Some embodiments of the present disclosure can also turn off the output clock of the PHY and the analog transceiver circuit, effectively reducing the power consumption of the digital transceiver logic and the power consumption of the PHY.

At least one embodiment of the present disclosure provides a core particle. The core particle includes a physical layer functional module and a first physical layer interface module. The first physical layer interface module is used to electrically connect with the second physical layer interface module of another core particle through a physical link. The physical layer functional module includes a transmitter State machine sub-module, data message sending sub-module and control message sending sub-module, the data message sending sub-module is configured to provide the first data message to the first physical layer interface module, and the control message sending sub-module is configured to provide the first data message to the first physical layer interface module. A physical layer interface module provides a first state entry message, and the sending state machine submodule is configured to: receive a first control signal; in response to the first mode of the first control signal, control the physical layer function module to pass to the first physical layer interface module Providing the first data message is switched to providing the first state entry message to the first physical layer interface module, so that the first physical layer interface module switches from providing the first data message to another core through the physical link to providing the first data message through the physical link. The link provides the first state entry message to another core particle, and after the first physical layer interface module provides the first state entry message to the other core particle, controls the first physical layer interface module to enter the low power state from the working state. consumption state, the first state entry message is used to notify another chip to enter the low power consumption state, and the power consumption of the first physical layer interface module in the low power consumption state is less than the power consumption in the working state. The core particle controls the physical link to transmit status entry messages by sending the state machine sub-module, so that the physical link can transmit not only data messages but also status entry messages, so that the core particle can be made without adding additional pins. Quickly enter and exit low-power mode.

Figure 2 shows an architectural diagram of a chip that quickly enters a low power consumption state provided by at least one embodiment of the present disclosure. An example of a core particle provided by at least one embodiment of the present disclosure will be described below with reference to FIG. 2 .

As shown in Figure 2, the core particle DIE0 is included in the architecture. The core particle DIE0 includes the physical layer function module PCA0 and the physical layer interface module PHY0. The physical layer interface module PHY0 is used to electrically connect with the physical layer interface module PHY1 of another chip DIE1 through a physical link. The physical layer interface module PHY0 is an example of the first physical layer interface module, and the physical layer interface module PHY1 is an example of the second physical layer interface module.

For example, the physical layer function module PCA0 may be a physical layer coding submodule or an adaptation layer. The adaptation layer is used to select and arbitrate between multiple protocols. The physical layer coding submodule is used to control the physical layer interface module to send and receive data. The physical layer interface module is responsible for signal transmission technology related to electrical characteristics. The physical link may be a wired link or a wireless link (for example, optical fiber, etc.). The embodiments of the present disclosure do not specifically limit the form of the physical link.

The physical layer function module PCA0 includes a sending state machine sub-module 210, a data message sending sub-module 220 and a control message sending sub-module 230.

The data message sending sub-module 220 is configured to provide the data message txData to the physical layer interface module PHY0. The data message txData is an example of the first data message. The control message sending sub-module 230 is configured to provide the first state entry message to the physical layer interface module PHY0. The first state entry message is used to notify another chip DIE1 to enter a low power consumption state. The first state entry message is, for example, the FPMEntry message in Figure 2.

The sending state machine sub-module 210 is configured to: receive the control signal txLowPower (the control signal txLowPower is an example of the first control signal); in response to the control signal txLowPower switching from the second mode to the first mode, control the physical layer function module PCA0 from to the physical layer The interface module PHY0 provides the first data message and switches to providing the first state entry message (for example, FPMEntry message) to the physical layer interface module PHY0, so that the physical layer interface module PHY0 provides it to another core chip DIE1 through the physical link. The data message txData is switched to provide the first state entry message to the other core DIE1 through the physical link, and after the physical layer interface module PHY0 provides the first state entry message to the other core DIE1, the physical layer interface is controlled. The module PHY0 enters the low power consumption state from the working state, and the power consumption of the physical layer interface module PHY0 in the low power consumption state is less than the power consumption in the working state.

For example, the control signal txLowPower may include one or more level signals. For example, the control signal txLowPower includes a level signal. If the level signal is a first level (for example, high level), the control signal txLowPower is a first mode. If the level signal is a second level (for example, high level) For example, low level), the control signal txLowPower is in the second mode. For another example, the control signal txLowPower includes multiple level signals, and different combinations of the multiple level signals represent different modes. For example, if two level signals are both high level, it means that the control signal txLowPower is in the first mode. If both level signals are low level, it means that the control signal txLowPower is in the second mode. One of the two level signals is high. Level one is low level, indicating that the control signal txLowPower is in the third mode. This disclosure does not limit the first control signal and the mode of the first control signal.

In the following, the control signal txLowPower is at a high level as the first mode, and the control signal txLowPower is at a low level as the second mode.

For example, in response to the control signal txLowPower switching from low level to high level, the sending state machine sub-module 210 controls the physical layer function module PCA0 to switch from providing the first data message to the physical layer interface module PHY0 to providing the first data message to the physical layer interface module PHY0. The first state enters the message. That is, if the control signal txLowPower is low level, the sending state machine sub-module 210 controls the physical layer function module PCA0 to provide the first data message to the physical layer interface module PHY0; if the control signal txLowPower is high level, the sending state machine sub-module 210 210 controls the physical layer function module PCA0 to provide the first state entry message to the physical layer interface module PHY0.

The physical interface module PHY0 provides the message received from the physical layer function module PCA0 to another core chip DIE1 through a physical link. For example, the physical layer function module PCA0 provides the data message txData to the physical interface module PHY0, then the physical interface module PHY0 provides the data message txData to another core chip DIE1 through the physical link; if the physical layer function module PCA0 provides the data message txData to the physical interface module PHY0 provides the first state entry message, and the physical interface module PHY0 provides the first state entry message to another chip DIE1 through the physical link.

The physical layer function module PCA0 switches from providing the data message txData to the physical layer interface module PHY0 to providing the first state entry message to the physical layer interface module PHY0, so that the physical layer interface module PHY0 switches from providing the data message txData to the other core chip DIE1 through the physical link. Providing the data message txData is switched to providing the first state entry message to the other core particle DIE1 through the physical link.

After the physical layer interface module PHY0 provides the first state entry message to the other die DIE1, the physical layer interface module PHY0 is controlled to enter the low power consumption state from the working state. The power consumption of the physical layer interface module PHY0 in the low power consumption state is less than the power consumption in the working state.

For example, the physical layer interface module PHY0 includes a sending sub-module TX0. The sending sub-module TX0 is used for sending data messages. The transmitting sub-module TX0 is electrically connected to the transmitting state machine sub-module 210. The transmitting state machine sub-module 210 is configured to respond to the first mode of the first control signal and control the transmitting sub-module TX0 to enter the low power consumption state from the working state. That is, the physical layer interface module PHY0 entering the low power consumption state includes the sending sub-module TX0 entering the low power consumption state.

In the embodiment of the present disclosure, the core particle responds to the control signal by sending the state machine sub-module, and controls the physical layer function module to use the physical link to transmit the data message and the physical link to transmit the first state entry message, so that the core particle The chip can quickly enter and exit low-power consumption mode without adding additional pins.

As shown in Figure 2, in some embodiments of the present disclosure, the physical layer function module PCA0 may also include a selector. The selector includes a first input terminal (for example, input terminal D0), a second input terminal (for example, input terminal D0 D1), a third input terminal (for example, input terminal S) and an output terminal (for example, input terminal P).

The data message sending sub-module 220 is connected to the input terminal D0, the control message sending sub-module 230 is connected to the input terminal D1, and the output terminal P is connected to the physical layer interface module PHY0.

The sending state machine sub-module 210 is further configured to provide a second control signal to the input terminal S. The second control signal is, for example, the control signal txFastPM_Sel shown in FIG. 2 .

The selector 240 is configured to select the output terminal P to provide the message provided by the data message sending sub-module 220 or the control message provided by the control message sending sub-module 230 to the physical layer interface module PHY0 according to the control signal txFastPM_Sel.

The control messages provided by the control message sending sub-module 230 may not only include the first state entry message described above, but may also include state exit messages, wake-up messages, etc. For exit messages or wake-up messages, please refer to the description below.

For example, if the control signal txLowPower is low level, the control signal txFastPM_Sel output by the sending state machine sub-module 210 is low level, the input terminal S of the selector 240 receives the low level signal, and the signal output of the input terminal D0 is selected, that is, The data message txData is provided to the physical layer interface module PHY0 via the output terminal P; if the control signal txLowPower is high level, the control signal txFastPM_Sel output by the sending state machine sub-module 210 is high level, and the input terminal S of the selector 240 receives The high-level signal selects the signal output of the input terminal D1, that is, provides the first state entry message to the physical layer interface module PHY0 via the output terminal P.

The physical layer function module PCA0 is controlled by the selector to provide data messages or control messages to the physical layer interface module PHY0, making the logic of the physical layer function module PCA0 simple and easy to implement. However, this disclosure does not limit the method of controlling the physical layer function module PCA0 to provide data messages or control messages to the physical layer interface module PHY0. Those skilled in the art can use other methods to control the physical layer function module PCA0 to provide the physical layer interface module PHY0 with data messages or control messages. The layer interface module PHY0 provides data packets or control packets

In some embodiments of the present disclosure, the control message sending sub-module 230 is also configured to provide a wake-up message and a status exit message to the sending sub-module TX0.

The sending state machine sub-module 210 is also configured to switch from the first mode to the second mode in response to the first control signal (for example, the control signal txLowPower), and control the sending sub-module TX0 to exit the low power consumption state and enter the working state; control the control message The sending sub-module 230 provides a wake-up message to the sending sub-module TX0, so that the sending sub-module provides a wake-up message to another core chip DIE1 to notify the physical layer interface module PHY1 to enter the working state; the control control message sending sub-module 230 controls the sending sub-module 230 to send a wake-up message to the sending sub-module TX0. The sub-module TX0 provides a status exit message, so that the sending sub-module TX0 provides a status exit message to another core chip DIE1 to notify the other core chip DIE1 to resume receiving the first data message in the next clock cycle.

For example, as shown in Figure 2, the wake-up message is the FPMWake message and the exit message is the FPMExit message. For example, both the FPMWake message and the FPMExit message are provided by the sending state machine sub-module 210 to the control message sending sub-module 230, so that the control message sending sub-module 230 provides the wake-up message and the status exit message to the sending sub-module TX0.

Providing wake-up messages and status exit messages to another core through a physical link allows the other core to be controlled to resume working status without adding pins.

In some embodiments of the present disclosure, the sending state machine sub-module 210 is further configured to provide a message stop receiving signal Tx_stop to the data message sending sub-module 220 in response to the first mode of the first control signal; the data message sending sub-module 220 is configured to stop receiving the first data message in response to the message stop receiving signal Tx_stop.

In some embodiments of the present disclosure, the transmitting state machine sub-module 210 is further configured to provide a third control signal to the transmitting sub-module TX0, so that the transmitting sub-module TX0 enters the low power consumption state from the working state. In response to the third control signal being in the first control mode, the sending sub-module TX0 is in the working state. In response to the third control signal being in the second control mode, the sending sub-module TX0 is in the low power consumption state.

As shown in FIG. 2 , the third control signal is, for example, the control signal TX_LP. For example, when the control signal TX_LP is low level, it is the first control mode, and when the control signal TX_LP is high level, it is the second control mode. Similar to the first control signal, the present disclosure does not limit the first control mode and the second control mode of the third control signal.

For example, after the physical layer interface module PHY0 provides the FPMEntry message to another core die DIE1, the sending state machine sub-module 210 provides the high-level control signal TX_LP to the physical layer interface module PHY0, so that the sending sub-module of the physical layer interface module PHY0 TX0 enters a low power state.

In some embodiments of the present disclosure, the second control mode of the control signal TX_LP causes at least part of the circuit structure in the sending sub-module TX to be turned off, so that the sending sub-module TX0 is in a low power consumption state, and the first control mode causes at least part of the circuit structure to Turn on, so that the sending sub-module TX0 is in working state.

For example, at least part of the circuit structure includes a clock circuit, a data path, a phase-locked loop, and the like. Those skilled in the art can set up a circuit structure that is turned off in a low power consumption state by themselves, and this disclosure does not limit it.

In some embodiments of the present disclosure, the physical layer interface module of the core particle may include a sending sub-module and a receiving sub-module, and the receiving sub-module is used for receiving data messages. For example, the physical layer interface module PHY0 includes a transmitting sub-module TX0 and a receiving sub-module RX0; the physical layer interface module PHY1 includes a transmitting sub-module TX1 and a receiving sub-module RX1.

FIG. 3 shows a schematic diagram of part of the internal circuit structure of the physical layer interface module provided by at least one embodiment of the present disclosure.

For example, part of the internal circuit structure of the transmitting sub-module TX0 of the physical layer interface module PHY0 is shown on the left side of Figure 3; part of the internal circuit structure of the receiving sub-module RX1 of the physical layer interface module PHY1 is shown on the right side of Figure 3. The figure only shows the connection relationship between the transmitting sub-module TX0 of the physical layer interface module PHY0 and the receiving sub-module RX1 of the physical layer interface module PHY1. The receiving sub-module RX0 of the physical layer interface module PHY0 has a similar structure to the receiving sub-module RX1 of the physical layer interface module PHY1, and will not be described again. The transmitting sub-module TX1 of the physical layer interface module PHY1 is similar to the transmitting sub-module TX0 of the physical layer interface module PHY1, and will not be described again.

In some embodiments of the present disclosure, each physical layer interface module has multiple data lanes (Lane). Multiple data channels include multiple data sending channels and multiple data receiving channels. The sending sub-module in the physical layer interface module includes multiple data sending channels, and the receiving sub-module includes multiple data receiving channels, thereby independently sending and receiving data through multiple data sending channels and multiple data receiving channels. In addition to multiple data transmission channels, the sending sub-module also contains a clock channel for providing the sending clock of the sending end to the receiving end (for example, receiving sub-module RX1).

For example, the sending sub-module TX0 includes multiple data sending channels for transmitting data messages. Each data transmission channel includes a data driver buffer and a parallel-to-serial conversion unit. The parallel-to-serial conversion unit is connected to the data driver buffer, and the parallel-to-serial conversion unit is configured to convert parallel data into serial data to provide serial data to the data driver buffer, and each driver buffer is connected to a physical link. For example, data channel 0 includes at least cache 0, parallel-to-serial conversion unit 0 and data drive buffer DD0. Other data channels are similar to data channel 0, including at least cache, parallel-to-serial conversion unit and data driver buffer.

As shown in Figure 3, the transmission data of each data channel (for example, transmission data 0, transmission data 1, ..., transmission data n) is buffered and then undergoes a parallel-to-serial conversion to convert the parallel data into serial data. Serial data is sent to the physical channel (i.e., physical link) through a data-driven buffer. After receiving the signal from the physical channel, the receiving end RX1 passes through a data reception buffer and provides it to the serial-to-parallel conversion unit, which converts the serial data into parallel data and then sends it to the buffer.

As shown in Figure 3, the transmitting sub-module TX also includes a phase-locked loop PLL, a clock phase control unit 310 and a clock switch unit 320.

The phase-locked loop PLL is connected to the clock phase control unit 310, and the clock switch unit 320 is connected to the clock phase control unit 310 and to each of the plurality of parallel-to-serial conversion units. The phase locked loop PLL is configured to generate a clock signal, the clock phase control unit 310 is configured to control the phase of the clock signal, and after the phase control of the clock signal, provides the clock signal to the clock switch unit 320, the clock switch unit 320 is configured to The serial conversion unit provides the clock signal.

At least part of the circuit structure includes at least one data driving buffer and clock switch unit 320 in a plurality of data paths.

In some embodiments of the present disclosure, as shown in Figure 3, for example, the sending sub-module TX0 receives the control signal TX_LP provided by the physical layer functional module (for example, PCA0 in Figure 2), and the physical layer functional module controls the sending sub-module TX0 Quickly enter a low power state. Since the physical layer interface module PHY0 enters the low power consumption state and no valid data is sent, the control signal TX_LP controls the clock switch module to turn off the clock. At the same time, the control signal TX_LP can control the power switch (Power Switch) of the data driver buffer to turn off. For example, the power supply switch 330 of the data drive buffer DD0 is turned off, thereby turning off the power supply of the analog input and output (IO), thereby saving the power consumption of the sending sub-module TX0.

In the embodiment of the present disclosure, when PHY0 quickly enters low power, the analog circuit power supply of PHY0 is turned off, for example, the data driver buffer is turned off, and there is no need to retrain PHY0. Therefore, you can quickly enter and exit low-power mode.

In some embodiments of the present disclosure, the data driving buffer in the target data channel among the multiple data paths in the low power consumption state of the transmitting sub-module TX0 is in an open state. The sending state machine sub-module 210 is configured to: provide a wake-up message to another core through a data-driven buffer in the target data channel.

The data driver buffer in the target data channel remains open and can wake up the receiving end RX1 of the other chip DIE1 in time. The target data channel can be one data channel or multiple data channels. For example, in order to wake up the receiving end RX1 of another chip DIE1 in time, a data channel in the sending sub-module TX0 is kept open, and the data channel kept open is the target data channel. As shown in FIG. 3 , the power supply switch 330 of the data driving buffer DD0 is in an open state. For example, the power supply switch 330 includes a transistor, and the transistor is turned on at a low level. The gate input signal 0 of the transistor of the data driving buffer DD0 indicates a low level, so that the power supply switch 301 is in an open state. Data channel 0 where the data driver buffer DD0 is located is the target data channel.

For example, when the control signal TX_LP is low level, at least part of the circuit structure in the sending sub-module TX0 of the physical layer interface module PHY0 is turned off. The at least part of the circuit structure may include, for example, the data driving buffer DD1,... the data driving buffer DDn. and clock switch unit 320. The data drive buffer DD0 and the clock drive buffer remain open to wake up the receiving end RX1 of the other chip DIE1 in time.

In other embodiments of the present disclosure, the sending sub-module TX0 also includes a sideband signal path, and the sending state machine sub-module 210 is configured to: provide a wake-up message to another core particle through the sideband signal path. In this embodiment, it is not necessary to keep at least one data channel and clock channel in an open state, but an additional sideband signal path needs to be added.

In some embodiments of the present disclosure, the core particle may also include a data bus module (DataFabric, DF) 250.

The data bus module 250 is configured to provide a first data packet (eg, data packet txData) and a first control signal (eg, control signal txLowPower) to the physical layer function module PCA0.

The data bus module 250 controls data communication between various modules in the chip, such as data communication between the processor and the memory module. In the chiplet structure, the data of the data bus module 250 needs to be transmitted across DIEs. For example, when the data bus module 250 of DIE0 needs to send data to DIE1, the data message is first sent to the physical layer coding sub-module PCS of DIE0. The data message sending sub-module 220 in PCS processes the data and then sends it to the physical layer. Layer interface module PHY0. The physical layer interface module PHY0 processes the data packets and sends them to the physical link. After DIE1 receives the data message from the physical layer interface module PHY1, it will send the received data message to the physical layer coding sub-module PCS of DIE1. The data message receiving module in the physical layer coding sub-module PCS will process the data. , and then sent to its own data bus module.

In some embodiments of the present disclosure, the data bus module 250 is further configured to: count the number of invalid data; and in response to the number of invalid data being greater than the first preset threshold, trigger the first control signal to switch to the first model.

If the number of invalid data is greater than the first preset threshold, it indicates that the data bus module 250 has no valid data to send. When the data bus module 250 has no valid data to send, it controls the first control signal to switch to the first mode, provides the first control signal of the first mode to the physical layer encoding sub-module PCS of DIE0, and controls the physical layer encoding sub-module of DIE0. The module PCS and the physical layer interface module PHY0 enter the low power consumption state of the sending sub-module. For example, the first mode of the first control signal is the low-level signal of the control signal txLowPower. The low-level signal of the control signal txLowPower is referred to as the “txFastPM_Entry signal” in the following. The method of generating the txFastPM_Entry signal can be obtained by counting the number of invalid data sent. When no valid data is sent, a counter is used to count the number of invalid data. When the number of continuously sent invalid data exceeds the first preset threshold, the txFastPM_Entry signal is triggered.

FIG. 4A shows a schematic circuit diagram of a data bus module generating a txFastPM_Entry signal provided by at least one embodiment of the present disclosure.

As shown in Figure 4A, the data bus module 250 at least includes a counter 401, a comparator 402 and a plurality of selectors.

Counter 401 and multiple selectors are used to count invalid data. For example, if the Valid_packet signal is 1, it indicates that the data bus module 250 outputs valid data; if the Valid_packet signal is 0, it indicates that the data bus module 250 outputs invalid data. The Valid_packet signal is a signal generated by the data bus module 250 itself according to whether it needs to transmit valid data. The comparator 402 is used to compare the number of invalid data and the size of the first preset threshold. If the number of invalid data is greater than the first preset threshold, the comparator 402 generates the txFastPM_Entry signal. Regarding the txFastPM_Exit signal in Figure 4A, please refer to the description of Figure 4B.

In some embodiments of the present disclosure, the data bus module 250 includes a data buffer for storing the first data message provided to the physical layer function module. The data bus module 250 is also configured to store valid data in the data buffer. The number is counted; and in response to the number of valid data reaching the second preset threshold, triggering the first control signal to switch to the second mode to provide the first data message to the physical layer interface module.

If the number of valid data in the data buffer is greater than the second preset threshold, it indicates that the data bus module 250 has valid data that needs to be sent. When there is valid data that needs to be sent, the data bus module 250 controls the first control signal to switch to the second mode, provides the first control signal of the second mode to the physical layer encoding sub-module PCS of the core chip DIE0, and controls the physical layer of DIE0. The coding sub-module PCS and the physical layer interface module PHY0 enter the working state of the sending sub-module. For example, the second mode of the first control signal is a high-level signal of the control signal txLowPower. The high-level signal of the control signal txLowPower is referred to as the “txFastPM_Exit signal” in the following. The txFastPM_Exit signal is sent to the PCS to control the PCS and PHY to exit from the low power consumption state and return to the normal working state (Active). The method of generating the txFastPM_Exit signal can be obtained by counting the number of valid data in the data buffer of the data bus module 250 . When the number of valid data exceeds the second preset threshold, txFastPM_Exit is triggered.

FIG. 4B shows a schematic circuit diagram of a data bus module generating a txFastPM_Exit signal provided by at least one embodiment of the present disclosure.

As shown in FIG. 4B, the data bus module 250 at least includes a buffer 410, a comparator 420, a counter 430 and a plurality of selectors.

The counter 430 and multiple selectors are used to count valid data in the buffer. The comparator 420 is used to compare the number of invalid data and the size of the second preset threshold. If the number of valid data is greater than the second threshold, the comparator 402 generates the txFastPM_Exit signal.

Write_Data represents the data packet written to the buffer 410.

The circuit diagram shown in FIG. 4A and FIG. 4B is only an example. Those skilled in the art can design the circuit structure for triggering the txFastPM_Entry signal and the txFastPM_Exit signal by themselves. This disclosure does not limit the circuit structure of the data bus module.

In some embodiments of the present disclosure, as shown in Figure 2, the physical layer function module PCA0 also includes a receiving state machine sub-module 260, a data message receiving sub-module 270 and a control message receiving module 280. The physical layer interface module PHY0 is also configured to: receive communication messages provided from another core die DIE1, and provide the communication messages to the data message receiving sub-module 270 and the control message receiving sub-module 280. The data message receiving sub-module 270 is configured to receive communication messages. The control message receiving sub-module 280 is configured to receive the communication message, and in response to the communication message being the second state entry message, provide the second state entry message to the receiving state machine sub-module. The receiving state machine sub-module 260 is configured to: in response to the second state entry message, control the data message receiving sub-module 270 to stop receiving the second data message, and control the first physical layer interface module PHY0 to switch from the working state to low power consumption. state.

In this embodiment, the core particle DIE0 serves as the receiving end, and DIE1 serves as the sending end. DIE0 receives the communication message from the core particle DIE1 via the physical interface module PHY0. The communication message may be a data message or a control message. As described above, the control message may be any of a state entry message, a wake-up message, and a state exit message.

For example, the receiving sub-module RX0 of the core particle DIE0 receives the communication message provided by the sending sub-module TX1 of the core particle DIE1.

The second state entry message refers to the control message provided by another core particle DIE1 to the core particle DIE0. The above-mentioned first state entry message refers to the control message provided by the core particle DIE0 to the other core particle DIE1. The format of the second-state entry message may be the same as the format of the above-mentioned first-state entry message, or the second-state entry message may be the same as the first-state entry message.

The second data message refers to the data message provided by another core particle DIE1 to the core particle DIE0. The above-mentioned first data message refers to the data message provided by the core particle DIE0 to the other core particle DIE1. The first data packet and the second data packet are different, but the formats of the first data packet and the second data packet may be the same.

In some embodiments of the present disclosure, the control message receiving sub-module 280 can determine whether the communication message is a data message or a control message according to the message format of the communication message. In response to the communication message being the second data message, the data message receiving sub-module 270 provides the second data message to the data bus module 250 . The second data packet is, for example, the data packet rxData in Figure 2 . In response to the communication message being the second state entry message, the second state entry message is provided to the receiving state machine sub-module 260, so that the receiving state machine sub-module 260 controls the data message receiving sub-module 270 to stop receiving the second data message, and Control the first physical layer interface module PHY0 to switch from a working state to a low power consumption state. The second state entry message is, for example, the FPMEntry' message shown in Figure 2.

For example, in response to the communication message being the second state entry message, the receiving state machine sub-module 260 provides the message stop receiving signal Rx_stop to the data message receiving sub-module 270 . The data message receiving sub-module 270 is configured to stop receiving the second data message in response to the message stop receiving signal Rx_stop.

In some embodiments of the present disclosure, the physical layer interface module PHY0 includes a receiving sub-module RX0, and the receiving sub-module RX0 is connected to the receiving state machine sub-module 260. The receiving state machine sub-module 260 is configured to control the receiving sub-module RX0 to switch from the working state to the low power consumption state. For example, in response to the FPMEntry' message, the receiving state machine sub-module 260 controls the receiving sub-module RX0 to switch from the working state to the low power consumption state.

This embodiment can independently control the receiving sub-module and the transmitting sub-module in the two transmission directions of receiving and transmitting to quickly enter a low-power state, and can save chip power consumption when there is no valid data transmission in either direction. When there is no valid data transmission in one direction, the sending sub-module of the sending end and the receiving sub-module of the receiving end are controlled to enter a low-power state to save power consumption, and keep the data channel in the other direction still in working state (the receiving sub-module of the sending end and the sending sub-module of the receiving end is still in normal working condition).

FIG. 4C shows a schematic diagram of independent control of core particles in two transmission directions, receiving and transmitting, provided by at least one embodiment of the present disclosure.

Figure 4C shows the structure of the core particle DIE0 and the core particle DIE1 and the functions of each structure are the same as those in the aforementioned Figure 2 and will not be described again.

As shown in Figure 4C, DIE0 serves as the transmitter and DIE1 serves as the receiver. The sending transmission direction 4000 and the receiving transmission direction 4100 are independent of each other. That is, some embodiments of the present disclosure can independently control the sending sub-module TX0 of DIE0 and the receiving sub-module RX1 of DIE1, and can independently control the receiving sub-module RX0 of DIE0 and the sending sub-module TX1 of DIE1, thereby realizing DIE0 as a sending sub-module. End and DIE1 as the receiving end of the transmission direction and DIE0 as the receiving end and DIE1 as the transmitting end of the independent control of the transmission direction.

In some embodiments of the present disclosure, the receiving state machine sub-module 260 is further configured to provide a fourth control signal to the receiving sub-module RX, so that the receiving sub-module RX enters the low power consumption state from the working state. The fourth control signal is, for example, the control signal RX_LP in FIG. 2 . The control signal RX_LP includes, for example, multiple operating modes. For example, when the control signal RX_LP is low level, it is the first control mode of the control signal RX_LP, and when the control signal RX_LP is high level, it is the second control mode of the control signal RX_LP.

In response to the fourth control signal being in the first control mode, the receiving sub-module RX0 is in the working state. In response to the fourth control signal being in the second control mode, the receiving sub-module RX0 is in the low power consumption state. For example, the receiving sub-module RX0 responds to the low level of the control signal RX_LP and enters the working state; the receiving sub-module RX0 responds to the low level of the control signal RX_LP and enters the low power consumption state.

In some embodiments of the present disclosure, the second control mode of the fourth control signal causes at least part of the circuit structure in the receiving sub-module to be turned off, so that the receiving sub-module is in a low power consumption state, and the first control mode causes at least part of the circuit structure to turn on , so that the receiving sub-module is in working status.

For example, at least part of the circuit structure includes a clock circuit, a data channel, a phase-locked loop, etc. Those skilled in the art can set up a circuit structure that is turned off in a low power consumption state by themselves, and this disclosure does not limit it.

The circuit structure of the receiving sub-module RX0 of the physical layer interface module PHY0 can be similar to the circuit structure of the receiving sub-module RX1 of the physical layer interface module PHY1. The following uses the receiving sub-module RX1 of the physical layer interface module PHY1 as an example to illustrate the reception in conjunction with Figure 3. Circuit structure of submodule RX0.

For example, the receiving submodule RX1 includes multiple data receiving channels for transmitting data messages. Each of the multiple data receiving channels includes a data receiving buffer and a serial-to-parallel conversion unit. The serial-to-parallel conversion unit is connected to the data reception buffer, and the serial-to-parallel conversion unit is configured to receive serial data provided by the data reception buffer and convert the serial data into parallel data. Each data receive buffer is connected to a physical link. For example, data reception channel 0 includes at least buffer 3, serial-to-parallel conversion unit 0 and data reception buffer DR0. Other data reception channels are similar to data reception channel 0, including at least buffers, serial-to-parallel conversion units and data reception buffers.

As shown in Figure 3, the data packets of each data receiving channel are converted into parallel data after passing through the serial-to-parallel conversion unit, and then passed through a buffer and provided to the physical layer coding module PCS.

As shown in Figure 3, the receiving sub-module RX1 also includes multiple clock phase control units and multiple clock switch units. For example, each data receiving channel corresponds to a clock phase control unit and a clock switching unit. For example, data reception channel 0 corresponds to the clock phase control unit 340 and the clock switch unit 350.

The clock switch unit 350 is connected to the clock phase control unit 340 and is connected to the serial-to-parallel conversion unit 0 and the cache 3 . The clock phase control unit 340 is configured to control the phase of the clock signal, and after the phase control of the clock signal, provides the clock signal to the clock switch unit 350, and the clock switch unit 320 is configured to provide the clock signal to the serial-to-parallel conversion unit.

For example, the circuit structure of the receiving sub-module RX0 is the same as the circuit structure of the receiving sub-module RX1 in Figure 3, then the second control mode causes the data receiving buffer in at least one of the multiple data receiving channels in the receiving sub-module RX0 to The controller and clock switching unit are turned off.

In some embodiments of the present disclosure, for example, the control signal RX_LP is received in the receiving sub-module RX0. For example, the control signal RX_LP is provided by a physical layer function module (for example, PCS), so that the receiving sub-module RX0 quickly enters low power in response to the control signal RX_LP. consumption status. Since the physical layer interface module PHY0 enters the low power consumption state and no valid data is sent, the control signal RX_LP can control the power supply switch of the data receiving driver buffer to turn off. For example, the power supply switch 360 of the data receiving buffer DR0 of the data receiving channel 0 is turned off, thereby saving the power consumption of the receiving sub-module RX.

In some embodiments of the present disclosure, the receiving sub-module RX0 in the core chip DIE0 has the data receiving buffer in the target data receiving channel among the multiple data receiving channels in the low power consumption state. The data reception buffer in the target data reception channel remains open and can receive the wake-up message provided by another chip DIE1 in time. The target data receiving channel can be one data receiving channel or multiple data receiving channels. For example, in order to wake up the receiving end RX0 of the core DIE0 in time, the receiving end RX0 of the core DIE0 keeps a data receiving channel open, and the data channel kept open is the target data receiving channel.

In other embodiments of the present disclosure, the receiving sub-module RX0 may also include a sideband signal path, and the receiving state machine sub-module 260 is configured to: receive a wake-up message provided by another core chip through the sideband signal path. In this embodiment, it is not necessary to keep at least one data channel and clock channel in an open state, but an additional sideband signal path needs to be added.

In other embodiments of the present disclosure, the control message receiving sub-module 280 is further configured to send a wake-up message to the receiving state machine sub-module 260 in response to the communication message being a wake-up message. The wake-up message is, for example, the FPMWake' message shown in Figure 2. The receiving state machine sub-module 260 is configured to, in response to receiving the wake-up message, switch the fourth control signal (for example, the control signal RX_LP) to the first control mode to control the receiving sub-module RX to enter the working state. The control message receiving sub-module 280 is further configured to provide the state exit message to the receiving state machine sub-module 260 in response to the communication message being a state exit message. The status exit message is, for example, the FPMExit’ message shown in Figure 2. The receiving state machine sub-module 260 is further configured to control the data message receiving sub-module 270 to start receiving the second data message in response to the state exit message.

For example, in response to the state exit message, the receiving state machine sub-module 260 sends a message receiving indication signal to the data message receiving sub-module to notify the data message receiving sub-module 270 to prepare to receive the second data message.

Figure 5 shows a block diagram of a physical layer coding module PCS or adaptation layer provided by at least one embodiment of the present disclosure.

The physical layer coding module PCS or the adaptation layer Adapter shown in Figure 5 is, for example, applied to the core particle DIE0 or the core particle DIE1 in Figure 2 . The physical layer coding module PCS or the adaptation layer Adapter includes two parts: a data message sending and receiving channel and a control message sending and receiving channel.

The data message sending and receiving channel is used to provide data messages from its own data bus module to other cores under normal working conditions, and to receive data messages from other cores from the physical layer interface module PHY and send them to its own data bus module. Provide this datagram.

Combining Figure 5 and Figure 2, and taking the physical layer coding module PCS shown in Figure 5 or the physical layer coding module whose adaptation layer is the core DIE0 in Figure 2 as an example to illustrate the physical layer coding module provided by at least one embodiment of the present disclosure. .

As shown in Figure 5, in the sending path of the data message sending and receiving path, the PCS receives the data message txData provided by the data bus module and processes it through the data message sending sub-module 220 (for example, performing verification, encoding, etc.) Then send it to a selector. When sending a data message, the selector will select the port D0 input, and the data message txData will be provided to the TXDATA signal line, and provided to the sending sub-module TX0 of the physical layer interface module PHY0 via the TXDATA signal line.

As shown in Figure 2, after the receiving channel of another core chip DIE1 receives the data message rxData (that is, the data message txData provided by DIE0) from PHY0, it sends it to the data message receiving sub-module 2100 and 2100 respectively via the RXDATA signal line. Control message receiving sub-module 2200.

Since a normal data packet is received, the output of the control packet receiving sub-module 2200 is 0. The data message receiving sub-module 2100 will output the processed data message rxData to the data bus module 2300.

As shown in Figure 5, for the receiving channel of the data message sending and receiving path of the core chip DIE0, after receiving the data message rxData (that is, the data message txData provided by DIE1) from PHY1, the data message is sent to the data message via the RXDATA signal line. message receiving sub-module 270 and control message receiving sub-module 280.

Since a normal data packet is received, the output of the control packet receiving sub-module 280 is 0. The data message receiving sub-module 27 0 will output the processed data message rxData to the data bus module 250 .

The control message sending and receiving path is to exchange control messages between PCS to quickly control entering and exiting the low power consumption state.

As shown in Figure 5, in the transmission path of the control message transmission and reception path, the PCS receives the txFastPM_Entry signal from the data bus module, that is, txLowPower=1, to control the PCS to quickly enter the low power consumption mode. The sending state machine sub-module 210 in the PCS will generate the Tx_Stop signal to control the data message sending sub-module 220 to stop normal data sending. The sending state machine sub-module 210 controls the control message sending sub-module 230 to send the FPMEntry control message. The sending state machine sub-module 210 will output the txFastPM_sel signal to the selector to control the selector to select the D1 path to provide the FPMEntry control message. The FPMEntry control report indicates that the sending sub-module TX will enter a low power consumption state. The FPMEntry control message is finally sent to another chip DIE1 through the TXDATA signal line and physical link.

The transmitting state machine sub-module 210 generates a TX_LP signal to control the transmitting sub-module TX0 of the physical layer interface module PHY0 to quickly enter a low power consumption state. PHY0 only reserves one data transmission channel (for example, data transmission channel 0) and clock signal channel in the transmission sub-module TX0 for wake-up, closes other data transmission channels in the transmission sub-module TX0 and performs clock gating on the transmission clock.

The communication message received by the other core particle DIE1 will be sent to the data message receiving sub-module 2100 and the control message receiving sub-module 2200 of the core particle DIE1. Since the FPMEntry control message is received at this time, the control message receiving sub-module 2200 determines that the FPMEntry message is received, and the message will be sent to the receiving state machine sub-module 2400 of the core DIE1. The receiving state machine of the core DIE1 The module will generate the Rx_stop signal to control the data message receiving sub-module 2100 to stop receiving data messages. The receiving state machine sub-module 2400 of the core DIE1 will generate the RX_LP signal to control the circuit of the receiving sub-module RX1 of the physical layer interface module PHY1 of the core DIE1 to quickly enter a low power consumption state. The physical layer interface module PHY1 of the core chip DIE1 only reserves one data receiving channel (for example, data receiving channel 0) and clock signal channel of the receiving sub-module for wake-up, and closes other data receiving channels of the receiving sub-module.

If the sending path receives the txFastPM_Exit signal from the data bus module, that is, txLowPower=0, it controls the PCS to quickly exit the low-power mode. The transmit state machine sub-module 210 will pull down the TX_LP signal to control the TX0 module of the PHY to quickly exit the low power consumption mode. The sending state machine sub-module 210 in the PCS controls the control message sending sub-module 230 to send the FPMWake control message and the FPMExit control message. FPMWake is used to wake up the other party's receiving state machine sub-module. The FPMExit control message is used to tell another chip to resume data reception in the next clock cycle.

The sending state machine sub-module 210 will pull down the Tx_Stop signal to control the data message sending module to start normal data sending.

Before the other core particle DIE1 receives the FPMWake control message, only one data receiving channel and clock signal channel are open for receiving the FPMWake message. After receiving the FPMWake control message, the control message receiving sub-module 2200 will pull down the RX_LP signal, control PHY1 to exit the low power consumption state, and PHY1 will open all data receiving channels.

After receiving the FPMExit control message, the receiving state machine sub-module 2400 pulls the Rx_Stop signal low and controls the data message receiving module 2100 to start receiving data messages normally.

As shown in Figure 5, for the receiving channel of the control message sending and receiving path of the core particle DIE0, before the core particle DIE0 receives the FPMWake control message, only one data receiving channel and a clock signal channel are open for receiving FPMWake messages. . After receiving the FPMWake control message, the control message receiving sub-module 280 will pull down the RX_LP signal, control PHY0 to exit the low power consumption state, and PHY0 will open all data receiving channels.

After receiving the FPMExit control message, the receiving state machine sub-module 260 pulls the Rx_Stop signal low and controls the data message receiving module 270 to start receiving data messages normally.

FIG. 6A shows a schematic diagram of a state machine of a sending submodule provided by at least one embodiment of the present disclosure. FIG. 6B shows a schematic diagram of a state machine of a receiving submodule provided by at least one embodiment of the present disclosure.

As shown in Figure 6A, when the signal TX_LP=1, the sending sub-module of the physical layer interface module quickly enters a low power consumption state and turns off the IO power supply of the data channel of the sending sub-module. When the signal TX_LP=0, it quickly exits the low power consumption state and turns on the IO power supply of the data channel of the sending sub-module.

As shown in Figure 6B, when the signal RX_LP=1, the receiving sub-module of the physical layer interface module quickly enters a low power consumption state and turns off the IO power supply of the data channel of the receiving sub-module. When the signal TX_LP=0, it quickly exits the low-power state and turns on the IO power supply of the data channel of the receiving sub-module.

The core provided by at least some embodiments of the present disclosure controls the PHY to enter and exit the low power consumption mode by sending and receiving interactive control messages from both parties, without requiring additional chip pins. The embodiment of the present disclosure realizes interactive control messages between the two parties by sending the logic of the state machine sub-module and the data bus module, without requiring additional chip pins. Extra chip pins not only increase costs, but also bring inconvenience to chip design. Some embodiments of the present disclosure determine the time point when the PHY safely enters and exits the low-power mode through negotiation between the sending and receiving parties, and can safely turn off the IO power supply of the PHY, thereby saving more power consumption than the gated clock solution. When the PHY enters fast low power mode, turning off the analog driver buffer does not require retraining the PHY. Therefore, you can quickly enter and exit low-power mode.

It should be noted that in some of the above embodiments, the clock signal channel remains open when entering the fast low power mode, but the clock signal is turned off when entering the fast low power mode, and is turned on when exiting the fast low power mode. In other embodiments of the present disclosure, the transition of the clock signal may be used to control the wake-up of the receiving sub-module at the receiving end.

Another embodiment of the present disclosure provides a method for controlling core particles. The core particle includes a physical layer function module and a first physical layer interface module. The first physical layer interface module is used to electrically connect with the second physical layer interface module of another core particle through a physical link. The method includes: in response to the first mode of the first control signal, controlling the physical layer function module to switch from providing a first data message to the first physical layer interface module to providing a first state entry message to the first physical layer interface module. , causing the first physical layer interface module to switch from providing the first data message to another core through the physical link to providing the first state entry message to another core through the physical link, and in the first physical layer interface After the module provides the first state entry message to another core particle, it controls the first physical layer interface module to enter the low power consumption state from the working state. The first state entry message is used to notify the other core particle to enter the low power consumption state. The power consumption of the first physical layer interface module in the low power consumption state is less than the power consumption in the working state.

This control method controls the physical link to transmit status entry messages by sending a state machine sub-module, so that the physical link can transmit not only data messages but also status entry messages, so that the core can be made without adding additional pins. Quickly enter and exit low-power mode.

For example, the physical layer functional module can be a physical layer coding sub-module or an adaptation layer. The adaptation layer is used to select and arbitrate between multiple protocols. The physical layer coding submodule is used to control the physical layer interface module to send and receive data. The physical layer interface module is responsible for signal transmission technology related to electrical characteristics. The physical link may be a wired link or a wireless link (for example, optical fiber, etc.). The embodiments of the present disclosure do not specifically limit the form of the physical link.

For example, as shown in Figure 2, the physical layer function module PCA0 of the core particle DIE0 includes a sending state machine sub-module 210, a data message sending sub-module 220 and a control message sending sub-module 230.

The physical interface module PHY0 provides the message received from the physical layer function module PCA0 to another core chip DIE1 through a physical link. For example, the physical layer function module PCA0 provides the data message txData to the physical interface module PHY0, then the physical interface module PHY0 provides the data message txData to another core chip DIE1 through the physical link; if the physical layer function module PCA0 provides the data message txData to the physical interface module PHY0 provides the first state entry message, and the physical interface module PHY0 provides the first state entry message to another chip DIE1 through the physical link.

The physical layer function module PCA0 switches from providing the data message txData to the physical layer interface module PHY0 to providing the first state entry message to the physical layer interface module PHY0, so that the physical layer interface module PHY0 switches from providing the data message txData to the other core chip DIE1 through the physical link. Providing the data message txData is switched to providing the first state entry message to the other core particle DIE1 through the physical link.

After the physical layer interface module PHY0 provides the first state entry message to the other die DIE1, the physical layer interface module PHY0 is controlled to enter the low power consumption state from the working state. The power consumption of the physical layer interface module PHY0 in the low power consumption state is less than the power consumption in the working state.

In the embodiment of the present disclosure, the core particle responds to the control signal by sending the state machine sub-module, and controls the physical layer function module to use the physical link to transmit the data message and the physical link to transmit the first state entry message, so that the core particle The chip can quickly enter and exit low-power consumption mode without adding additional pins.

As shown in Figure 2, in some embodiments of the present disclosure, the physical layer function module PCA0 may also include a selector. The selector includes a first input terminal (for example, input terminal D0), a second input terminal (for example, input terminal D0 D1), a third input terminal (for example, input terminal S) and an output terminal (for example, input terminal P).

The data message sending sub-module 220 is connected to the input terminal D0, the control message sending sub-module 230 is connected to the input terminal D1, and the output terminal P is connected to the physical layer interface module PHY0.

The sending state machine sub-module 210 is further configured to provide a second control signal to the input terminal S. The second control signal is, for example, the control signal txFastPM_Sel shown in FIG. 2 .

The selector 240 is configured to select the output terminal P to provide the message provided by the data message sending sub-module 220 or the control message provided by the control message sending sub-module 230 to the physical layer interface module PHY0 according to the control signal txFastPM_Sel.

The control messages provided by the control message sending sub-module 230 may not only include the first state entry message described above, but may also include state exit messages, wake-up messages, etc. For exit messages or wake-up messages, please refer to the description below.

In some embodiments of the present disclosure, the control message sending sub-module 230 is also configured to provide a wake-up message and a status exit message to the sending sub-module TX0.

Regarding the wake-up message and status exit message, please refer to the above description and will not be repeated.

This control method is, for example, applied to the core particles provided in any of the foregoing embodiments. This control method corresponds to each part of the aforementioned core particles. Please refer to the description of the aforementioned core particles.

Figure 7A shows a flow chart of a method for a transmitter and a receiver to quickly enter a low power consumption state provided by at least one embodiment of the present disclosure; Figure 7B shows a method for a transmitter to quickly enter a low power state provided by at least one embodiment of the present disclosure. Timing diagram of low power consumption state; FIG. 7C shows a timing diagram of a receiving end quickly entering a low power consumption state provided by at least one embodiment of the present disclosure.

The low power consumption state is referred to as "FastPM state" in the following. The FastPM state is initiated by the PCS of the sending end (eg, die DIE0 in Figure 7A). The receiving end is, for example, the core particle DIE1 in Figure 7A.

As shown in Figure 7A, the method of entering the FastPM state includes steps S701 to S705.

Step S701: The data bus module at the sending end raises the txLowerPower signal to control the PCS at the sending end to enter the txFastPM state, and the PCS at the sending end stops receiving data from the data bus module. The txFastPM state indicates that the sending sub-module enters a low power consumption state. At the beginning, the sending sub-module TX of the sending end is in normal working state. "TX" in Figure 7A represents the transmitting sub-module, and "RX" represents the receiving sub-module.

After the data bus module of DIE0 sends the high TxLowPower signal, no data will be sent. Therefore, the sending direction of the data bus module is idle at this time.

Step S702: The PCS at the sending end sends the FPMEntry control message.

Step S703: After the PCS at the sending end sends the FPMEntry control message, the PCS at the sending end pulls up the TX_LP signal and controls the PHY at the sending end to enter the txFastPM state, that is, the transmitting submodule at the sending end is idle, and the PHY performs clock gating.

Step S704: After receiving the FPMEntry control message, the PCS at the receiving end controls the PCS at the receiving end to enter the rxFastPM state, and the PCS at the receiving end stops receiving data from the PHY at the receiving end to the data bus module at the receiving end. The rxFastPM state indicates that the receiving submodule enters a low power consumption state.

Step S705: The PCS of the receiving end pulls the RX_LP control signal high to control the PHY of the receiving end to enter the rxFastPM state, that is, the receiving sub-module RX of the receiving end is idle.

After receiving rxValid=0, the data bus module of DIE1 does not receive valid data, so the receiving direction of the data bus module of DIE1 is also in an idle state.

As shown in Figure 7B, first, for example, at the rising edge of the i-th clock cycle of the clock signal Clock (i is an integer greater than or equal to 1), the data bus module at the sending end pulls up the txLowPower signal to control the sending status of the PCS at the sending end. The machine enters the low power consumption state from the normal working state and stops sending data packets. Afterwards, for example, in the i+1th clock cycle, the PCS at the sending end sends the FPMEntry message through the TXDATA signal line. In the i+2th clock cycle, the PCS at the transmitting end pulls TX_LP high. In the i+3 clock cycle, the PHY at the transmitting end enters the low power consumption state from the normal working state.

As shown in Figure 7C, for example, first in j clock cycles, the PCS in the receiving end receives the FPMEntry message through the RXDATA signal line. In response to detecting the FPMEntry message, it enters the rxFastPM state and stops receiving data messages. After that, the PCS at the receiving end pulls the RX_LP signal high. Finally, the PHY at the receiving end enters the rxFastPM state. j is an integer greater than i+1.

Figure 8A shows a flow chart of a method for a sending end and a receiving end to exit a fast low power consumption state provided by at least one embodiment of the present disclosure; Figure 8B shows a method for a sending end to quickly exit provided by at least one embodiment of the present disclosure. Timing diagram of low power consumption state; FIG. 8C shows a timing diagram of a receiving end quickly exiting the low power consumption state provided by at least one embodiment of the present disclosure.

As shown in Figure 8A, the method of exiting the FastPM state includes steps S801 to S807.

Step S801: The data bus module at the sending end pulls down the txLowerPower signal and controls the PCS at the sending end to exit the txFastPM state.

Step S802: The PCS of the transmitting end pulls down the TX_LP control signal to control the PHY of the transmitting end to exit the txFastPM state.

Step S803: The PCS at the sending end sends the FPMWake control message.

Step S804: After receiving the FPMWake control message, the PCS at the receiving end controls the PCS at the receiving end to exit the rxFastPM state.

Step S805: The PCS at the receiving end pulls down the RX_LP control signal to control the PHY at the receiving end to exit the rxFastPM state.

Step S806: The PCS at the sending end sends the FPMExit control message and starts sending data messages.

Step S807: After receiving the FPMExit control message, the PCS at the receiving end starts receiving data messages.

As shown in Figure 8B, first, for example, at the rising edge of the mth (m is an integer greater than or equal to 1) clock cycle of the clock signal Clock, the data bus module at the sending end pulls down the txLowPower signal to control the reception in the PCS at the sending end. The state machine exits the low-power state and enters the wake-up state. Afterwards, for example, in the m+1th clock cycle, the PCS at the transmitting end pulls down the TX_LP control signal to control the PHY at the transmitting end to exit the low power consumption state and enter the normal working state. For example, in the i+2th clock cycle, the transmitting end PHY responds to the low-level signal of TX_LP and exits the low-power state. After the PHY at the sending end exits the low-power state and enters the working state, it starts sending valid data messages.

As shown in Figure 8C, for example, first in n clock cycles, the PCS at the receiving end receives the FPMWake message through the RXDATA signal line, exits the low-power working state, and enters the wake-up state. Afterwards, the PCS at the receiving end pulls the RX_LP signal low to control the PHY at the receiving end to exit the low-power state. After the PCS at the receiving end pulls the RX_LP signal low, the PHY at the receiving end exits the low power consumption state. Finally, the PCS at the receiving end sends the FPMExit control message, enters the working state, and starts receiving data normally. n is an integer greater than m+1.

FIG. 9A shows a flow chart of state transition of a sending state machine provided by at least one embodiment of the present disclosure. For example, the sending state machine submodule performs control operations according to the sending state machine shown in FIG. 9A.

As shown in Figure 9A, the state transition of the sending state machine includes steps S901 to S907.

Step S901: The sending state machine is in the TXFPM_IDLE state. The TXFPM_IDLE state indicates that the sending end is in the initial state, that is, it has not received the control signal txLowPower from the bus module to enter low power consumption, and is in the state of sending data messages.

Step S902: When the control signal txLowPower sent to the PCS by the data bus sending module at the sending end is high level (ie, txLowPower==1), the PCS sends the FPMEntry control message. Notify the PCS at the receiving end to enter the FastPM state.

Step S903: After sending the FPMEntry control message, enter the TXFPM_ENTRY_WAIT state. The TXFPM_ENTRY_WAIT state represents the waiting state before entering the FastPM state. At this time, wait for the preset time. If txLowPower switches to low level (ie, txLowPower==0) within this preset time, jump to the TXFPM_EXIT_WAKE state. Or, during the preset waiting time, if a cyclic redundancy check (CRC) error occurs on the receiving end, it will also exit to the TXFPM_EXIT_WAKE state and notify the receiving state machine sub-module of the receiving end to stop the process of entering the rxFastPM state. In the TXFPM_EXIT_WAKE state, the internal circuit of the PHY's transmit submodule is turned on.

Step S904: After waiting for the preset time in the TXFPM_ENTRY_WAIT state, jump to the TXFPM_ENTRY_DONE state, that is, enter the txFastPM state. The receiving sub-module of the PHY at the sending end is turned off. The preset time can be set by those skilled in the art.

Step S905: When txLowPower switches to low level, it indicates that the data bus control module controls the PCS to exit the txFastPM state. The transmit state machine jumps to the TXFPM_EXIT_WAKE state. In the TXFPM_EXIT_WAKE state, open the PHY's TX and send the FPMWake control message.

Step S906: After the FPMWake control message is sent, it enters the TXFPM_EXIT_SENT state. In the TXFPM_EXIT_SENT state, the sender starts sending FPMExit control messages.

Step S907: After sending the FPMExit control message, enter the TXFPM_EXIT_DONE state to completely exit the txFastPM state.

Finally, the sending state machine returns to the TXFPM_IDLE state.

FIG. 9B shows a flow chart of state transition of a receiving state machine provided by at least one embodiment of the present disclosure. For example, the receiving state machine submodule performs control operations according to the receiving state machine shown in FIG. 9B.

As shown in Figure 9B, the state transition of the receiving state machine includes steps S910 to S950.

Step S910: Initially, the receiving state machine is in the RXFPM_IDLE state (that is, the initial state).

Step S920: After receiving the FPMEntry control message, the receiving state machine enters the RXFPM_ENTRY_WAIT state. If the FPMWake control message is received in the RXFPM_ENTRY_WAIT state, step S940 is entered. If the system waits for the preset time in the RXFPM_ENTRY_WAIT state, jump to step S930. The preset time can be set by those skilled in the art.

Step S930: The receiving state machine enters the RXFPM_ENTRY_DONE state. In the RXFPM_ENTRY_DONE state, the receiving sub-module of the PHY at the receiving end is turned off.

Step S940: The receiving state machine enters the RXFPM_ENTRY_WAKE state (ie, wake-up state), exits the rxFastPM state, and opens the internal circuit of the receiving sub-module of the receiving end PHY.

Step S950: In the RXFPM_ENTRY_WAKE state, after receiving the FPMExit control message, it enters the RXFPM_EXIT_DONE state and completely exits the rxFastPM state.

Finally, the receiving state machine returns to the RXFPM_IDLE state.

This control method controls the physical link to transmit status entry messages by sending a state machine sub-module, so that the physical link can transmit not only data messages but also status entry messages, so that the core can be made without adding additional pins. Quickly enter and exit low-power mode.

The following points need to be explained:

(1) The drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures can refer to common designs.

(2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (20)

1. A core particle comprising a physical layer functional module and a first physical layer interface module, wherein the first physical layer interface module is used for being electrically connected with a second physical layer interface module of another core particle through a physical link,

the physical layer function module comprises a sending state machine sub-module, a data message sending sub-module and a control message sending sub-module, wherein the data message sending sub-module is configured to provide a first data message for the first physical layer interface module, the control message sending sub-module is configured to provide a first state entering message for the first physical layer interface module,

the transmit state machine submodule is configured to:

Receiving a first control signal;

in response to the first control signal switching from a second mode to a first mode, controlling the physical layer functional module to switch from providing the first data message to the first physical layer interface module to providing a first state entry message to the first physical layer interface module, so that the first physical layer interface module switches from providing the first data message to the other core particle through the physical link to providing the first state entry message to the other core particle through the physical link; and

after the first physical layer interface module provides the first state entry message for the other core particle, the first physical layer interface module is controlled to enter a low power consumption state from a working state, wherein the first state entry message is used for notifying the other core particle to enter the low power consumption state, the power consumption of the first physical layer interface module in the low power consumption state is smaller than that in the working state,

in the low power state of the first physical layer interface module, the first physical layer interface module includes a target data channel that is kept in an open state or includes a sideband signal path to wake up the second physical layer interface module through the target data channel or the sideband signal path.

2. The core particle of claim 1, wherein the first physical layer interface module comprises a transmit sub-module electrically coupled to the transmit state machine sub-module,

the transmit state machine submodule is configured to control the transmit submodule to enter the low-power-consumption state from the operational state in response to a first mode of the first control signal.

3. The core particle of claim 2, wherein the control message transmitting sub-module is further configured to provide a wake-up message and a state exit message to the transmitting sub-module,

the transmit state machine sub-module is further configured to:

responding to the first control signal to switch from the first mode to the second mode, and controlling the sending sub-module to exit the low-power consumption state and enter the working state;

controlling the control message sending sub-module to provide the wake-up message for the sending sub-module, so that the sending sub-module provides the wake-up message for the other core particle to inform the second physical layer interface module to enter a working state;

and controlling the control message sending sub-module to provide the state exit message for the sending sub-module, so that the sending sub-module provides the state exit message for another core particle to inform the other core particle of recovering the receiving of the first data message in the next clock cycle.

4. The core particle of claim 3, wherein the transmit state machine submodule is further configured to: providing a third control signal to the transmitting sub-module to enable the transmitting sub-module to enter the low power consumption state from the working state,

the transmitting sub-module is in the working state in response to the third control signal being in the first control mode, and is in the low power consumption state in response to the third control signal being in the second control mode.

5. The core particle of claim 4, wherein said second control mode causes at least a portion of the circuit structure in said transmit sub-module to be off, causing said transmit sub-module to be in said low power state, said first control mode causes said at least a portion of the circuit structure to be on, causing said transmit sub-module to be in said operational state,

the second control mode causes at least part of circuit structures in the sending sub-module to be closed, and the method comprises the following steps:

the second control mode enables circuit structures in data transmission channels except the target data channel in the plurality of data transmission channels in the transmission sub-module to be closed; or alternatively

The transmit sub-module further includes the sideband signal path, and the second control mode causes each circuit structure in the plurality of data transmit channels in the transmit sub-module to be closed.

6. The core particle of claim 5, wherein the transmit sub-module further comprises a phase locked loop, a clock phase control unit, and a clock switching unit, the plurality of data transmit channels each comprising a data drive buffer and a parallel to serial conversion unit coupled to the data drive buffer, the parallel to serial conversion unit configured to convert parallel data to serial data to provide the serial data to the data drive buffer, each data drive buffer coupled to the physical link,

the phase-locked loop is connected with the clock phase control unit, the clock switch unit is connected with the clock phase control unit and the parallel-serial conversion unit,

the phase locked loop is configured to generate a clock signal, the clock phase control unit is configured to control a phase of the clock signal, and after the phase control of the clock signal, the clock signal is provided to the clock switching unit, the clock switching unit is configured to provide the clock signal to the parallel-to-serial conversion unit,

The at least part of the circuit structure comprises: a data driving buffer in at least one of the plurality of data transmission channels and the clock switching unit.

7. The core particle of claim 6, wherein the transmit sub-module is in an on state for a data-driven buffer in a target data lane of the plurality of data transmit lanes in the low power state,

the sending state machine submodule is configured to provide the wake-up message to the other core particle through a data drive buffer in the target data channel; or alternatively

The transmit state machine sub-module is configured to provide the wake-up message to the other core via the sideband signal path.

8. The core particle of claim 1, wherein the physical layer function further comprises a selector comprising a first input, a second input, a third input, and an output,

the data message sending sub-module is connected with the first input end, the control message sending sub-module is connected with the second input end, the output end is connected with the physical layer interface module,

the transmit state machine sub-module is further configured to provide a second control signal to the third input,

The selector is configured to:

and selecting the data message provided by the data message sending sub-module or the control message provided by the control message sending sub-module from the output end to the first physical layer interface module according to the second control signal.

9. The core particle of claim 1, wherein the transmit state machine submodule is further configured to:

responding to a first mode of the first control signal, and providing a message stop receiving signal for the data message sending sub-module;

the data message sending submodule is configured to: and responding to the message stop receiving signal, and stopping receiving the first data message.

10. The core particle of claim 3, further comprising:

and the data bus module is configured to provide the first data message and the first control signal for the physical layer functional module.

11. The core particle of claim 10, wherein the data bus module is further configured to:

counting the number of invalid data; and

and triggering the first control signal to switch to the first mode in response to the number of invalid data being greater than a first preset threshold.

12. The core particle of claim 11, wherein the data bus module comprises a data buffer for storing the first data packet provided to the physical layer function module, the data bus module further configured to:

Counting the number of effective data in the data buffer; and

and triggering the first control signal to switch to the second mode in response to the number of the effective data reaching a second preset threshold so as to provide the first data message for the physical layer interface module.

13. The core particle of claim 10, wherein the physical layer function module further comprises a receive state machine sub-module, a data message receive sub-module, and a control message receive sub-module,

the first physical layer interface module is further configured to: receiving a communication message provided from the other core particle and providing the communication message to the data message receiving sub-module and the control message receiving sub-module,

the data message receiving submodule is configured to: the communication message is received and the message is sent to the server,

the control message receiving sub-module is configured to: receiving the communication message and providing the second state entry message to the receive state machine sub-module in response to the communication message being the second state entry message,

the receive state machine module is configured to: and responding to the second state entering message, controlling the data message receiving sub-module to stop receiving the second data message, and controlling the first physical layer interface module to be switched from the working state to the low power consumption state.

14. The core particle of claim 13, wherein the data message receiving sub-module provides the second data message to the data bus module in response to the communication message being the second data message.

15. The core particle of claim 13, wherein the first physical layer interface module comprises a receive sub-module coupled to the receive state machine sub-module,

the receive state machine sub-module is configured to: and controlling the receiving sub-module to be switched from the working state to the low-power consumption state.

16. The core particle of claim 15, wherein the receive state machine submodule is further configured to: providing a fourth control signal to the receiving sub-module to enable the receiving sub-module to enter the low power consumption state from the working state,

and the receiving sub-module is in the working state in response to the fourth control signal being in the first control mode, and is in the low power consumption state in response to the fourth control signal being in the second control mode.

17. The core particle of claim 16, wherein the second control mode causes at least a portion of the circuit structure in the receiving sub-module to be off, causing the receiving sub-module to be in the low power state, the first control mode causes the at least a portion of the circuit structure to be on, causing the receiving sub-module to be in the operational state,

The receiving sub-module comprises a plurality of data receiving channels for transmitting the data message, and the second control mode enables at least part of circuit structures in the receiving sub-module to be closed, and the method comprises the following steps:

the second control mode causes a circuit structure in a data receiving channel other than a target data receiving channel among the plurality of data receiving channels in the receiving sub-module to be turned off; or the receiving sub-module further comprises the sideband signal path, and the second control mode causes each circuit structure in the plurality of data receiving channels in the receiving sub-module to be turned off.

18. The core particle of claim 17, wherein the receive sub-module comprises a clock phase control unit and a clock switching unit, the plurality of data receive channels each comprising a data receive buffer and a serial-to-parallel conversion unit, each data receive buffer being coupled to the physical link, the serial-to-parallel conversion unit being coupled to the data receive buffer, the serial-to-parallel conversion unit being configured to receive serial data provided by the data receive buffer and to convert the serial data to parallel data,

the clock switch unit is connected with the clock phase control unit and connected with the serial-parallel conversion unit,

The clock phase control unit is configured to receive a clock signal, control a phase of the clock signal, and after the phase control of the clock signal, provide the clock signal to the clock switching unit, the clock switching unit is configured to provide the clock signal to the serial-parallel conversion unit,

the at least part of the circuit structure comprises: a data reception buffer in at least one of the plurality of data reception channels and the clock switching unit.

19. The core particle of claim 16, wherein the control message receiving sub-module is further configured to:

responding the communication message as the awakening message, sending the awakening message to the receiving state machine submodule,

the receive state machine sub-module is configured to: responding to the received awakening message, and switching the fourth control signal into the first control mode so as to control the receiving sub-module to enter the working state;

the control message receiving sub-module is further configured to: providing the exit message to the receiving state machine sub-module in response to the communication message being the state exit message,

The receive state machine sub-module is further configured to: and responding to the state exit message, and controlling the data message receiving sub-module to start receiving the second data message.

20. A control method of a core particle, wherein the core particle comprises a physical layer functional module and a first physical layer interface module, the first physical layer interface module is used for being electrically connected with a second physical layer interface module of another core particle through a physical link,

the method comprises the following steps:

controlling the physical layer function module to switch from providing a first data message to the first physical layer interface module to providing a first state entry message to the first physical layer interface module in response to a first mode of a first control signal, causing the first physical layer interface module to switch from providing the first data message to the other core particle via the physical link to providing the first state entry message to the other core particle via the physical link, and controlling the first physical layer interface module to enter a low power consumption state from an operating state after the first physical layer interface module provides the first state entry message to the other core particle,

wherein the first state entry message is used for notifying the other core particle to enter the low power consumption state, the power consumption of the first physical layer interface module in the low power consumption state is smaller than that in the working state,

In the low power state of the first physical layer interface module, the first physical layer interface module includes a target data channel that is kept in an open state or includes a sideband signal path to wake up the second physical layer interface module through the target data channel or the sideband signal path.