CN116399489A - A high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration - Google Patents

Abstract

The invention discloses a high-temperature silicon-based photoelectric pressure sensor chip oriented to on-crystal system integration. The preparation method comprises: a step of deep etching of a Fapper cavity, a step of filling a sacrificial layer, a step of manufacturing an optical waveguide, a step of releasing a sacrificial layer, and air sealing Install steps. The invention adopts the microelectronic deep etching method to directly manufacture a vertical Fab cavity on the silicon-on-insulator wafer, and utilizes the device layer single crystal silicon and the buried oxide layer silicon dioxide of the silicon-on-insulator wafer to manufacture silicon for beam transmission. The base optical waveguide is fully compatible with microelectronics process and has higher production efficiency. At the same time, the manufacturing process of the present invention directly manufactures the silicon-based optoelectronic sensor chip on the silicon wafer, which is beneficial to realize the monolithic integration of the photoelectric hybrid on the silicon-based microelectronic chip on the wafer, and further improves the performance of the system. In addition, the invention manufactures the silicon-based Fabry pressure sensor chip on the wafer, which can work in a high-temperature environment above 120°C.

Description

A high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration

technical field

The invention belongs to the field of electronic technology, and in particular relates to a high-temperature silicon-based photoelectric pressure sensor chip for on-crystal system integration.

Background technique

Since Fabry and Perot invented the multi-beam interferometer, a variety of Fabry sensors based on the principle of multi-beam interference have been developed, and the Fabry pressure sensor is one of the typical applications. The traditional Foper pressure sensor is mainly of fiber optic type, that is, it is mainly composed of a vacuum Foper cavity containing a pressure sensitive diaphragm and an optical fiber. The fiber-optic Fapper pressure sensor has the advantages of strong anti-electromagnetic interference, high measurement accuracy, and can work in high-temperature environments. However, both the processing process of the vacuum Fab cavity and the assembly process of the optical fiber and the vacuum Fab cavity are usually carried out by traditional mechanical processing. Not only is the production efficiency low, but it is also impossible to achieve monolithic integration with integrated circuit chips.

With the development of microelectronics manufacturing process and silicon-based optoelectronics technology, monolithic integration of photonic devices and electronic devices on silicon wafers through microelectronics technology has become a research hotspot. The optoelectronic hybrid integrated circuit integrates optoelectronic devices and microelectronic devices, realizing the combination of the advantages of integrated circuit technology and optical interconnection technology. On the one hand, photoelectric hybrid integration greatly shortens the interconnection length and improves the integration level; on the other hand, optical interconnection improves the communication speed and transmission bandwidth of the big data system, and improves the performance of the integrated circuit system. In addition, based on the microelectronics manufacturing process, silicon-based optoelectronic devices can be manufactured quickly, in large quantities, and with high precision, which significantly improves the production efficiency of optoelectronic devices.

Contents of the invention

The purpose of the embodiment of the present application is to provide a high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration, which does not use the traditional fiber-optic device structure and manufacturing process, but uses the microelectronics deep etching method, directly on the insulator A vertical Fab cavity is manufactured on a silicon-on-silicon (SOI) wafer, and a silicon-based optical waveguide for beam transmission is manufactured using the device layer monocrystalline silicon of the SOI wafer and the buried oxide layer of silicon dioxide. Compared with the traditional manufacturing method of fiber-optic Fabry pressure sensor, the method proposed by the present invention is fully compatible with the integrated circuit technology, can realize on-crystal photoelectric hybrid integration, and greatly improves the production efficiency and system performance.

According to the first aspect of the embodiments of the present application, there is provided a high-temperature silicon-based photoelectric pressure sensor chip for system-on-chip integration, and the method for preparing the chip includes:

Deep etching of the Fab cavity: photolithography and deep etching of silicon, buried oxide layer silicon dioxide, and substrate silicon on the silicon-on-insulator wafer to form an open Fab cavity, vertical pressure-sensitive diaphragm, and air intake groove;

Sacrificial layer filling step: filling the open Fab cavity and air intake groove with a sacrificial layer material that acts as a temporary support, and depositing a sealing layer on the front side of the wafer;

Optical waveguide manufacturing steps: Photolithography etch the device layer of the wafer to form the core layer of the single crystal silicon optical waveguide, and deposit a silicon dioxide layer on the upper surface of the wafer to wrap the core layer to form a single crystal silicon optical waveguide The cladding of the waveguide;

Sacrificial layer releasing step: removing the open Fab cavity, filling the air intake groove with the sacrificial layer material which acts as a temporary support;

Hermetic packaging step: sealing the open Fappel cavity under vacuum condition.

Further, in the step of filling the sacrificial layer, the material of the sacrificial layer is filled by multiple times of alternate spin coating, drying photoresist or spraying photoresist.

Further, the manufacturing steps of the optical waveguide include:

Photolithography etches the device layer of the silicon-on-insulator wafer to form the core layer of the single crystal silicon optical waveguide;

Deposit a silicon dioxide layer on the front side of the silicon-on-insulator wafer, and wrap the core layer with silicon dioxide, the buried oxide layer of the silicon-on-insulator wafer, to form the cladding layer of the single crystal silicon optical waveguide;

The material is temporarily filled in the optical waveguide area to make the deep groove form a process plane.

Further, the axis of the core layer coincides with the central axis of the pressure-sensitive diaphragm in the vertical direction.

Further, the step of releasing the sacrificial layer includes:

Lithographically etching the Fab cavity of the opening and the silicon dioxide layer above the air intake groove to form the release hole of the Fab cavity and the release hole of the air intake groove of the sacrificial layer material;

The sacrificial layer material of the temporary support is removed through the release hole of the Fab cavity and the release hole of the gas inlet groove.

Further, in the hermetic packaging step, under vacuum conditions, the opening of the Fab cavity release hole is sealed by depositing a sealing structure; the materials of the sealing structure include metal paste, glass paste, polyamide Imine, SU8, BCB, silica, epoxy resin, metal coating, sodium ion-containing glass wafer, silicon wafer; the deposition method of the sealing structure includes screen printing, flip-chip bonding, chemical vapor deposition , Sacrificial layer adhesion effect method, anodic bonding, thermocompression bonding, laser local heating.

According to the second aspect of the embodiment of the present application, there is provided a Faptor pressure sensor chip with a differential function, which is monolithically integrated with a Faptor pressure sensor chip with a vertical sensitive diaphragm and a capacitive pressure sensor chip, The preparation method of the pressure sensor comprises:

Deep etching of the Fab cavity: photolithography and deep etching of silicon, buried oxide layer silicon dioxide, and substrate silicon on the silicon-on-insulator wafer to form an open Fab cavity, vertical pressure-sensitive diaphragm, and air intake groove;

Sacrificial layer filling step: filling the open Fab cavity and air intake groove with a sacrificial layer material that acts as a temporary support, and depositing a sealing layer on the front side of the wafer;

Optical waveguide manufacturing steps: Photolithography etch the device layer of the wafer to form the core layer of the single crystal silicon optical waveguide, and deposit a silicon dioxide layer on the upper surface of the wafer to wrap the core layer to form a single crystal silicon optical waveguide The cladding of the waveguide;

The first sacrificial layer releasing step: removing the sacrificial layer material filled in the air intake groove and acting as a temporary support;

Parallel plate capacitor manufacturing steps: depositing a silicon dioxide layer with an electrical insulation function on the inner wall of the air inlet slot, and depositing a metal layer on the outer wall of the Fapp cavity and its opposite side wall as a parallel plate capacitor plate;

The second sacrificial layer releasing step: removing the sacrificial layer material filled with temporary support in the opened Fab cavity;

Hermetic packaging step: sealing the open Fappel cavity under vacuum condition.

Further, the manufacturing steps of the parallel plate capacitor include:

Depositing a silicon dioxide layer with an electrical insulation function on the inner wall of the air intake groove;

Depositing a metal layer on the outer wall of the sealed vacuum Fapper cavity and its opposite side wall as the polar plate of the parallel plate capacitor;

The pole plates of the parallel plate capacitors are drawn out to the upper surface of the wafer to form pads.

The technical solutions provided by the embodiments of the present application may include the following beneficial effects:

First, adopt microelectronics deep etching method to directly fabricate a vertical Fab cavity on the SOI wafer, and at the same time fabricate a silicon-based optical fiber for beam transmission using the single crystal silicon of the device layer and the buried oxide layer of silicon dioxide on the SOI wafer. Waveguide, fully compatible with microelectronics technology, can be mass-produced on a large scale;

Second, the manufacturing process of the present invention directly manufactures silicon-based optoelectronic sensor chips on silicon wafers, which is conducive to the realization of monolithic integration of photoelectric hybrids on silicon-based microelectronic chips on the wafer, and improves the performance of the system;

Thirdly, the present invention manufactures a silicon-based Fabry pressure sensor chip on a wafer, which can work in a high-temperature environment above 120°C.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application.

Figure 1 is a flow chart of the manufacturing process of a high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration, in which (a) in Figure 1 to (h) in Figure 1 are wafer sections in each process picture;

Figure 2 is a manufacturing process flow chart of a high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration, in which (a) in Figure 2 to (g) in Figure 2 are top views of wafers in each process ;

Fig. 3 is a schematic diagram of a three-dimensional structure of a high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration;

Figure 4 is a schematic diagram of the working principle of a high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration, where (a) in Figure 4 is a cross-sectional view of the wafer, and (b) in Figure 4 is a top view of the wafer;

Fig. 5 is a structural schematic diagram of a Fapau pressure sensor chip with a differential function;

FIG. 6 is a schematic structural diagram of a double-sided Fappaut pressure sensor chip with a differential function.

Reference numerals: SOI wafer 1, buried oxide layer silicon dioxide 2, Fappel cavity 3, vertical direction pressure sensitive diaphragm 4, air inlet groove 5, sacrificial layer material 6, upper surface silicon dioxide layer 7, core layer 8, cladding layer 9, material 10, release hole 11 of Faper cavity, release hole 12 of gas inlet groove, sealing structure 13, vacuum Faper cavity 14, first interface 15, second interface 16, silicon dioxide layer 17, pole plate 18.

Detailed ways

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application.

The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present application, first information may also be called second information, and similarly, second information may also be called first information. Depending on the context, the word "if" as used herein may be interpreted as "at" or "when" or "in response to a determination."

The following is an example of an SOI-based Fapper pressure sensor chip, but the scope of application of the present invention is not limited to the Fapper pressure sensor chip and SOI wafer, and is also applicable to other devices with vertically sensitive structures. Fabrication of sensor chips.

Figure 1 shows a cross-sectional view (left) and a top view (right) of the manufacturing process flow of a Fappon-style pressure sensing chip with a vertical sensitive film based on an SOI wafer. In this embodiment, the chip is manufactured using an SOI wafer 1 with a thicker device layer as a material ((a) in FIG. 1 ).

Deep etching step of Fab cavity 3: photolithography and deep etching of device layer silicon, buried oxide layer silicon dioxide 2, substrate silicon on SOI wafer 1 device layer to form open Fab cavity 3, vertical pressure sensitive film Sheet 4, air intake groove 5 ((b) in Figure 1, (a) in Figure 2).

Sacrificial layer filling step: filling the open Fab cavity 3 and air intake groove 5 with a sacrificial layer material 6 that acts as a temporary support, and depositing a sealing layer on the front side of the wafer; specifically:

Firstly, fill the sacrificial layer material 6 which acts as a temporary support in the open Fapp chamber 3 and air inlet groove 5 , preferably by multiple times of alternating spin coating, drying photoresist or spraying photoresist. Then, deposit a sealing layer on the front side of the SOI wafer, wherein the material of the sealing layer includes but not limited to polyimide, SU8, BCB, silicon dioxide, preferably deposited by plasma enhanced chemical vapor deposition (PECVD) Upper surface silicon dioxide layer 7 ((c) in FIG. 1 , (b) in FIG. 2 ).

Optical waveguide manufacturing steps: photoetching the device layer of the wafer to form the core layer 8 of the single crystal silicon optical waveguide, and depositing a silicon dioxide layer on the upper surface of the wafer, wrapping the core layer 8 to form a single crystal The cladding 9 of the silicon optical waveguide; specifically:

The device layer of the SOI wafer is photolithographically etched to form the core layer 8 of the single crystal silicon optical waveguide ((d) in FIG. 1 and (c) in FIG. The central axes of the pressure-sensitive diaphragms 4 in the vertical direction coincide.

A silicon dioxide layer is deposited on the upper surface of the SOI wafer by PECVD, and the core layer 8 is wrapped with the buried oxide layer silicon dioxide 2 of the SOI wafer to form a cladding layer 9 of a single crystal silicon optical waveguide (Fig. 1 (e) in Fig. 2, (d) in Fig. 2).

The material 10 is temporarily filled in the optical waveguide area to make the deep groove form a process plane, preferably by multiple alternate spin coating, drying photoresist or spraying photoresist.

Sacrificial layer release step: removing the open Fab cavity 3, filling the air intake groove 5 with the sacrificial layer material 6 which acts as a temporary support;

Specifically, photolithography etches the upper surface silicon dioxide layer 7 above the open Fapp cavity 3 and the air inlet groove 5 to form the Fab cavity release hole 11 and the air inlet groove release hole 12 of the sacrificial layer material 6 respectively. ((f) in Figure 1, (e) in Figure 2). Preferably, acetone or glue remover is used to remove the temporarily supported sacrificial layer material 6 and the material 10 temporarily filled in the optical waveguide region ((g) in FIG. 1 , (f) in FIG. 2 ).

Hermetic packaging step: sealing the open Fapp chamber 3 under vacuum condition;

Specifically, under vacuum conditions, the release hole 11 of the Fapp chamber is sealed by depositing a sealing structure 13, as shown in (h) in FIG. 1 and (g) in FIG. 2 , forming a vertically sensitive diaphragm Absolute-pressure vacuum fapper cavity 14, and at the same time, the high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration is formed. The materials of the sealing structure 13 include but are not limited to metal paste, glass paste, polyimide, SU8, BCB, silicon dioxide, epoxy resin, metal plating, sodium ion-containing glass wafer, silicon wafer wait. Deposition methods of the sealing structure 13 include but are not limited to screen printing, flip-chip bonding, chemical vapor deposition, sacrificial layer adhesion effect method, anodic bonding, thermocompression bonding, localized laser heating, and the like.

Fig. 3 is a schematic diagram of a three-dimensional structure of a high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration, and Fig. 4 is a schematic diagram of the working principle of a high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration. As shown in Fig. 3 and Fig. 4, the working principle of the Fapper type pressure sensor chip with vertical sensitive film is that when the light beam enters the vacuum Faber cavity 14 from the core layer 8 of the single crystal silicon optical waveguide, the incident light beam Reflection will occur at the first interface 15 and the second interface 16, and the two beams of reflected light will interfere. When the external pressure increases, the central deformation of the pressure-sensitive diaphragm 4 in the vertical direction increases, and the cavity length of the vacuum Fab cavity 14 shortens. The pressure on the pressure-sensitive diaphragm 4 in the vertical direction can be calculated by obtaining the variation of the cavity length through demodulation. Since the process steps described in the present invention are carried out on silicon wafers, the single-crystal silicon optical waveguide and the silicon-based Fab cavity that make up the Fapau pressure sensor chip are all high-temperature-resistant materials, so they can be used in high-temperature environments above 120°C. work in. In addition, the deep groove parallel plate capacitor structure in the vertical direction occupies a small chip area, and does not necessarily rely on complex silicon-silicon and silicon-glass bonding processes, which is conducive to realizing optoelectronic monolithic on the wafer with the signal processing part integrated.

The present application also provides a Fapole pressure sensor chip with a differential function monolithically integrated with a Fapole pressure sensor chip with a vertical sensitive diaphragm and a capacitive pressure sensor chip as shown in FIG. 5 . The preparation method of the pressure sensor comprises:

Step of deep etching of Fab cavity 3: photolithography and deep etching of silicon, buried oxide layer silicon dioxide 2, and substrate silicon on the silicon-on-insulator wafer to form an open Fap cavity 3, vertical pressure sensitive diaphragm 4, Air intake slot 5;

Sacrificial layer filling step: filling the open Fab cavity 3 and air inlet groove 5 with a sacrificial layer material 6 for temporary support, and depositing a sealing layer on the front side of the wafer;

Optical waveguide manufacturing steps: photoetching the device layer of the wafer to form the core layer 8 of the single crystal silicon optical waveguide, and depositing a silicon dioxide layer on the upper surface of the wafer, wrapping the core layer 8 to form a single crystal The cladding 9 of the silicon optical waveguide;

The first sacrificial layer releasing step: removing the sacrificial layer material 6 filled in the air intake groove 5 and acting as a temporary support;

Parallel plate capacitor manufacturing steps: depositing a silicon dioxide layer 17 with an electrical insulation function on the inner wall of the air inlet groove 5, and depositing a metal layer on the outer wall of the Fab cavity 3 and its opposite side wall as a parallel plate capacitor. plate 18 of the plate capacitor;

The second sacrificial layer releasing step: removing the sacrificial layer material 6 filled with temporary support in the Fab cavity 3 of the opening;

Hermetic packaging step: sealing the open Fapp chamber 3 under vacuum condition.

Specifically, the difference between this method and the above-mentioned method for preparing a high-temperature silicon-based photoelectric pressure sensor chip for on-chip system integration is that after the optical waveguide manufacturing step, in this method, the sacrificial layer in the gas inlet groove needs to be released first. material, depositing a silicon dioxide layer 17 with electrical insulation and isolation functions on the inner wall of the air inlet slot 5; then, depositing a metal layer on the outer side wall of the Fab cavity 3 and its opposite side wall as a parallel plate capacitor The pole plate 18; then lead the pole plate 18 to the upper surface of the wafer to form a pad 19. The material of the sacrificial layer in the opened Fapp cavity and the material 10 temporarily filled in the optical waveguide area are released again.

The operating principle of the photoelectrically integrated Fappau pressure sensor chip with differential function is that when the external pressure increases, the central deformation of the pressure sensitive diaphragm 4 in the vertical direction increases, and the cavity length of the vacuum Fapp cavity 14 shortens. ; And the spacing of the parallel plate capacitors becomes larger, that is, the width spacing of the air intake groove 5 becomes larger. Therefore, the corresponding pressure change can be obtained by detecting the phase change of the reflected light and the capacitance change caused by the shortening of the cavity length and the increase of the spacing, respectively, which has the function of further amplifying the pressure signal.

FIG. 6 is a schematic structural diagram of a double-sided Fappaut pressure sensor chip with a differential function. When subjected to pressure, the cavity length of the Fappel cavity on the side of absolute pressure becomes shorter, and the cavity length of the Fappel cavity on the side communicating with the outside gas becomes longer, forming a differential structure, which has the function of further amplifying the pressure signal.

In this paper, specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; meanwhile, for those of ordinary skill in the art, according to the present invention Thoughts, there will be changes in the specific implementation and application scope. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (8)

1. A high-temperature silicon-based photoelectric pressure sensor chip for system integration on a crystal, characterized in that the preparation method of the chip comprises: Deep etching of the Fab cavity: photolithography and deep etching of silicon, buried oxide layer silicon dioxide, and substrate silicon on the silicon-on-insulator wafer to form an open Fab cavity, vertical pressure-sensitive diaphragm, and air intake groove; Sacrificial layer filling step: filling the open Fab cavity and air intake groove with a sacrificial layer material that acts as a temporary support, and depositing a sealing layer on the front side of the wafer; Optical waveguide manufacturing steps: Photolithography etch the device layer of the wafer to form the core layer of the single crystal silicon optical waveguide, and deposit a silicon dioxide layer on the upper surface of the wafer to wrap the core layer to form a single crystal silicon optical waveguide The cladding of the waveguide; Sacrificial layer releasing step: removing the open Fab cavity, filling the air intake groove with the sacrificial layer material which acts as a temporary support; Hermetic packaging step: sealing the open Fappel cavity under vacuum condition. 2. The chip according to claim 1, characterized in that, in the step of filling the sacrificial layer, the sacrificial layer is filled by multiple times of alternate spin coating, drying photoresist or spraying photoresist Material. 3. The chip according to claim 1, wherein the manufacturing step of the optical waveguide comprises: Photolithography etches the device layer of the silicon-on-insulator wafer to form the core layer of the single crystal silicon optical waveguide; Deposit a silicon dioxide layer on the front side of the silicon-on-insulator wafer, and wrap the core layer with silicon dioxide, the buried oxide layer of the silicon-on-insulator wafer, to form the cladding layer of the single crystal silicon optical waveguide; The material is temporarily filled in the optical waveguide area to make the deep groove form a process plane. 4 . The chip according to claim 3 , wherein the axis of the core layer coincides with the central axis of the pressure-sensitive diaphragm in the vertical direction. 5. The chip according to claim 1, wherein the step of releasing the sacrificial layer comprises: Lithographically etching the Fab cavity of the opening and the silicon dioxide layer above the air intake groove to form the release hole of the Fab cavity and the release hole of the air intake groove of the sacrificial layer material; The sacrificial layer material of the temporary support is removed through the release hole of the Fab cavity and the release hole of the gas inlet groove. 6. The chip according to claim 1, characterized in that, in the hermetic packaging step, under vacuum conditions, the Fapp cavity of the opening is sealed by depositing a sealing structure; the material of the sealing structure comprises Metal paste, glass paste, polyimide, SU8, BCB, silica, epoxy, metal plating, sodium ion glass discs, silicon wafers; deposition methods for said sealing structures include screen printing , Flip-chip bonding, chemical vapor deposition, sacrificial layer adhesion effect method, anodic bonding, thermocompression bonding, laser local heating. 7. A Fabry type pressure sensor chip with differential function, characterized in that, the Fabry type pressure sensor chip with a vertical sensitive diaphragm is monolithically integrated with the capacitive pressure sensor chip, and the preparation of the pressure sensor Methods include: Deep etching of the Fab cavity: photolithography and deep etching of silicon, buried oxide layer silicon dioxide, and substrate silicon on the silicon-on-insulator wafer to form an open Fab cavity, vertical pressure-sensitive diaphragm, and air intake groove; Sacrificial layer filling step: filling the open Fab cavity and air intake groove with a sacrificial layer material that acts as a temporary support, and depositing a sealing layer on the front side of the wafer; Optical waveguide manufacturing steps: Photolithography etch the device layer of the wafer to form the core layer of the single crystal silicon optical waveguide, and deposit a silicon dioxide layer on the upper surface of the wafer to wrap the core layer to form a single crystal silicon optical waveguide The cladding of the waveguide; The first sacrificial layer releasing step: removing the sacrificial layer material filled in the air intake groove and acting as a temporary support; Parallel plate capacitor manufacturing steps: depositing a silicon dioxide layer with an electrical insulation function on the inner wall of the air inlet slot, and depositing a metal layer on the outer wall of the Fapp cavity and its opposite side wall as a parallel plate capacitor plate; The second sacrificial layer releasing step: removing the sacrificial layer material filled with temporary support in the opened Fab cavity; Hermetic packaging step: sealing the open Fappel cavity under vacuum condition. 8. The chip according to claim 7, wherein the parallel plate capacitance manufacturing step comprises: Depositing a silicon dioxide layer with an electrical insulation function on the inner wall of the air intake groove; Depositing a metal layer on the outer wall of the sealed vacuum Fapper cavity and its opposite side wall as the polar plate of the parallel plate capacitor; The pole plates of the parallel plate capacitors are drawn out to the upper surface of the wafer to form pads.

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