CN116317574A - Method and device for power conversion - Google Patents

Abstract

The application relates to the technical field of electronics, and provides a power conversion method and equipment. The controller receives an output voltage feedback signal from the power conversion circuit and sends a control signal to the power switching tube. The control signal is used for controlling the power switch tube to be periodically conducted according to a constant time period. The time period between the first moment corresponding to the rising edge of one pulse and the second moment corresponding to the falling edge of the pulse of the control signal is the actual conduction time of the power switch tube in one period. The second moment is after the end moment of the preset conduction time corresponding to the pulse, and the first moment is after the start moment of the preset conduction time. According to the embodiment of the application, the length of the actual conduction time is enabled to be closer to the length of the preset conduction time, so that the switching frequency accuracy is improved.

Description

Method and apparatus for power conversion

technical field

The embodiments of the present application relate to the field of electronic technology, and more specifically, to a power conversion method and device.

Background technique

A DC power supply (direct current-direct current, DC-DC) converter (converter) is a device that converts electrical energy of one voltage value into electrical energy of another voltage value in a DC circuit. The DC-DC chip involves a variety of chip control technologies, including control technologies that can be used to generate fixed time pulses, for example, constant on time (constant on time, COT) control, constant off time control, and the like.

Taking COT control as an example, the constant on-time of the DC-DC power switch is controlled by the chip circuit. Generally, a power switch tube is used as a power switch, and the input voltage is converted into an output voltage by turning on and off the power switch tube to drive a load. Currently, the actual turn-on time of the power switch controlled by the chip circuit used for COT control is longer than the preset turn-on time determined according to the circuit parameters of the chip, thereby reducing the accuracy of the switching frequency. The reduction of switching frequency accuracy is likely to reduce the performance of the load chip, and even cause the load chip to restart.

Therefore, how to improve the frequency accuracy of the power switch is an urgent problem to be solved.

Contents of the invention

The present application provides a power conversion method and device, which can improve the frequency accuracy of a power switch.

In the first aspect, a power conversion device is provided, the power conversion device includes a controller and a power conversion circuit, the controller is connected to the power switch tube of the power conversion circuit; the controller is also used to send a control signal to the power switch tube, and control The signal is used to control the power switch to conduct periodically according to a constant time period. The time period between the first moment corresponding to the rising edge of a pulse of the control signal and the second moment corresponding to the falling edge of the pulse is the power The actual conduction time of the switch tube in one cycle; wherein, the second moment is after the end moment of the preset conduction time corresponding to the pulse, the first moment is after the start moment of the preset conduction time, and the preset conduction time It is the theoretical conduction time of the power switch tube in one cycle determined according to the circuit parameters of the controller and the power conversion circuit.

In the above scheme, when the second moment is after the end moment of the preset conduction time, compared with the case where the first moment is the same as the start time of the preset conduction time, the above scheme passes the preset conduction at the first moment After the start moment of the time, the length of the actual conduction time can be reduced, so that the length of the actual conduction time is closer to the length of the preset conduction time, and the influence of the second moment on the conduction after the end of the preset conduction time is reduced. The influence of the length of the on-time, thereby improving the switching frequency accuracy.

In a possible implementation manner, the time period between the second moment and the end moment is a first time period, and the time period between the first moment and the start moment is a second time period, The difference between the length of the first time period and the length of the second time period≤the preset value. Or, the error of the length of the second time period relative to the first time period≤a preset value.

The above scheme can make the lengths of the first time period and the second time closer by limiting the difference between the length of the first time period and the length of the second time period to be less than or equal to the preset value, so that the conduction time is further close to the preset conduction time. The on-time further reduces the influence of the second moment on the length of the on-time after the end of the preset on-time, thereby further improving the accuracy of the switching frequency.

In a possible implementation manner, the controller is further configured to convert the output voltage feedback signal into an error signal, and convert the error signal into a first pre-control signal and a second pre-control signal, and the rising edge of the first pre-control signal The corresponding moment is the same as the start moment of the preset conduction time; the controller is also used to convert the second pre-control signal into the first pre-compensation signal, wherein the second pre-control signal is converted into the first pre-compensation signal Time is the second time period; the controller is further configured to determine the first moment based on the first pre-control signal and the first pre-compensation signal.

In a possible implementation manner, the second time period includes a first compensation time period and a second compensation time period, and the control unit is specifically configured to determine the second pre-compensation signal based on the second pre-control signal and the first reference voltage, wherein , the time between the time corresponding to the rising edge of the second pre-compensation signal and the time when the second pre-control signal crosses the first reference signal is the first compensation period; the control unit is specifically used to set the second pre-compensation signal to The compensation signal is converted into the first pre-compensation signal, and the time for converting the second pre-compensation signal into the first pre-compensation signal is the second compensation time period.

In a possible implementation, when the second pre-control signal is a rising ramp voltage signal, 0V≤the first reference voltage≤the first threshold; or, when the second pre-control signal is a falling ramp voltage signal , the second threshold ≤ the first reference voltage ≤ the power supply voltage.

In a possible implementation manner, the controller is configured to convert the output voltage feedback signal into a first control signal, determine the first moment according to the first control signal and the second reference voltage, and determine the first moment according to the first control signal and the third The reference voltage determines the second moment; wherein, the second reference voltage is different from the third reference voltage, the first moment is delayed by a second time period relative to the moment when the first control signal crosses the second reference voltage, and the second moment is relative to the first A time when the control signal crosses the third reference voltage is delayed by the first time period.

In a possible implementation manner, before the first moment, the reference voltage used for comparison with the first control signal is the second reference voltage; after the first moment and before the second moment, the reference voltage used for comparison with the first control signal The reference voltage for comparison is the third reference voltage.

In a possible implementation, when the first control signal is a rising ramp voltage signal, 0V≤second reference voltage≤first threshold, and the third reference voltage>second reference voltage; or, the first control signal is In the case of a falling ramp voltage signal, the second threshold ≤ the second reference voltage ≤ the power supply voltage, and the third reference voltage < the second reference voltage.

In a second aspect, a power conversion method is provided, which is applied to a controller in a power conversion device, where the power conversion device further includes a power conversion circuit, and the controller is connected to a power switch tube of the power conversion circuit, Including: receiving the output voltage feedback signal of the power conversion circuit; sending a control signal to the power switch tube, the control signal is used to control the power switch tube to conduct periodically according to a constant time period, and the rising edge of a pulse of the control signal corresponds to the first At one moment, the time period between the second moment corresponding to the falling edge of the pulse is the actual conduction time of the power switch tube in one cycle; wherein, the second moment is at the end of the preset conduction time corresponding to the pulse After that, the first moment is after the start moment of the preset conduction time, which is the theoretical conduction time of the power switch tube in one cycle determined according to the circuit parameters of the controller and the power conversion circuit.

The beneficial effect of the second aspect can refer to the first aspect.

In the above solution, the first time period is compensated by the second time period, which can reduce the influence of the first time period on the conduction time, thereby improving the switching frequency accuracy. In a possible implementation manner, the length of the first time period is equal to the length of the second time period. Therefore, the actual conduction time compensated by the second time period can be as close as possible to the preset conduction time.

In a possible implementation manner, the time period between the second moment and the end moment is a first time period, and the time period between the first moment and the start moment is a second time period, The difference between the length of the first time period and the length of the second time period≤the preset value. Or, the error of the length of the second time period relative to the first time period≤a preset value.

In a possible implementation manner, the method further includes: converting the output voltage feedback signal into an error signal, and converting the error signal into a first pre-control signal and a second pre-control signal, the pulse width of the first pre-control signal corresponds to The period is equal to the preset conduction time of the power switch tube; the second pre-control signal is converted into the first pre-compensation signal, wherein the time for converting the second pre-control signal into the first pre-compensation signal is the second time period; based on The first pre-control signal and the first pre-compensation signal define a control signal.

In a possible implementation manner, the second time period includes the first compensation time period and the second compensation time period, and the method further includes: determining the second pre-compensation signal based on the second pre-control signal and the first reference voltage, wherein the first The time between the time corresponding to the rising edge of the two pre-compensation signals and the time when the second pre-control signal crosses the first reference signal is the first compensation period; convert the second pre-compensation signal into the first pre-compensation signal, the time for converting the second pre-compensation signal into the first pre-compensation signal is the second compensation time period.

In a possible implementation, when the second pre-control signal is a rising ramp voltage signal, 0V≤the first reference voltage≤the first threshold; or, when the second pre-control signal is a falling ramp voltage signal , the second threshold ≤ the first reference voltage ≤ the power supply voltage.

In a possible implementation, the method further includes: converting the output voltage feedback signal into a first control signal, determining the first moment according to the first control signal and the second reference voltage, and determining the first moment according to the first control signal and the third reference voltage The voltage determines the second moment; wherein, the second reference voltage is different from the third reference voltage, the first moment is delayed by a second time period relative to the moment when the first control signal crosses the second reference voltage, and the second moment is relative to the first The timing at which the control signal crosses the third reference voltage is delayed by a first period of time.

In a possible implementation manner, before the first moment, the reference voltage used for comparison with the first control signal is the second reference voltage; after the first moment and before the second moment, the reference voltage used for comparison with the first control signal The reference voltage for comparison is the third reference voltage.

In a possible implementation, when the first control signal is a rising ramp voltage signal, 0V≤second reference voltage≤first threshold, and the third reference voltage>second reference voltage; or, the first control signal is In the case of a falling ramp voltage signal, the second threshold ≤ the second reference voltage ≤ the power supply voltage, and the third reference voltage < the second reference voltage.

In the third aspect, a power chip is provided, which is applied to a power conversion device, and the power conversion device further includes a power conversion circuit composed of a power switch tube, and a power chip is used to receive an output voltage feedback signal of the power conversion circuit ; The power supply chip is also used to send a turn-on time control signal to the power switch tube, the turn-on time control signal is used to control the power switch tube to be turned on within a constant turn-on time, and the turn-on time The period corresponding to the pulse width of the control signal is the turn-on time of the power switch tube, wherein the first moment corresponding to the falling edge of the turn-on time control signal is relative to the end of the designed turn-on time of the power switch tube The moment is delayed by the first time period, and the second time period corresponding to the rising edge of the conduction time control signal is delayed by the second time period relative to the start time of the design conduction time of the power switch tube, and the second time period used to compensate for the first time period.

Description of drawings

Figure 1 shows a schematic block diagram of a fixed pulse controlled DC-DC converter used.

FIG. 2 shows a circuit architecture diagram of a chip for generating fixed time pulse control and a corresponding timing diagram.

FIG. 3 shows a schematic diagram of a power conversion method 100 provided in the present application.

Fig. 4 is a schematic block diagram of an example of a power conversion device provided by the present application.

Fig. 5 shows a schematic block diagram of a control circuit 1 for a power conversion device provided by the present application.

Fig. 6 shows a schematic block diagram of a control circuit 1-1 for a power conversion device provided in the present application and a corresponding timing diagram.

FIG. 7 shows a schematic block diagram of a control circuit 1-2 for a power conversion device provided in the present application and a corresponding timing diagram.

FIG. 8 shows a schematic block diagram of a control circuit 2 for a power conversion device provided by the present application.

Fig. 9 shows a schematic block diagram of a control circuit 2-1 for a power conversion device provided in the present application and a corresponding timing diagram.

FIG. 10 shows a schematic block diagram of the control circuit 2-2 provided in the present application and a corresponding timing diagram.

FIG. 11 shows a schematic block diagram and a corresponding timing diagram of an example of the control circuit 2 - 1 and the sequential logic module in the control circuit 2 - 2 provided in the present application.

Detailed ways

The DC-DC chip involves a variety of chip control technologies, including control technologies that can be used to generate fixed time pulses, such as COT control, constant off-time control, and so on.

Figure 1 shows a schematic block diagram of a fixed pulse controlled DC-DC converter used. The DC-DC converter shown in Figure 1 is suitable for many different power conversion topologies, such as buck (Buck), boost (Boost), boost-buck (Buck-Boost), converter (Inverter), etc. power conversion topologies. In this application, a DC-DC converter using COT control is taken as an example for illustration, and this application is also applicable to constant off-time control and other DC-DC architectures using fixed pulse control.

As shown in Figure 1, in the control circuit of the constant on-time control switching power supply, the constant on-time control circuit is in the box, and the power conversion circuit is outside the box. In the power conversion circuit, the power tube (upper power tube Q1 and power tube lower tube Q2) is used as a switch, and the power conversion circuit converts the input voltage VIN into an output voltage V _O to drive the load by turning on and off the power tube (load). Among them, the conduction time of Q1 is T _on , I _ripple is the ripple of the inductor current I _Lo , V _ripple is the ripple of the output voltage V _O , V _ref is the internal reference voltage of the chip, I _load is the load current, and the capacitor C _oThe series connection is the equivalent series resistance (ESR). In the constant on-time control circuit, the feedback received by the inverting input terminal of the high-speed comparator is V _ripple , and the voltage at the non-inverting input terminal is V _ref . The high-speed comparator outputs an error signal. The error signal and the signal output by the masking time unit pass through the AND gate and then are transmitted to the switching logic unit. The switching logic unit also receives the pulse signal from the one-shot circuit. The switching logic unit determines whether to output driving high level (driving high, DRVH) or driving low level (driving low, DRVL) according to the received signal. When the switching logic unit outputs DRVH, Q1 is turned on and Q2 is turned off; when the switching logic unit outputs DRVL, Q2 is turned on and Q1 is turned off.

This COT control technology uses a fixed T _on , and the on-time of Q1 is the starting point of a cycle. After the on-time is over, the turn-off of Q1 is determined by the crossover of the V _ripple and the internal reference voltage V _ref Time to complete a cycle of Q1 on and off.

FIG. 2 shows a circuit architecture diagram of a chip for generating fixed time pulse control and a corresponding timing diagram. As shown in (a) in FIG. 2 , the power switch can be understood as Q1 and Q2 in FIG. 1 . The units or modules in (a) in FIG. 2 other than the power switch tube correspond to the units or modules in the box in FIG. 1 . Specifically, the logic #1 unit in (a) in FIG. 2 corresponds to the switch logic #1 unit in FIG. 1, and the pulse width modulation (pulse width modulation, PWM) signal output by the logic #1 unit drives the power switch tube , the conduction or closure of the power switch tube is controlled by the PWM signal. The error comparator in (a) in Figure 2 corresponds to the high-speed comparator in Figure 1. The inverting input terminal of the error comparator receives V _ripple , the positive input terminal is V _ref , and the output terminal outputs an error signal (ERR ). The circuit in the dotted line box in (a) in FIG. 2 corresponds to the one-shot circuit in FIG. 1 . The circuit in the dotted box includes an inverter, an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), a capacitor C, a circuit supply voltage (voltage common collector, VCC), a current source, and T _on Comparator #1. (b) in FIG. 2 shows a time pulse of the PWM signal, and the width of the time pulse is the time required for the PWM signal to maintain a high potential, or can be understood as T _on . Wherein, the width of the time pulse is the time period between the moment corresponding to the rising edge of the time pulse and the moment corresponding to the falling edge of the time pulse.

Combining (a) and (b) in FIG. 2 , it can be understood that the error comparator in the circuit architecture outputs an error signal, and the error signal outputs a PWM signal after being processed by the logic #1 unit. The logic #1 unit is also used to generate the rising and falling edges of the timing pulses of the PWM signal. In a digital circuit, the moment (moment) when the digital level jumps from a low level (digital "0") to a high level (digital "1") is called a rising edge. In a digital circuit, the moment (moment) when the digital level jumps from a high level (digital "1") to a low level (digital "0") is called a falling edge. Among them, the processing time delay of the logic #1 unit is Td2. It can be seen from (b) in FIG. 2 that there is a difference of Td2 between the time corresponding to the rising edge of the PWM signal and the time corresponding to the rising edge of the ERR signal. On the one hand, the PWM signal is used to control the power switch to turn on or off; on the other hand, the circuit in the dotted box receives the PWM signal and generates a signal that rises or falls linearly according to a fixed slope, T _{on_RAMP} . T _{on_RAMP} in (a) in FIG. 2 is described by taking a rising ramp signal as an example. The moment when T _{on_RAMP} starts to rise is also the moment corresponding to the rising edge of the PWM signal. The intersection of T _{on_RAMP} and T _{on_REF} triggers the circuit in the dotted box to output the T _{on_pulse} signal. The delay between the moment when the circuit in the dotted line box outputs the T _{on_pulse} signal and the moment when the logic #1 unit receives the T _{on_pulse} is Td2, or the time delay for the logic #1 unit to process the T _{on_pulse} signal is Td2. It can be seen from (b) in FIG. 2 that there is a difference of Td2 between the time corresponding to the rising edge of T _{on_pulse} and the time corresponding to the falling edge of the PWM signal. Specifically, in the circuit in the dotted line box, it is necessary to compare the potentials of T _{on_RAMP} and T _{on_REF} by the T _on comparator #1 to determine whether T _{on_RAMP} and T _{on_REF} cross. The delay of T _on comparator #1 is Td1. It can be seen from (b) in FIG. 2 that there is a difference of Td1 between the time when T _{on_RAMP} and T _{on_REF} cross and the time corresponding to the rising edge of T _{on_pulse} . Among them, T _{on_REF} satisfies the following formula:

具体地，在虚线框的电路中，PWM信号经过反相器后生成重置信号。N型金氧半场效晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)与电容C并联，N型MOS管接收重置信号，电容C的电压V_C根据固定斜率线性上升。T_on比较器#1的正向输入端的输入信号为T_{on_RAMP}，T_{on_RAMP}即为电容C的电压信号，呈现为上升型斜坡信号。电流源提供的电路I＝V_ref/R，R为电流源的电阻值；图2中的VCC的电压值为V_VCC。一种可能的实现方式中，本申请中的VCC可以替换为芯片的工作电压，例如漏极电源电压(drain power voltage，VDD)，芯片的工作电压的电压值为V_VDD，相应地，本申请中的V_VCC可以替换为V_VDD。T _{on_REF} = V _ref · Duty Cycle (formula 1). Among them, Duty Cycle is

Specifically, in the circuit in the dotted line box, the reset signal is generated after the PWM signal passes through the inverter. An N-type metal-oxide-semiconductor field-effect transistor (MOSFET) is connected in parallel with the capacitor C, and the N-type MOS transistor receives the reset signal, and the voltage V _C of the capacitor C rises linearly according to a fixed slope. The input signal of the positive input terminal of the T _on comparator #1 is T _{on_RAMP} , and T _{on_RAMP} is the voltage signal of the capacitor C, presenting a rising ramp signal. The circuit provided by the current source is I=V _ref /R, where R is the resistance value of the current source; the voltage value of VCC in FIG. 2 is V _VCC . In a possible implementation manner, VCC in the present application can be replaced by the working voltage of the chip, such as the drain power voltage (drain power voltage, VDD), and the voltage value of the working voltage of the chip is V _VDD , correspondingly, the present application V _VCC in can be replaced by V _VDD .

可以理解的是，在设计上述电路架构时，对于设计者来说，该电路架构的电路参数是已知的。电路参数包括但不限于电阻、电容、电感、V_IN、V_O。如公式2所示，预设导通时间可以根据R、C、以及V_IN、V_O计算获得。预设导通时间可以理解为电路处于理想状态下(例如不存在时延)PWM信号的维持为高电位的时间。另外，PWM信号的一个或多个脉冲对应的预设导通时间的开始时刻和结束时刻也可以通过计算或仿真获得。Based on the circuit architecture shown in FIG. 2 , the preset on-time, ie T _ideal , satisfies the following formula: T _ideal =R·C·Duty Cycle (Formula 2). Among them, R is the resistance value of the current source, C is the capacitance value that generates T _{on_RAMP} , both R and C are preset fixed values inside the chip, and Duty Cycle is

It can be understood that, when designing the above circuit architecture, the circuit parameters of the circuit architecture are known to the designer. Circuit parameters include but not limited to resistance, capacitance, inductance, V _IN , V _O . As shown in Equation 2, the preset on-time can be calculated according to R, C, and V _IN , V _O. The preset on-time can be understood as the time during which the PWM signal remains at a high potential when the circuit is in an ideal state (for example, there is no time delay). In addition, the start time and end time of the preset conduction time corresponding to one or more pulses of the PWM signal can also be obtained through calculation or simulation.

所以根据V_O和V_IN发送变化，T_on的值也会随之变化。导通时间可以理解为具体实现中PWM信号的维持为高电位的时间。In the above circuit architecture, the on-time, ie T _on , satisfies the following formula: T _on =R·C·Duty Cycle+Td1+Td2 (Formula 3). Among them, R is the resistance value of the current source, C is the capacitance value that generates T _{on_RAMP} , both R and C are preset fixed values inside the chip, and Duty Cycle is

So according to V _O and V _IN changes, the value of T _on will also change accordingly. The conduction time can be understood as the time during which the PWM signal is maintained at a high potential in a specific implementation.

温度、工艺等变化。开关频率精度过低很可能造成DC-DC产品的纹波过大、效率和热表现波动大、或对电源后级(对频率精度敏感的)负载电路产生负面影响。Combining Equation 2 and Equation 3, it can be seen that the conduction time is affected by the delay times Td1 and Td2, which will be longer than the preset conduction time, thus resulting in a decrease in the accuracy of the DC-DC switching frequency. In addition, switching frequency accuracy also varies with

Changes in temperature, process, etc. Too low switching frequency accuracy is likely to cause excessive ripple of DC-DC products, large fluctuations in efficiency and thermal performance, or have a negative impact on the load circuit of the power supply stage (sensitive to frequency accuracy).

In view of this, the method and device for power conversion provided by the present application can improve switching frequency accuracy.

FIG. 3 shows a schematic diagram of a power conversion method 100 provided in the present application. The method can be applied to power conversion equipment, and the power conversion equipment includes a controller and a power conversion circuit, specifically, the controller is connected to a power switch tube of the power conversion circuit. In a possible implementation manner, the power conversion device here can be understood as a DC-DC converter.

S101, the power conversion circuit sends an output voltage feedback signal to the controller, and correspondingly, the controller receives the output voltage feedback signal from the power conversion circuit.

In a possible implementation manner, the output voltage feedback signal can be understood as V _ripple mentioned above.

S102, the controller sends a control signal to the power switch tube, and correspondingly, the power switch tube receives the control signal from the controller.

Wherein, the control signal is used to control the power switch to conduct periodically according to a constant time period. The time period between the first moment corresponding to the rising edge of a pulse of the control signal and the second moment corresponding to the falling edge of the pulse is the actual turn-on time of the power switch tube in one cycle. Wherein, the second moment is after the end moment of the preset conduction time corresponding to the pulse, and the first moment is after the start moment of the preset conduction time, and the preset conduction time is determined according to the circuit parameters of the controller and the power conversion circuit The theoretical conduction time of the power switch tube in one cycle. For example, reference may be made to formula 2 for the determination method of the preset on-time. The time period between the second moment and the end moment of the preset on-time may be referred to as a first time period. In a possible implementation manner, the second moment may be understood as the moment corresponding to the falling edge of the PWM signal in (b) in FIG. 2 . The first period of time can be understood as Td1 and Td2 in (b) in FIG. 2 . The first moment is after the start moment of the preset conduction time. It can be understood that the first moment is different from the moment corresponding to the rising edge of the PWM signal in (b) in FIG. 2 . Specifically, the time corresponding to the rising edge of the PWM signal in (b) in FIG. 2 is the same as the start time of the preset conduction time. On-time #1) is longer than the preset on-time. While the first moment is after the start moment of the preset conduction time, in this case the conduction time of the power switch (that is, the above-mentioned actual conduction time, referred to as conduction time #2 for convenience below) is shorter than the conduction time Turn-on time #1, and can reduce the influence of the first time period on the actual turn-on time of the power switch tube, thereby improving the accuracy of the switching frequency. The time period between the first moment and the start moment of the preset conduction time may be referred to as a second time period. In other words, the second time period can partially or completely compensate for the influence of the first time period on the actual turn-on time.

In a possible implementation manner, the difference between the length of the first time period and the length of the second time period is ≤ a preset value. For example, the preset value is 5ms, and the second time period=the first time period±5ms, or the preset value can also be other specific values, which are not limited in this application. In another possible implementation manner, the error of the length of the second time period relative to the first time period is ≤ a preset value. The error here can be understood as a relative error, for example, the preset value is 5%, the ratio of the absolute error between the second time period and the first time period to the first time period is ≤5%, or the preset value can also be other specific value, which is not limited in this application. By limiting the size relationship between the length of the first time period and the length of the second time period, the lengths of the first time period and the second time can be made closer, so that the length of the actual conduction time of the power switch tube is further closer to the preset conduction time. The length of the on-time further reduces the influence of the second moment on the length of the actual on-time after the end of the preset on-time, thereby further improving the accuracy of the switching frequency.

Two possible implementations of the method 100 are given below.

Implementation method one:

Step a1, the controller converts the output voltage feedback signal into an error signal, and converts the error signal into a first pre-control signal and a second pre-control signal, and the time corresponding to the rising edge of the first pre-control signal is the same as the preset lead The start time of the pass time is the same.

Step a2, the controller converts the second pre-control signal into the first pre-compensation signal.

Wherein, the time spent converting the second pre-control signal into the first pre-compensation signal is the second time period.

Step a3, the controller determines the first moment based on the first pre-control signal and the first pre-compensation signal.

It can be understood that the controller acquires the second pre-control signal first, and acquires the first pre-compensation signal after a second time period, and then determines the first moment based on the first pre-control signal and the first pre-compensation signal. Specifically, the first moment is a moment delayed by a second time period relative to the moment corresponding to the rising edge of the first pre-control signal.

In a possible implementation manner, the second time period includes the first compensation time period and the second compensation time period, and step a3 may be implemented according to the following steps.

Step a3-1, the controller determines the second pre-compensation signal based on the second pre-control signal and the first reference voltage.

Wherein, the time between the moment corresponding to the rising edge of the second pre-compensation signal and the moment when the second pre-control signal crosses the first reference signal is the first compensation time period.

In step a3-2, the controller converts the second pre-compensation signal into the first pre-compensation signal, and the time taken to convert the second pre-compensation signal into the first pre-compensation signal is the second compensation time period.

In this possible implementation manner, when the second pre-control signal is a rising ramp voltage signal, 0V≤the first reference voltage≤the first threshold (condition 1). For example, the first threshold here can be a reference voltage close to 0V. Optionally, 0<the first reference voltage≤the first threshold. For example, the first reference voltage may be 0.01V, 0.02V, or 0.015V, etc., or other voltage values satisfying condition 1. Alternatively, when the second pre-control signal is a falling ramp voltage signal, the second threshold value≤the first reference voltage≤the power supply voltage (condition 2). Optionally, the second threshold≦first reference voltage<supply voltage. For example, the first reference voltage may be a power supply voltage of -0.01V, or a power supply voltage of -0.02V, or a power supply voltage of -0.015V, etc., or may be other voltage values satisfying condition 2.

Implementation method two:

In step b1, the controller converts the output voltage feedback signal into a first control signal, and determines the first moment according to the first control signal and the second reference voltage, and determines the second moment according to the first control signal and the third reference voltage.

Wherein, the second reference voltage is different from the third reference voltage. The first instant is delayed by a second time period relative to the instant at which the first control signal crosses the second reference voltage. The second instant is delayed by a first period of time relative to the instant at which the first control signal crosses the third reference voltage.

In a possible implementation manner, before the first moment, the reference voltage used for comparison with the first control signal is the second reference voltage. After the first moment and before the second moment, the reference voltage used for comparison with the first control signal is the third reference voltage. For example, the switching of the reference voltage is controlled by the controller.

In this possible implementation manner, when the first control signal is a rising ramp voltage signal, 0V≤second reference voltage≤first threshold, and third reference voltage>second reference voltage. Alternatively, when the first control signal is a falling ramp voltage signal, the second threshold ≤ the second reference voltage ≤ the power supply voltage, and the third reference voltage < the second reference voltage. For descriptions of the first threshold and the second threshold, reference may be made to the description in Implementation Mode 1.

Fig. 4 is a schematic block diagram of an example of a power conversion device provided by the present application. As shown in FIG. 10 , the power conversion device includes a controller and a power conversion circuit. The controller here can be used to execute the method 100 introduced above.

Exemplarily, the power conversion device may be a product applied in different fields such as consumption, mobile carrier, information and communication technology, and the like. For example, the mobile carrier can be a vehicle, which is a vehicle in a broad sense, and can be a means of transportation (such as commercial vehicles, passenger cars, motorcycles, flying cars, trains, etc.), industrial vehicles (such as: forklifts, trailers, tractors, etc.) etc.), engineering vehicles (such as excavators, bulldozers, cranes, etc.), agricultural equipment (such as lawn mowers, harvesters, etc.), amusement equipment, toy vehicles, etc., the embodiment of the present application does not specifically limit the type of vehicles. For another example, the mobile carrier may be a vehicle such as an airplane or a ship.

Exemplarily, the method 100 introduced above can be executed by a power chip. Optionally, the power chip may be an unpackaged power chip die. Exemplarily, the power chip here can also be replaced by a power packaging module, or a power management unit.

Possible examples of control circuits corresponding to the above-mentioned controllers are given below for the above-mentioned implementation manner 1 and the implementation manner 2 respectively. Specifically, FIGS. 5 to 7 correspond to the first implementation, and FIGS. 8 to 10 correspond to the second implementation.

Fig. 5 shows a schematic block diagram of a control circuit 1 for a power conversion device provided by the present application. As shown in FIG. 5 , the control circuit 1 is connected to the power conversion circuit. The control circuit 1 mainly includes a compensation unit 11 . The compensation unit 11 is configured to receive an output voltage feedback signal of the power conversion circuit. The output end of the compensation unit 11 is connected to the power switch tube of the power conversion circuit, and is used for sending a control signal to the power switch tube. Wherein, the control signal is used to control the power switch to conduct within a constant conduction time, and the period corresponding to the pulse width of the control signal is conduction time #2 of the power switch. The conduction time of the power switch tube includes a first time period Td. Specifically, the second moment #1 corresponding to the falling edge of the control signal is delayed by the first time relative to the end time of the preset conduction time of the power switch tube. period. For example, the first time period here can be understood as the above-mentioned Td1 and Td2. The compensation unit 11 is further configured to obtain a second time period Tc according to the output voltage feedback signal, and the second time period Tc is used to compensate the first time period Td. Specifically, the first moment #1 corresponding to the rising edge of the control signal is delayed by Tc. In other words, the first moment #1 corresponding to the rising edge of the control signal sent by the compensation unit is after the start moment of the preset conduction time, and the difference between the first moment #1 and the start moment of the preset conduction time is The time length of is equal to the second time period Tc.

Thus, T _on = T _ideal + Td - Tc. Wherein, T _on is the on-time #2, and T _ideal is the designed on-time or preset on-time.

In the above solution, by offsetting part or all of the first time period by the second time period, the influence of the first time period on the actual conduction time can be reduced, thereby improving the accuracy of the switching frequency. In a possible implementation manner, the length of the second time period is equal to the length of the first time period, that is, Tc=Td. Therefore, the length of the on-time #2 can be as close as possible to the length of the designed on-time (or preset on-time).

In a possible implementation manner, the compensation unit 11 includes a pre-control unit 111 , a pre-compensation unit 112 and a sequential logic unit 113 . The sequential logic unit involved in the present application may be a logic unit that utilizes a sequential logic circuit to realize a sequentially related logic function, such as a reset-set (set-reset, S-R) flip-flop (latch), a D-type flip-flop, a one-shot circuit wait.

Wherein, the pre-control unit 111 is configured to receive the error signal, send the first pre-control signal to the sequential logic unit 113 , and send the second pre-control signal to the pre-compensation unit 112 . Wherein, the error signal is obtained according to the output voltage feedback signal. For example, the compensation unit 11 further includes an error processing module, which receives an output voltage feedback signal from the power conversion circuit and sends an error signal to the pre-control unit 111 . The first pre-control signal is the control signal before compensation, for example, it can be understood as the PWM signal involved in FIG. 2 .

The pre-compensation unit 112 is configured to receive the second pre-control signal, process the second pre-control signal to obtain the first pre-compensation signal, and send the first pre-compensation signal to the sequential logic unit 113 . Wherein, the time for the pre-compensation unit 112 to process the second pre-control signal is the second time period, and the time corresponding to the rising edge of the first pre-control signal is the same as the start time of the preset conduction time.

Optionally, the second time period Tc includes a first compensation time period Tc1 and a second compensation time period Tc2. The pre-compensation unit 112 includes a first pre-compensation module 1121 and a second pre-compensation module 1122 . The first pre-compensation module 1121 is configured to receive the second pre-control signal, and send the second pre-compensation signal to the second pre-compensation module 1122 after the second pre-control signal crosses the first reference voltage. Wherein, the time between the time when the first pre-compensation module 1121 sends the second pre-compensation signal and the time when the second pre-control signal crosses the first reference signal is the first compensation time period Tc1. The second pre-compensation module 1122 is configured to process the second pre-compensation signal to obtain the first pre-compensation signal, and the time for the second pre-compensation module to process the second pre-compensation signal is the second compensation time period Tc2. Optionally, Td1=Tc1, Td2=Tc2.

Thus, T _on = T _ideal + Td1 + Td2 - Tc1 - Tc2. Wherein, T _on is the on-time #2, and T _ideal is the designed on-time or preset on-time.

The timing logic unit 113 is configured to receive the first pre-control signal, receive the first pre-compensation signal after the second time period, and send a control signal to the power switch tube. The timing logic unit 113 also obtains the time corresponding to the rising edge of the control signal according to the time corresponding to the rising edge of the first pre-control signal and the second time period. The output terminal of the sequential logic unit is connected with the power conversion circuit.

Two possible specific examples of FIG. 5 are given below with reference to FIG. 6 and FIG. 7 respectively. Wherein, FIG. 6 takes the second pre-control signal as an example of a rising ramp signal for illustration, and FIG. 7 takes the second pre-control signal as an example of a falling ramp signal for illustration.

Fig. 6 shows a schematic block diagram of a control circuit 1-1 for a power conversion device provided in the present application and a corresponding timing diagram. As shown in (a) of FIG. 6 , the control circuit 1 - 1 for the power conversion device can be understood as a specific example of the delay compensation unit 1 . Wherein, in the control circuit 1-1 for power conversion equipment, the sequential logic unit 113 in the control circuit 1 for power conversion equipment is described by taking the SR latch as an example, and the control circuit 1 for power conversion equipment The pre-control unit 111 in is illustrated by taking the circuit in the dotted box as an example, and the pre-compensation unit 112 in the control circuit 1 for power conversion equipment is illustrated by taking the T _on comparator #2 and the logic #2 unit as examples. Specifically, the first pre-compensation unit 1121 and the second pre-compensation unit 1122 used in the control circuit 1 of the power conversion device are illustrated by taking the T _on comparator #2 and the logic #2 unit as examples respectively. In addition, the error processing unit used in the control circuit 1 of the power conversion device is described as an error comparator. As shown in (b) in Figure 6, signals such as ERR, PWM _old , T _{on_pulse} , T _{on_REF#1,} and T _{on_RAMP} can refer to the corresponding descriptions in Figure 2 for ERR, PWM, T _{on_pulse} , T _{on_REF} , and T _{on_RAMP} and other signal descriptions.

As shown in (a) in Fig. 6, in the control circuit 1-1 for power conversion equipment, the units or modules except the SR latch, the T _on comparator #2 and the logic #2 unit can all be Refer to the relevant description of the chip circuit controlled by the fixed time pulse shown in FIG. 2 . The following mainly introduces in detail the T _on comparator #2, the logic #2 unit and the SR latch.

T _on comparator #2 and T _on comparator #1 use the same circuit and layout design, so that the two comparators can generate delay times that match each other. The delay time of the T _on comparator #2 is Tc1, the delay time of the T _on comparator #1 is Td1, and Td1=Tc1. Both the positive phase inputs of T _on comparator #2 and T _on comparator #1 input T _{on_RAMP} , the threshold of T _on comparator #2 is different from the threshold of T _on comparator #1, that is, T _on comparator #2 and T _on The voltage at the inverting input of comparator #1 is different. Specifically, the threshold of the T _on comparator #1, that is, the T _{on_REF #1} input to the inverting input terminal is determined according to formula 3. The threshold of the T _on comparator #2, that is, the first reference voltage input to the inverting input terminal (ie, T _{on_REF#2} ) satisfies: 0≦the first reference voltage≦the first threshold (condition 1). In a possible implementation manner, the first threshold here may be less than or equal to T _{on_REF#1} . For example, the first reference voltage may be a voltage less than or equal to T _{on_REF#1} . In another possible implementation manner, the first reference voltage may be a reference voltage close to 0V. Optionally, 0<the first reference voltage≤the first threshold. It can be understood that the T _on comparator #2 may have an offset in actual use, and the first reference voltage > 0V can prevent the T _on comparator #2 from being unable to accurately determine the intersection of T _{on_RAMP} and T _{on_REF #2 due} to the offset. In other words, the first reference voltage>0V can improve the accuracy of the T _on comparator #2 in determining the timing of the crossing of T _{on_RAMP} and T _{on_REF#2} . For example, the first reference voltage may be 0.01V, 0.02V, or 0.015V, etc., or other voltage values satisfying condition 1.

Logic #2 cells use the same circuit and layout design as Logic #1 cells, so that the two logic cells can generate matching delay times. The delay time of the logic #2 unit is Tc2, the delay time of the logic #1 unit is Td2, and Tc2=Td2.

The SR latch receives the reset input (reset input) signal from the logic #1 unit and the set input (set input) signal from the logic #2 unit, and determines the output PWM _new according to the reset input signal and the set input signal time pulse. The timing function table of the SR latch is shown in Table 1. The different input timings of the SR latch Reset input and Setinput determine the output to be 0 or 1. Table 1 is described in detail below. In Table 1, the priority of the reset bar (reset bar, RB) is higher than that of the set bar (set bar, SB). For example, in the second row and the third row in Table 1, if RB is low-bit reset or low potential, or RB input is 0, then the output (output) of the Q terminal of the SR latch is 0. In the fourth line of Table 1, RB is high potential, and SB is low set or low potential, then the Q terminal output of the SR latch is 1. In the fifth line of Table 1, the RB and SB inputs are both high potentials, and the output of the Q terminal maintains the previous state (previous state).

Table 1

RB (Reset Input) SB (Set Input) Q(Output) 0 0 0 0 1 0 1 0 1 1 1 previous state

It can be understood that the SR latch does not only determine the rising edge of PWM _new according to the time pulse input by RB, but determines the rising edge of PWM _new signal by combining the signals input by RB and SB. The signal input by RB is the PWM _old signal output by logic #1 unit. The signal input by SB is the signal output by the logic #2 unit after the precompensation unit 11 including the T _on comparator #2 and the logic #2 unit receives the PWM _old signal. Since the delay time of the T _on comparator #2 and the logic #2 unit is Tc1 and Tc2, the delay time of the signal output by the logic #2 unit compared to the PWM _old signal is Tc1+Tc2. Understandably, the T _on comparator #2 and logic #2 unit determines the rising edge of the PWM _new signal. As shown in (b) of FIG. 6 , the time corresponding to the rising edge of the PWM _new signal is after the crossing time of T _{on_RAMP} and T _{on_REF#2} , and the difference between these two times is Tc1+Tc2.

It can also be understood that the crossing of T _{on_RAMP} and T _{on_REF#2} triggers the falling edge of the PWM _new signal, in other words, the T _on comparator #1 and logic #1 unit determines the falling edge of the PWM _new signal. The processing delay of T _on comparator #1 and logic #1 unit is Td1+Td2.

Therefore, Tc1+Tc2 is used to offset part or all of the time in Td1+Td2, so that the length of T _{on_new} corresponding to PWM _new can be as close as possible to the length of the preset on-time T _ideal . Specifically, by matching the delay times of the T _on comparator #1 and the T _on comparator #2, the influence caused by the delay of the T _on comparator #1 can be eliminated. By matching the delay times of the logic #1 unit and the logic #2 unit, the influence caused by the delay of the logic #1 unit can be eliminated.

In addition, since the logic #2 unit and the logic #1 unit use the same circuit and layout design, the T _on comparator #2 and the T _on comparator #1 use the same circuit and layout design, so that the control for power conversion equipment The compensation effect of the circuit has a high degree of consistency and will not fluctuate with the influence of voltage, temperature or process. Moreover, the delay compensation unit provided by the present application does not introduce additional engineering means (such as adjusting internal parameter values, such as resistance values, capacitance values, or voltage values, etc.) or circuits (such as frequency-locked loops, etc.), design complexity And circuit processing complexity is lower.

FIG. 7 shows a schematic block diagram of a control circuit 1-2 for a power conversion device provided in the present application and a corresponding timing diagram. As shown in (a) of FIG. 7 , the control circuit 1 - 2 for the power conversion device can be understood as a specific example of the delay compensation unit 1 . Among them, in the delay compensation unit 1-2, the sequential logic unit used in the control circuit 1 of the power conversion equipment is illustrated by taking the SR latch as an example, and the pre-control unit used in the control circuit 1 of the power conversion equipment The circuit in the dotted line box in FIG. 7 is taken as an example for illustration, and the precompensation unit used in the control circuit 1 of the power conversion device is described by taking the T _on comparator #2 and the logic #2 unit as examples. Specifically, the first pre-compensation unit and the second pre-compensation unit used in the control circuit 1 of the power conversion device are described by taking the T _on comparator #2 and the logic #2 unit as examples respectively. In addition, the error processing unit used in the control circuit 1 of the power conversion device is described as an error comparator. As shown in (b) in Figure 7, signals such as ERR, PWM _old , T _{on_pulse} , T _{on_REF#1,} and T _{on_RAMP} can refer to the corresponding descriptions in Figure 2 for ERR, PWM, T _{on_pulse} , T _{on_REF} , and T _{on_RAMP} and other signal descriptions.

The difference between the control circuit 1-2 for power conversion equipment and the control circuit 1-1 for power conversion equipment is:

In the control circuit 1-1 for power conversion equipment, T _{on_RAMP} is a rising ramp signal from low potential to high potential, and the voltage value of T _{on_RAMP} =V _C , so the initial value of the voltage of T _{on_RAMP} is 0V. In the control circuit 1-2 for power conversion equipment, T _{on_RAMP} is a falling ramp signal from high potential to low potential, and the voltage value of T _{on_RAMP} =V _VCC −V _C , so the initial value of the voltage of T _{on_RAMP} is V _VCC .

In the control circuit 1-1 for power conversion equipment, the capacitor C and the N-type MOS tube are grounded, and the current source is connected to VCC; in the control circuit 1-2 for the power conversion device, the capacitor C and the N-type MOS tube are connected to VCC, current source ground.

The control circuit 1-2 for the power conversion device modifies the polarity of the T _on comparator #1 compared to the control circuit 1-1 for the power conversion device. In the control circuit 1-2 for power conversion equipment, the inverting input terminal of the T _on comparator #1 is used to receive T _{on_RAMP} , and the voltage of the non-inverting input terminal is T _{on_REF#1} . T _{on_REF#1} can be determined according to Equation 3.

The control circuit 1-2 for the power conversion device modifies the polarity of the T _on comparator #2 compared to the control circuit 1-1 for the power conversion device. In the control circuit 1-2 for power conversion equipment, the inverting input terminal of the T _on comparator #2 is used to receive T _{on_RAMP} , the voltage of the non-inverting input terminal is the first reference voltage T _{on_REF#2} , T _{on_REF#2} satisfies : Second threshold ≤T _{on_REF#2} ≤V _VCC (condition 2). In a possible implementation manner, the second threshold here may be greater than or equal to T _{on_REF#1} . For example, the first reference voltage may be a voltage greater than or equal to T _{on_REF#1} . In another possible implementation, T _{on_REF#2} can be a reference voltage close to V _VCC . Optionally, the second threshold ≦T _{on_REF#2} <V _VCC . It can be understood that the T _on comparator #2 may have an offset in actual use, and the first reference voltage <V _VCC can prevent the T _on comparator #2 from being unable to accurately determine T _{on_RAMP} and T _{on_REF#2} due to the offset The timing of the crossover, in other words, the first reference voltage < V _VCC can improve the accuracy of the T _on comparator #2 in determining the timing of the crossover of T _{on_RAMP} and T _{on_REF #2} . For example, the first reference voltage may be V _VCC -0.01V or V _VCC -0.02V or V _VCC -0.015V, etc., or may be other voltage values satisfying condition 2.

FIG. 8 shows a schematic block diagram of a control circuit 2 for a power conversion device provided by the present application. As shown in FIG. 8, the control circuit 2 is connected to the power conversion circuit. The control circuit 2 mainly includes a control unit 21 . The control unit 21 is configured to receive an output voltage feedback signal of the power conversion circuit. The control unit 21 is connected with the power switch tube of the power conversion circuit, and is also used for sending a control signal to the power switch tube. Wherein, the control signal is used to control the power switch to conduct within a constant conduction time, and the time period corresponding to the pulse width of the control signal is the conduction time of the power switch. The control unit 21 is further configured to determine the first moment #2 corresponding to the rising edge of the control signal and the second moment #2 corresponding to the falling edge of the control signal according to the output voltage feedback signal. Wherein, the length of the first time period generated when the control unit 21 determines the second moment #2 is equal to the length of the second time period generated when the control unit 21 determines the first moment #2. It can be understood that the second time period here can be understood as the processing time required for the control unit 21 to determine the rising edge of the control signal. The first time period here can be understood as the processing time required for the control unit 21 to determine the falling edge of the control signal. Since the processing time of the same control unit 21 is fixed, the first time period=the second time period.

Therefore, T _on =T _ideal . Wherein, T _on is the on-time #2, and T _ideal is the designed on-time or preset on-time. Alternatively, "=" here can be replaced with "≈".

In the above solution, the first moment #2 corresponding to the rising edge of the control signal and the second moment #2 corresponding to the falling edge are determined by the same control unit 21, so that when the first moment #2 and the second moment #2 are determined, the Latency is the same. Therefore, the length of the conduction time can be as close as possible to the length of the designed conduction time (or preset conduction time), so as to avoid the situation that the switching frequency accuracy is reduced due to too long conduction time.

The control unit 21 is configured to obtain a first control signal according to the output voltage feedback signal. Specifically, the control unit 21 is configured to obtain the first moment #2 after the second time period elapses after the first control signal crosses the second reference voltage. Exemplarily, the second time period includes a first delay time period and a second delay time period. The control unit 21 includes a first control module 211 and a second control module 212 . The first control module 211 is configured to obtain a first control signal according to the output voltage feedback signal, and send a second control signal according to the first control signal. Specifically, the moment when the first delay period passes after the moment when the first control signal crosses the second reference voltage is the moment corresponding to the rising edge of the i-th pulse of the second control signal, i≥1 and i is an integer . It can be understood that the first delay time period is the time required for the first control module 211 to determine that the first control signal and the second reference voltage cross. The second control module 212 is configured to receive a second control signal, and send a control signal according to the second control signal. Wherein, the time after the second delay time period after the time corresponding to the rising edge of the i-th pulse of the second control signal is the first time #2. It can be understood that the second delay period is the time required by the first control module 211 to determine the first moment #2.

The control unit 21 is further configured to obtain a second moment #2 after the first time period elapses after the first control signal crosses the third reference voltage. Specifically, the first time period includes a third delay time period and a fourth delay time period. The control unit 21 includes a first control module 211 and a second control module 212 . The first control module 211 is configured to obtain a first control signal according to the output voltage feedback signal, and send a second control signal according to the first control signal. Specifically, the moment when the third delay period passes after the moment when the first control signal crosses the third reference voltage is the moment corresponding to the rising edge of the i+1th pulse of the second control signal, i≥1 and i is an integer. It can be understood that the third delay period is the time required for the first control module 211 to determine that the first control signal and the third reference voltage cross. The second control module 212 is configured to receive a second control signal, and send a control signal according to the second control signal. Wherein, the time after the fourth delay period after the time corresponding to the rising edge of the i+1th pulse of the second control signal is the second time #2. It can be understood that the fourth delay period is the time required by the first control module 211 to determine the second moment #2. Optionally, the time length of the first delay time period is equal to the time length of the third delay time period; the time length of the second delay time period is equal to the time length of the fourth delay time period.

It can be understood that the above-mentioned second reference voltage is different from the above-mentioned third reference voltage. Optionally, the control unit 21 further includes a third control module for providing the first control module with the second reference voltage or the third reference voltage. Specifically, the third control module is used to provide the second reference voltage for the first control module 211 before the first moment #2; the third control module is also used to provide the second reference voltage after the first moment #2 and at the second moment Before #2, provide the first control module 211 with a third reference voltage.

Fig. 9 shows a schematic block diagram of a control circuit 2-1 for a power conversion device provided in the present application and a corresponding timing diagram. As shown in (a) of FIG. 9 , the control circuit 2 - 1 can be understood as a specific example of the control circuit 2 . Wherein, in the control circuit 2-1, the control unit 21 in the control circuit 2 is illustrated by taking the circuit in the dotted box as an example. Specifically, the first control module 211 and the second control module 212 in the control circuit 2 respectively take the T _on comparator #3 and the sequential logic module as examples for illustration. Optionally, in the case that the control circuit 2 includes a third control module, the third control module uses the two transmission gates in the dotted line box as an example for illustration. As shown in (b) in FIG. 9 , for signals such as ERR, PWM _old , and T _{on_RAMP} , please refer to the description of signals such as ERR, PWM, and T _{on_RAMP} in the description corresponding to FIG. 2 . The second control signal involved in the control circuit 2 is illustrated by taking T _{on_pulse} in FIG. 9 as an example. The i-th time pulse of the second control signal is T _{on_pulse#1} , and the i+1-th time pulse of the second control signal For T _{on_pulse#2} . The second reference voltage involved in the control circuit 2 is described by taking T _{on_REF#4} as an example, and the third reference voltage involved in the control circuit 2 is described by taking T _{on_REF#3} as an example.

As shown in (a) in Figure 9, in the control circuit 2-1, the units or modules except the T _on comparator #3, the sequential logic module and the two transmission gates can refer to the fixed The relevant description of the chip circuit controlled by the time pulse. The following mainly introduces in detail the T _on comparator #3, the sequential logic module and the two transmission gates.

The non-inverting input of T _on comparator #3 is input to T _{on_RAMP} , and the inverting input of T _on comparator #3 can be set with multiple different thresholds, or in other words, the inverting input of T _on comparator #3 can be Input multiple different voltages. In (a) of FIG. 9 , the T _on comparator #3 can input two different voltages, that is, T _{on_REF #3} and T _{on_REF #4} as an example for illustration. During the first period, the voltage input to the inverting input terminal of the T _on comparator #3 is T _{on_REF #4} . T _{on_REF#4} satisfies: 0≦T _{on_REF#4} ≦the first threshold (condition 3). For the introduction of T _{on_REF#4} , condition 3 and the first threshold, please refer to the description of T _{on_REF#2} , condition 1 and the first threshold in the control circuit 1-1, the difference is: replace T _{on_REF#2} with T _{on_REF #4} , replace condition 1 with condition 3. The starting moment of the first period may be the moment corresponding to the falling edge of the time pulse of the previous cycle of PWM _new in (b) in FIG. 9 , or after this moment. The end time of the first period is the time corresponding to the rising edge of the time pulse of the current cycle of PWM _new in (b) in FIG. 9 , that is, the first time #2. During the second time period, the voltage input to the inverting input terminal of the T _on comparator #3 is T _{on_REF #3} . T _{on_REF#3} satisfies: second threshold≦T _{on_REF#3} ≦V _VCC (condition 4). For the introduction of T _{on_REF#3} , condition 4 and the second threshold, please refer to the description of T _{on_REF#2} , condition 2 and the second threshold in the control circuit 1-2, the difference is: replace T _{on_REF#2} with T _{on_REF #3} , replace condition 2 with condition 4. The starting moment of the second period is the first moment #2. The end time of the second period is the time corresponding to the falling edge of the time pulse of the current cycle of PWM _new in (b) in FIG. 9 , that is, the second time #2. Taking the T _on comparator #3 using the same circuit and layout design as the T _on comparator in FIG. 2 as an example, the processing delay of the T _on comparator #3 is Td1. In addition, T _{on_REF #3} and T _{on_REF #4} satisfy: T _{on_REF #3} > T _{on_REF #4} (condition 5).

The main function of the sequential logic module is to make a logical judgment on the pulse output by the T _on comparator #3, and determine the first moment #2 and the second moment #2. The processing delay of the sequential logic module is Td3. The logic implementation of the sequential logic module will be described below with reference to FIG. 11 .

In the control circuit 2-1, T _{on_REF#4} and T _{on_REF#3} are provided to the T _on comparator #3 through two transmission gates, so as to switch different reference voltages at the rising and falling edges of PWM _new . Exemplarily, the two transmission gates are triggered by a sequential logic module to switch between different reference voltages. For example, the timing logic module triggers the transmission gate for providing T _{on_REF#4} to be turned on at the rising edge of PWM _new , and for example, the timing logic module triggers the transmission gate for providing T _{on_REF#3} to be turned on at the falling edge of PWM _new . In the circuit in the dotted line box in (a) of FIG. 9 , the inverter can ensure that at most one of the two transmission gates is turned on at the same time.

In addition, in (a) of FIG. 9 , the logic #1 unit is not connected to the power switch tube, and the logic #1 unit is connected to the sequential logic module. Logic #1 unit outputs PWM _old signal and PWM _RB signal. Among them, the PWM _old signal is used to control the start and end of the time pulse of the T _{on_RAMP} signal. Specifically, the logic #1 unit processes the error signal output by the error comparator to determine the start of the time pulse of the T _{on_RAMP} signal, that is, the time corresponding to the rising edge of the PWM _old signal is the time when the T _{on_RAMP} signal starts to rise. The sequential logic module sends the T _{on_Reset} signal to the logic #1 unit, and the logic #1 unit determines the falling edge of the PWM _old signal according to the T _{on_Reset} signal, thereby determining the end time of the T _{on_RAMP} signal. The logic #1 unit sends the PWM _RB to the sequential logic module, and the PWM _RB can be the same signal as the PWM _old , or the PWM _RB can be a signal obtained by the PWM _old after error processing. When the PWM _old signal is at low potential, the PWM _RB signal is used to reset the sequential logic module.

FIG. 10 shows a schematic block diagram of the control circuit 2-2 provided in the present application and a corresponding timing diagram. As shown in (a) of FIG. 10 , the control circuit 2 - 2 can be understood as a specific example of the control circuit 2 . Wherein, in the control circuit 2-2, the control unit 21 in the control circuit 2 is described by taking the circuit in the dotted box as an example. Specifically, the first control module 211 and the second control module 212 in the control circuit 2 respectively take the T _on comparator #3 and the sequential logic module as examples for illustration. Optionally, in the case that the control circuit 2 includes a third control module, the third control module uses the two transmission gates in the dotted line box as an example for illustration. As shown in (b) in FIG. 10 , for signals such as ERR, PWM _old , and T _{on_RAMP} , please refer to the description of signals such as ERR, PWM, and T _{on_RAMP} in the description corresponding to FIG. 2 . The second control signal involved in the control circuit 2 is illustrated by taking T _{on_pulse} in FIG. 9 as an example. The i-th time pulse of the second control signal is T _{on_pulse#1} , and the i+1-th time pulse of the second control signal For T _{on_pulse#2} . The second reference voltage involved in the control circuit 2 is described by taking T _{on_REF#4} as an example, and the third reference voltage involved in the control circuit 2 is described by taking T _{on_REF#3} as an example.

The difference between the control circuit 2-2 and the control circuit 1-1 is:

In the control circuit 2-1, T _{on_RAMP} is a rising ramp signal from low potential to high potential, and the voltage value of T _{on_RAMP} =V _C , so the initial value of the voltage of T _{on_RAMP} is 0V. In the control circuit 2-2, T _{on_RAMP} is a falling ramp signal from high potential to low potential, and the voltage value of T _{on_RAMP} =V _VCC −V _C , so the initial value of the voltage of T _{on_RAMP} is V _VCC .

In the control circuit 2-1, the capacitor C and the N-type MOS tube are connected to the ground, and the current source is connected to VCC; in the control circuit 2-2, the capacitor C and the N-type MOS tube are connected to VCC, and the current source is connected to the ground.

Control circuit 2-2 modifies the polarity of T _on comparator #3 compared to control circuit 2-1. In the control circuit 2-2, the inverting input terminal of the T _on comparator #3 is used to receive T _{on_RAMP} , and the voltage of the non-inverting input terminal is T _{on_REF#3} or T _{on_REF#4} . T _{on_REF#3} in the control circuit 2-2 satisfies condition 4, T _{on_REF#4} satisfies condition 3, T _{on_REF#3} and T _{on_REF#4} satisfy: T _{on_REF#3} <T _{on_REF#4} (condition 6).

FIG. 11 shows a schematic block diagram and a corresponding timing diagram of an example of the control circuit 2 - 1 and the sequential logic module in the control circuit 2 - 2 provided in the present application.

As shown in (a) of FIG. 11 , the sequential logic module may include three D flip-flops and one SR latch. The two input terminals of the sequential logic module respectively receive the PWM _RB signal and the T _{on_pulse} signal, and the two output terminals of the sequential logic module respectively output the PWM _new signal and the T _{on_Reset} signal. For the convenience of description, the three D flip-flops from left to right are called D flip-flop #1, D flip-flop #2 and D flip-flop #3 respectively. For the three D flip-flops, the input V of the data (data, D) terminal is a logic high potential, that is, V=1, which may be, for example, the power supply voltage on the chip.

为低电位，Q1B＝0。D触发器#2的CP输入端输入T_{on_pulse}信号，在T_{on_pulse#1}的上升沿对应的时刻，由于D触发器#2还未接收到来自D触发器#1的Q1信号，因此D触发器#2的D端仍为低电位，即输入为0；从而D触发器#2的输出Q也为逻辑上的低电位，Q2＝0，Q2B＝1。D触发器#3的CP输入端输入T_{on_pulse}信号经反相器处理之后的信号，在T_{on_pulse#1}的上升沿对应的时刻，D触发器#3的Q端输出为逻辑上的低电位，Q3＝0。或非门的输入为Q1B、Q2和Q3，输出为Set信号。由上可知，在T_{on_pulse#1}的上升沿对应的时刻，Q1B＝0，Q2＝0，Q3＝0，从而或非门输出的Set信号为逻辑上的高电平。与门的输入为Q2和PWM_RB，输出为Reset信号。由上可知，在T_{on_pulse#1}的上升沿对应的时刻，Q2＝0，从而Reset信号为逻辑上的低电平。如图11中的(b)所示，T_{on_pulse#1}的上升沿与Set信号的上升沿对应同一时刻。对于S-R锁存器，S端输入Set信号，R端输入Reset信号，Q端输出PWM_new信号。Set信号为高电平，Reset信号为低电平，PWM_new信号为高电平。如图11中的(b)所示，PWM_new信号的上升沿对应的时刻在T_{on_pulse#1}的上升沿对应的时刻之间相差Td3，Td3可以理解为S-R锁存器的处理时延。The time pulse (clock pulse, CP) input terminal of D flip-flop #1 inputs the T _{on_pulse} signal, and at the moment corresponding to the rising edge of T _{on_pulse #1} , the output Q of D flip-flop #1 is also a logically high potential, Q1 = 1, the output of D flip-flop #1

It is low potential, Q1B=0. The CP input terminal of D flip-flop #2 inputs the T _{on_pulse} signal. At the moment corresponding to the rising edge of T _{on_pulse #1} , since D flip-flop #2 has not received the Q1 signal from D flip-flop #1, the D flip-flop The D terminal of #2 is still at a low potential, that is, the input is 0; thus the output Q of the D flip-flop #2 is also at a logical low potential, Q2=0, Q2B=1. The CP input terminal of D flip-flop #3 inputs the T _{on_pulse} signal processed by the inverter. At the moment corresponding to the rising edge of T _{on_pulse #1} , the Q terminal output of D flip-flop #3 is a logical low potential. Q3=0. The input of the NOR gate is Q1B, Q2 and Q3, and the output is the Set signal. It can be known from the above that at the moment corresponding to the rising edge of T _{on_pulse#1} , Q1B=0, Q2=0, Q3=0, so the Set signal output by the NOR gate is at a logic high level. The input of the AND gate is Q2 and PWM _RB , and the output is the Reset signal. It can be known from the above that at the moment corresponding to the rising edge of T _{on_pulse#1} , Q2=0, so the Reset signal is at a logical low level. As shown in (b) of FIG. 11 , the rising edge of _{Ton_pulse#1} corresponds to the same moment as the rising edge of the Set signal. For the SR latch, the S terminal inputs the Set signal, the R terminal inputs the Reset signal, and the Q terminal outputs the PWM _new signal. The Set signal is high level, the Reset signal is low level, and the PWM _new signal is high level. As shown in (b) in Figure 11, the time corresponding to the rising edge of the PWM _new signal differs by Td3 between the times corresponding to the rising edge of T _{on_pulse#1} , and Td3 can be understood as the processing delay of the SR latch.

At the moment corresponding to the rising edge of T _{on_pulse#2} , D flip-flop #2 has received Q1, that is, the input of terminal D is high level, and the output of Q2 is also high level, Q2=1. The input of the NOR gate is Q1B, Q2 and Q3, and the output is the Set signal. In the case of Q2=1, the Set signal is at low level. The input of the AND gate is Q2 and PWM _RB , and the output is the Reset signal. Since PWM _RB is at high level at this time, the Reset signal is at high level. For the SR latch, the S terminal inputs the Set signal, the R terminal inputs the Reset signal, and the Q terminal outputs the PWM _new signal. The Set signal is low level, the Reset signal is high level, and the PWM _new signal is low level. As shown in (b) in Figure 11, the time corresponding to the falling edge of the PWM _new signal differs by Td3 from the time corresponding to the rising edge of T _{on_pulse#2} , and Td3 can be understood as the processing delay of the SR latch.

The output terminal of the AND gate also outputs a T _{on_Reset} signal, and the T _{on_Reset} signal is used to trigger the falling edge of the PWM _old signal. The PW _RB signal obtained from the PWM _old signal is used to reset the 3 D flip-flops.

It should be noted that the control circuit 2-1 and the sequential logic modules in the control circuit 2-2 can also be implemented by other design methods to achieve similar functions, which is not limited in this application.

Claims (17)

1. A power conversion device, characterized in that the power conversion device includes a controller and a power conversion circuit, and the controller is connected to a power switch tube of the power conversion circuit; The controller is configured to receive an output voltage feedback signal from the power conversion circuit; The controller is further configured to send a control signal to the power switch tube, the control signal is used to control the power switch tube to be turned on periodically according to a constant time period, and the rise of one pulse of the control signal The time period between the first moment corresponding to the edge and the second moment corresponding to the falling edge of the pulse is the time when the power switch tube is actually turned on in one cycle; Wherein, the second moment is after the end moment of the preset conduction time corresponding to the pulse, the first moment is after the start moment of the preset conduction time, and the preset conduction time is based on The theoretical turn-on time of the power switch tube within one cycle is determined by the circuit parameters of the controller and the power conversion circuit. 2. The power conversion device according to claim 1, wherein the time period between the second moment and the end moment is a first time period, and the period between the first moment and the start moment The time period is the second time period, and the difference between the length of the first time period and the length of the second time period is ≤ a preset value. 3. The power conversion device according to claim 1 or 2, characterized in that, The controller is further configured to convert the output voltage feedback signal into an error signal, and convert the error signal into a first pre-control signal and a second pre-control signal, and the rising edge of the first pre-control signal corresponds to The time is the same as the start time of the preset conduction time; The controller is further configured to convert the second pre-control signal into a first pre-compensation signal, wherein the time for converting the second pre-control signal into the first pre-compensation signal is the second period; The controller is further configured to determine the first moment based on the first pre-control signal and the first pre-compensation signal. 4. The power conversion device according to claim 3, wherein the second time period comprises a first compensation time period and a second compensation time period, The control unit is specifically configured to determine a second pre-compensation signal based on the second pre-control signal and the first reference voltage, wherein the time corresponding to the rising edge of the second pre-compensation signal is the same as the second pre-compensation signal. The time between the time when the control signal and the first reference signal cross is the first compensation time period; The control unit is specifically configured to convert the second precompensation signal into the first precompensation signal, and the time for converting the second precompensation signal into the first precompensation signal is the second Compensation period. 5. The power conversion device according to claim 4, characterized in that, When the second pre-control signal is a rising ramp voltage signal, 0V≤the first reference voltage≤the first threshold; or, When the second pre-control signal is a falling ramp voltage signal, the second threshold ≤ the first reference voltage ≤ power supply voltage. 6. The power conversion device according to claim 1 or 2, characterized in that, The controller is configured to convert the output voltage feedback signal into a first control signal, determine the first moment according to the first control signal and a second reference voltage, and determine the first moment according to the first control signal and A third reference voltage determines the second instant; Wherein, the second reference voltage is different from the third reference voltage, and the first moment is delayed by the second time period relative to the moment when the first control signal crosses the second reference voltage, so The second moment is delayed by the first period of time relative to the moment when the first control signal and the third reference voltage cross. 7. The power conversion device of claim 6, wherein Before the first moment, the reference voltage used for comparison with the first control signal is the second reference voltage; After the first moment and before the second moment, the reference voltage used for comparison with the first control signal is the third reference voltage. 8. The power conversion device according to claim 6 or 7, characterized in that, When the first control signal is a rising ramp voltage signal, 0V≤the second reference voltage≤the first threshold, and the third reference voltage>the second reference voltage; or, When the first control signal is a falling ramp voltage signal, the second threshold value≤the second reference voltage≤power supply voltage, and the third reference voltage<the second reference voltage. 9. A method for power conversion, applied to a controller in a power conversion device, the power conversion device further comprising a power conversion circuit, the controller is connected to a power switch tube of the power conversion circuit, characterized in that, include: receiving an output voltage feedback signal of the power conversion circuit; Sending a control signal to the power switch tube, the control signal is used to control the power switch tube to be turned on periodically according to a constant time period, the first moment corresponding to the rising edge of a pulse of the control signal, and The time period between the second moment corresponding to the falling edge of the pulse is the time when the power switch tube is actually turned on in one cycle; Wherein, the second moment is after the end moment of the preset conduction time corresponding to the pulse, the first moment is after the start moment of the preset conduction time, and the preset conduction time is based on The theoretical turn-on time of the power switch tube within one cycle is determined by the circuit parameters of the controller and the power conversion circuit. 10. The method according to claim 9, wherein the time period between the second moment and the end moment is a first time period, and the time period between the first moment and the start moment is The segment is a second time segment, and the difference between the length of the first time segment and the length of the second time segment is ≤ a preset value. 11. The method according to claim 9 or 10, further comprising: Converting the output voltage feedback signal into an error signal, and converting the error signal into a first pre-control signal and a second pre-control signal, the period corresponding to the pulse width of the first pre-control signal is equal to that of the power switch tube preset on-time; converting the second pre-control signal into a first pre-compensation signal, wherein the time for converting the second pre-control signal into the first pre-compensation signal is the second time period; The control signal is determined based on the first pre-control signal and the first pre-compensation signal. 12. The method according to claim 11, wherein the second time period comprises a first compensation time period and a second compensation time period, the method further comprising: The second pre-compensation signal is determined based on the second pre-control signal and the first reference voltage, wherein the moment corresponding to the rising edge of the second pre-compensation signal is the same as the second pre-control signal and the first reference The time between signal crossing moments is the first compensation time period; The second pre-compensation signal is converted into the first pre-compensation signal, and the time for converting the second pre-compensation signal into the first pre-compensation signal is the second compensation time period. 13. The method of claim 12, wherein, When the second pre-control signal is a rising ramp voltage signal, 0V≤the first reference voltage≤the first threshold; or, When the second pre-control signal is a falling ramp voltage signal, the second threshold ≤ the first reference voltage ≤ power supply voltage. 14. The method according to claim 9 or 10, further comprising: converting the output voltage feedback signal into a first control signal, determining the first moment according to the first control signal and a second reference voltage, and determining the second moment; Wherein, the second reference voltage is different from the third reference voltage, and the first moment is delayed by the second time period relative to the moment when the first control signal crosses the second reference voltage, so The second moment is delayed by the first period of time relative to the moment when the first control signal crosses the third reference voltage. 15. The method of claim 14, wherein, Before the first moment, the reference voltage used for comparison with the first control signal is the second reference voltage; After the first moment and before the second moment, the reference voltage used for comparison with the first control signal is the third reference voltage. 16. The method of claim 14 or 15, wherein When the first control signal is a rising ramp voltage signal, 0V≤the second reference voltage≤the first threshold, and the third reference voltage>the second reference voltage; or, When the first control signal is a falling ramp voltage signal, the second threshold value≤the second reference voltage≤power supply voltage, and the third reference voltage<the second reference voltage. 17. A power chip, applied to power conversion equipment, the power conversion equipment also includes a power conversion circuit composed of power switch tubes, characterized in that it includes: The power chip is configured to receive an output voltage feedback signal of the power conversion circuit; The power chip is also used to send a turn-on time control signal to the power switch tube, the turn-on time control signal is used to control the power switch tube to be turned on within a constant turn-on time, and the turn-on time The period corresponding to the pulse width of the time control signal is the conduction time of the power switch tube, Wherein, the first moment corresponding to the falling edge of the on-time control signal is delayed by a first time period relative to the end moment of the designed on-time of the power switch tube, and the rising edge of the on-time control signal corresponds to At the second moment, a second time period is delayed relative to the start time of the designed on-time of the power switch tube, and the second time period is used to compensate for the first time period.

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