CN116264054A

CN116264054A - electronic device

Info

Publication number: CN116264054A
Application number: CN202211024334.3A
Authority: CN
Inventors: 刘勇志; 曾名骏; 郭拱辰; 陈联祥; 陈柏勋
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2021-12-13
Filing date: 2022-08-24
Publication date: 2023-06-16

Abstract

The present disclosure provides an electronic device. The electronic device includes a detection circuit. The detection circuit comprises a programming detection circuit, a light-emitting detection circuit and a judging circuit. The programming detection circuit receives a scanning signal, a reset signal and a light-emitting enabling signal of a driving circuit for the pixel unit and provides a first detection signal in a first stage according to the scanning signal, the reset signal and the light-emitting enabling signal. The light emitting detection circuit receives the scanning signal, the reset signal and the light emitting enabling signal and provides a second detection signal in a second stage according to the scanning signal, the reset signal and the light emitting enabling signal. The judging circuit judges whether to output the light-emitting enabling signal to the driving circuit according to the first detection signal and the second detection signal.

Description

Electronic device

Technical Field

The present disclosure relates to electronic devices, and more particularly, to an electronic device capable of detecting signals.

Background

Generally, an existing device (e.g., a display apparatus) receives at least one signal and operates to provide a desired function corresponding to the at least one signal. However, when an abnormality occurs in waveform or timing among the at least one signal, the device may malfunction and fail to provide a desired function. Therefore, in order to reduce the malfunction of the device, the at least one signal must be detected in real time.

Disclosure of Invention

The present disclosure is directed to an electronic device capable of detecting a signal.

According to an embodiment of the disclosure, an electronic device includes a detection circuit, wherein the detection circuit includes a program detection circuit, a light emission detection circuit, and a determination circuit. The programming detection circuit receives a scanning signal, a reset signal and a light-emitting enabling signal for the driving circuit and provides a first detection signal in a first stage according to the scanning signal, the reset signal and the light-emitting enabling signal. The light emitting detection circuit receives the scanning signal, the reset signal and the light emitting enabling signal and provides a second detection signal in a second stage according to the scanning signal, the reset signal and the light emitting enabling signal. The judging circuit is coupled to the programming detecting circuit and the light emitting detecting circuit. The judging circuit judges whether to output the light-emitting enabling signal to the driving circuit according to the first detection signal and the second detection signal.

According to an embodiment of the disclosure, an electronic device includes a detection circuit, wherein the detection circuit includes a driving detection circuit, a determination circuit, and a correction circuit. The driving detection circuit receives the scanning signal and the light-emitting enabling signal for the driving circuit and provides a driving detection signal according to the scanning signal and the light-emitting enabling signal. The judging circuit is coupled to the driving detecting circuit. The judging circuit judges whether to output the scanning signal and the light-emitting enabling signal to the next-stage driving circuit according to the driving detection signal. The correction circuit is coupled to the judging circuit. The correction circuit corrects the level of the output of the judgment circuit according to the scanning signal and the light-emitting enabling signal.

Based on the above, the detection circuit detects the plurality of signals to provide at least one detection signal, and determines whether to output the signals to the driving circuit according to the at least one detection signal. In this way, the detection circuit of the present disclosure can determine whether the plurality of signals are abnormal according to the at least one detection signal, and stop outputting the plurality of signals to the driving circuit accordingly.

Drawings

FIG. 1 is a schematic diagram of an electronic device according to a first embodiment of the present invention;

FIG. 2A is a timing diagram of a normal signal according to an embodiment of the invention;

FIGS. 2B-2D are timing diagrams of abnormal signals according to an embodiment of the invention;

FIG. 3 is a first circuit schematic of the detection circuit according to the first embodiment;

fig. 4 is a second circuit schematic of the detection circuit according to the first embodiment;

fig. 5 is a third circuit schematic of the detection circuit according to the first embodiment;

FIG. 6 is a schematic diagram of an electronic device according to a second embodiment of the present invention;

fig. 7 is a first circuit schematic of the detection circuit according to the second embodiment;

fig. 8 is a second circuit schematic of the detection circuit according to the second embodiment;

Fig. 9 is a third circuit schematic of the detection circuit according to the second embodiment;

fig. 10 is a schematic diagram of an electronic device according to a third embodiment of the invention.

Description of the reference numerals

10. 30, 40: electronic device

100. 200, 200', 200", 300, 400', 400": detection circuit

110. 210: programming detection circuit

120. 220: luminescence detection circuit

130. 230, 230', 230", 320, 420', 420": judging circuit

231. 421: voltage stabilizing circuit

232: pull-up circuit

233: transmission circuit

234. 234', 234", 424', 424": pull-down circuit

310. 410: drive detection circuit

330. 430: correction circuit

440: reset circuit

C1, C2, CC: capacitor with a capacitor body

DC: driving circuit

DCN: next stage driving circuit

EM [ n ]: luminescence enable signal

EM [ n+1]: next-stage light-emitting enable signal

LE: light emitting assembly

NDC: control node

NDB, NDB': voltage stabilizing node

P1: first stage

P2: second stage

PU: pixel unit

R1 and R2: resistor

RST [ n ]: reset signal

SD1: first detection signal

SD2: second detection signal

SD3: drive detection signal

SN [ n ]: scanning signal

SN [ n+1]: next stage scanning signal

T1, T1': first detection transistor

T2, T2': second detection transistor

T3: third detection transistor

T3 'to T13', T6 to T11: transistor with a high-voltage power supply

T4: fourth detection transistor

T5: fifth detection transistor

TD: driving transistor

TEM: enable transistor

TR: reset transistor

TS: scanning transistor

VGH: high voltage

VGL: low voltage

VRST: reset bias voltage

Detailed Description

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings as described below. It should be noted that for purposes of clarity and ease of understanding by the reader, the various figures of the present disclosure illustrate a portion of an electronic device, and certain components in the various figures may not be drawn to scale. Furthermore, the number and size of each device shown in the drawings is illustrative only and is not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and following claims to refer to particular components. As will be appreciated by those skilled in the art, electronic device manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "comprises," "comprising," and "having" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to … …," and thus, when the terms "including," "comprising," and/or "having" are used in the description of the present disclosure, will indicate the presence of corresponding features, regions, steps, operations, and/or components, but are not limited to the presence of one or more corresponding features, regions, steps, operations, and/or components.

It will be understood that when an element is referred to as being "coupled," "connected," or "turned on" to another element, it can be directly connected to the other element and electrical connection can be directly established, or intervening elements may be present between the elements for intervening electrical connection (indirect electrical connection). In contrast, when a component is referred to as being "directly coupled," "directly conducting," or "directly connected" to another component, there are no intervening components present.

Although terms such as first, second, third, etc. may be used to describe different constituent components, such constituent components are not limited by these terms. The terminology is used only to distinguish the constituent components in the specification from other constituent components. The claims may not use the same term but rather the terms first, second, third, etc. may be used with respect to the order in which the components are required. Thus, in the following description, the first component may be the second component in the claims.

The electronic device of the present disclosure may include, but is not limited to, an antenna, a display, a lighting, a sensing, a touch, a stitching, a packaging, other suitable functions, or a combination thereof. The electronic device includes a flexible electronic device, but is not limited to the above. The electronic device may include, for example, a liquid crystal (liquid crystal), a light emitting diode (light emitting diode, LED), a Quantum Dot (QD), fluorescent (fluorescent), phosphorescent (phosphorescent), an encapsulation component, other suitable materials, or combinations thereof. The electronic device may include, for example, an electronic component, wherein the electronic component may include a passive component and an active component, such as, but not limited to, a capacitor (capacitor), a resistor (resistor), an inductor (inductor), a diode (diode), a transistor, a circuit board, a chip (chip), a die (die), an integrated circuit (integrated circuits, IC), a package component, or a combination of the above components, or other suitable electronic components. The diode may include, but is not limited to, a light emitting diode, a photodiode, or an antenna diode. The light emitting diode may include, for example, an organic light emitting diode (organic light emitting diode, OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot LED (which may include QLED, QDLED), or other suitable materials, or combinations thereof, but is not limited thereto. The package components may include, but are not limited to, circuit redistribution layers (redistribution layer), wafer level packages (WLP, wafer level packaging), panel level packages (PLP, panel level packaging), and the like. The sensing device may include a camera or an infrared sensor (ir sensor) or a fingerprint sensor, but the disclosure is not limited thereto. In some embodiments, the sensing device may also include, but is not limited to, a flash, an Infrared (IR) light source, other sensors, electronic components, or a combination of the above. The shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shape. The electronic device may have a driving system, a control system, a light source system …, and other peripheral systems to support the display device, the antenna device, or the splicing device, but the disclosure is not limited thereto. In this disclosure, an embodiment uses "pixel" or "pixel cell" as a means for describing a particular region including at least one functional circuit for at least one particular function. The area of a "pixel" depends on the unit used to provide a particular function, adjacent pixels may share the same portion or wire, but may also include a particular portion of themselves therein. For example, adjacent pixels may share the same scan line or the same data line, but the pixels may also have their own transistors or capacitances.

It should be noted that features in the different embodiments described below may be substituted, rearranged, or mixed with one another to form another embodiment without departing from the spirit of the present disclosure.

Referring to fig. 1, fig. 1 is a schematic diagram of an electronic device according to a first embodiment of the invention. In the present embodiment, the electronic device 10 includes a pixel circuit PU and a detection circuit 100. The pixel circuit PU includes a driving circuit DC and a light emitting element LE. The detection circuit 100 includes a program detection circuit 110, a light emission detection circuit 120, and a determination circuit 130. The program detection circuit 110 receives a scan signal SN [ n ], a reset signal RST [ n ], and a light emission enable signal EM [ n ] for the driving circuit DC. The program detecting circuit 110 provides a first detecting signal SD1 in a first stage according to the scan signal SN [ n ], the reset signal RST [ n ] and the light emitting enable signal EM [ n ]. The light emission detection circuit 120 receives a light emission enable signal EM [ n ] from the scan signal SN [ n ], the reset signal RST [ n ]. The light emitting detection circuit 120 provides a second detection signal SD2 in the second stage according to the scan signal SN [ n ], the reset signal RST [ n ] and the light emitting enable signal EM [ n ].

In the present embodiment, the determining circuit 130 is coupled to the program detecting circuit 110 and the light emitting detecting circuit 120. The judging circuit 130 judges whether to output the light emission enabling signal EM n to the driving circuit DC according to the first detection signal SD1 and the second detection signal SD2.

The judging circuit 130 judges whether the first stage and the second stage are abnormal according to the first detection signal SD1 and the second detection signal SD 2. When it is determined that at least one of the first stage and the second stage is abnormal, the determination circuit 130 stops outputting the light emission enabling signal to the driving circuit. On the other hand, when it is determined that no abnormality has occurred in both the first stage and the second stage, the determination circuit 130 outputs a light emission enable signal to the driving circuit. For example, when the first detection signal SD1 indicates an abnormality, the judging circuit 130 can know that one of the scan signal SN [ n ], the reset signal RST [ n ] and the light emitting enable signal EM [ n ] is abnormal in the first stage. Therefore, the determination circuit 130 stops outputting the light emission enable signal EM [ n ] to the driving circuit DC. When the second detection signal SD2 indicates an abnormality, the judging circuit 130 can know that one of the scan signal SN [ n ], the reset signal RST [ n ] and the light emitting enable signal EM [ n ] is abnormal in the second stage. Therefore, the determination circuit 130 stops outputting the light emission enable signal EM [ n ] to the driving circuit DC. When no abnormality is indicated by the first detection signal SD1 and the second detection signal SD2, the determining circuit 130 may determine that no abnormality occurs in the scan signal SN [ n ], the reset signal RST [ n ] and the light emitting enable signal EM [ n ]. Therefore, the judging circuit 130 outputs the light emission enabling signal EM [ n ] to the driving circuit DC.

It should be noted that the detection circuit 100 detects the scan signal SN [ n ], the reset signal RST [ n ] and the light emission enabling signal EM [ n ] to provide the first detection signal SD1 and the second detection signal SD2, and determines whether to output the light emission enabling signal EM [ n ] to the driving circuit DC according to the first detection signal SD1 and the second detection signal SD 2. In this way, the detection circuit 100 can determine whether the scan signal SN [ n ], the reset signal RST [ n ] and the light emission enable signal EM [ n ] are abnormal according to the first detection signal SD1 and the second detection signal SD2, and stop outputting the light emission enable signal EM [ n ] to the driving circuit DC accordingly.

In the present embodiment, the detection circuit 100 can be applied to a display device, for example. The driving circuit DC is, for example, a pixel driving circuit disposed in the pixel unit PU (the disclosure is not limited thereto). In the present embodiment, the driving circuit DC can drive the light emitting element LE disposed in the pixel unit PU by using the scan signal SN [ n ], the reset signal RST [ n ] and the light emitting enable signal EM [ n ]. The light emitting assembly LE may be at least one light emitting diode or other suitable electronic assembly. Taking the present embodiment as an example, the driving circuit DC includes a scan transistor TS, a reset transistor TR, a driving transistor TD, an enable transistor TEM, and a capacitor CC. The first terminal of the scan transistor TS receives the data signal VD. The second terminal of the scan transistor TS is coupled to the control node NDC. The control terminal of the scan transistor TS receives a scan signal SN [ n ]. A first terminal of the reset transistor TR is coupled to the control node NDC. A second terminal of the reset transistor TR is coupled to the reset bias VRST. The control terminal of the reset transistor TR receives a reset signal RST n. The reset signal RST [ n ] may be a previous scan signal (e.g., scan signal SN [ n-1], but the disclosure is not limited thereto). The first terminal of the driving transistor TD receives a high reference voltage ARVDD. The control terminal of the driving transistor TD is coupled to the control node NDC. The first terminal of the enable transistor TEM is coupled to the second terminal of the driving transistor TD. The control terminal of the enable transistor TEM receives the light emission enable signal EM n through the judging circuit 130. The first end of the light emitting element LE is coupled to the second end of the enable transistor TEM. A second terminal of the light emitting element LE is coupled to a second terminal of the enable transistor TEM for receiving a low reference voltage ARVSS. The capacitor CC is coupled between the first terminal of the driving transistor TD and the control terminal of the driving transistor TD. The scan transistor TS, the reset transistor TR, the driving transistor TD and the enabling transistor TEM are respectively exemplified by P-type transistors in the present embodiment, but the disclosure is not limited thereto. Therefore, in the present embodiment, the driving circuit DC operates based on the negative pulses of the scan signal SN [ n ], the reset signal RST [ n ] and the light-emitting enable signal EM [ n ]. The driving circuit DC of the present embodiment is implemented with a 4-transistor and 1-capacitor (4T 1C) structure, for example, but the disclosure is not limited thereto. Circuits capable of driving components based on a scan signal SN [ n ], a reset signal RST [ n ] and a light emission enable signal EM [ n ] are all within the scope of the driving circuit DC of the present disclosure.

In the present embodiment, in an example in which the detection circuit 100 is applicable to a display device, for example, the first stage is a data input stage for the driving circuit DC. Therefore, the determination circuit 130 can determine whether or not the scan signal SN [ n ], the reset signal RST [ n ], and the light emission enable signal EM [ n ] are abnormal in the data input stage using the first detection signal SD1. Further, the second stage is a light emitting stage for the driving circuit DC. Therefore, the determination circuit 130 can determine whether the scan signal SN [ n ], the reset signal RST [ n ], and the light emission enable signal EM [ n ] are abnormal in the light emission stage by using the second detection signal SD 2.

Referring to fig. 1 and fig. 2A, fig. 2A is a timing chart of normal signals according to an embodiment of the invention. Fig. 2A shows a normal timing diagram of the scan signal SN [ n ], the reset signal RST [ n ], and the light emission enable signal EM [ n ]. In the first phase P1, the light emission enable signal EM [ n ] is at a high level. The reset signal RST [ n ] has a negative pulse. The scan signal SN [ n ] also has a negative pulse. The timing of the negative pulse of the reset signal RST [ n ] is ahead of the timing of the negative pulse of the scan signal SN [ n ]. The negative pulse of the reset signal RST [ n ] and the negative pulse of the scan signal SN [ n ] do not overlap each other in time sequence. Therefore, the program detecting circuit 110 provides the first detecting signal SD1 with the first level (e.g. high level) according to the above-mentioned timing in the first stage P1.

In the second phase P2, the light emission enable signal EM [ n ] is at a low level. The reset signal RST [ n ] and the scan signal SN [ n ] are respectively at high level. Therefore, the light-emitting detection circuit 120 provides the second detection signal SD2 with the first level according to the above-mentioned timing in the second stage P2.

The judging circuit 130 outputs the light emitting enable signal EM n to the driving circuit DC according to the first detection signal SD1 and the second detection signal SD2 having the first level.

Fig. 2B to 2D are timing diagrams of abnormal signals according to an embodiment of the invention. Referring to fig. 1 and fig. 2B, fig. 2B shows an abnormal timing diagram of the scan signal SN [ n ] in the first stage P1. In the first phase P1, the scan signal SN [ n ] does not have a negative pulse. Therefore, the program detecting circuit 110 provides the first detecting signal SD1 with the second level (e.g. low level) according to the above-mentioned timing in the first stage P1. The judging circuit 130 stops outputting the light emitting enable signal EM n to the driving circuit DC according to the first detection signal SD1 having the second level.

Referring to fig. 1 and fig. 2C, fig. 2C shows an abnormal timing diagram of the light emitting enable signal EM n in the first stage P1. In the first phase P1, when the light emitting enable signal EM [ n ] is at the low level, the programming detection circuit 110 also provides the first detection signal SD1 at the second level.

Referring to fig. 1 and fig. 2D, fig. 2D shows an abnormal timing diagram of the scan signal SN [ n ] in the second stage P2. In the second phase P2, the scan signal SN [ n ] and the reset signal RST [ n ] have at least one negative pulse. Therefore, the light emitting detection circuit 120 provides the second detection signal SD2 with the second level according to the above-mentioned timing in the second stage P2. The judging circuit 130 stops outputting the light emitting enable signal EM n to the driving circuit DC according to the second detection signal SD2 having the second level. In some embodiments, in the second phase P2, when the light emitting enable signal EM [ n ] is at the high level, the programming detection circuit 110 also provides the second detection signal SD2 with the second level.

Referring to fig. 3, fig. 3 is a first circuit schematic of the detection circuit according to the first embodiment. In the present embodiment, the detection circuit 200 includes a program detection circuit 210, a light emission detection circuit 220, and a determination circuit 230. The program detection circuit 210 includes a first detection transistor T1 and a second detection transistor T2. The first terminal of the first detection transistor T1 receives the reset signal RST [ n ]. The second terminal of the first detection transistor T1 is coupled to the voltage stabilizing node NDB. The first terminal of the second detection transistor T2 is coupled to the voltage stabilizing node NDB. The second terminal of the second detection transistor T2 receives the light emission enabling signal EM n. The control terminal of the second detection transistor T2 receives the scan signal SN [ n ].

The light emission detection circuit 220 includes a third detection transistor T3, a fourth detection transistor T4, and a fifth detection transistor T5. The first terminal of the third detection transistor T3 is coupled to the voltage stabilizing node NDB. The control terminal of the third detection transistor T3 receives the scan signal SN [ n ]. The first terminal of the fourth detection transistor T4 is coupled to the voltage stabilizing node NDB. The control terminal of the fourth detection transistor T4 receives the reset signal RST n. The first terminal of the fifth detection transistor T5 is coupled to the second terminal of the third detection transistor T3 and the second terminal of the fourth detection transistor T4. The second terminal of the fifth detection transistor T5 is coupled to the low voltage VGL. The control terminal of the fifth detection transistor T5 receives the light-emitting enable signal EM n.

The judgment circuit 230 includes a voltage stabilizing circuit 231, a pull-up circuit 232, a transmission circuit 233, and a pull-down circuit 234. The voltage stabilizing circuit 231 is coupled to the voltage stabilizing node NDB. The voltage stabilizing circuit 231 provides voltage stabilization to the voltage stabilizing node NDB. The pull-up circuit 232 is coupled to the voltage stabilizing node NDB. The transmission circuit 233 is coupled to the pull-up circuit 232. The pull-down circuit 234 is coupled to the transmission circuit 233. In this embodiment, the pull-up circuit 232 is disabled in response to the first level (e.g., high level) at the voltage stabilizing node NDB, such that the transmission circuit 233 is turned on by the pull-down circuit 234 to output the light emitting enable signal EM [ n ] to the driving circuit DC. The pull-up circuit 232 is enabled in response to the second level (e.g., low level) at the voltage stabilizing node NDB, so that the transmission circuit 233 is turned off to stop outputting the light emission enabling signal EM n to the driving circuit DC.

In the present embodiment, the voltage stabilizing circuit 231 includes a capacitor C1. The capacitor C1 is coupled between the high voltage VGH and the voltage stabilizing node NDB. The voltage stabilizing circuit 231 may bias the voltage stabilizing node NDB with the high voltage VGH. The pull-up circuit 232 includes a transistor T6. The first terminal of the transistor T6 is coupled to the high voltage VGH. A second terminal of the transistor T6 is coupled to the transmission circuit 233. The control terminal of the transistor T6 is coupled to the voltage stabilizing node NDB and the voltage stabilizing circuit 231. The transmission circuit 233 includes transistors T7 and T8. The first terminal of the transistor T7 is coupled to the second terminal of the transistor T6. The control terminal of the transistor T7 receives the light emission enabling signal EM n. The first terminal of the transistor T8 is coupled to the control terminal of the transistor T7 for receiving the light emitting enable signal EM n. The second terminal of the transistor T8 is coupled to the first terminal of the transistor T7. The second terminal of the transistor T8 is used as the output terminal of the judging circuit 230. The control terminal of the transistor T8 is coupled to the second terminal of the transistor T7. Pull-down circuit 234 includes resistor R1. The resistor R1 is coupled between the control terminal of the transistor T8 and the low voltage VGL.

In the present embodiment, the first detection transistor T1, the second detection transistor T2, the third detection transistor T3, the fourth detection transistor T4, the fifth detection transistor T5, and the transistors T6 to T8 are exemplified as P-type transistors, respectively. In some embodiments, the first, second, third, fourth, fifth and third detection transistors T1, T2, T3, T4, T5 and the transistors T6 to T8 may also be N-type transistors.

Referring to fig. 1, 2A and 3, in the first stage P1, the first detection transistor T1 and the second detection transistor T2 may commonly provide the first detection signal SD1 with the first level (high level) to the voltage stabilizing node NDB based on the normal timing of the scan signal SN [ n ], the reset signal RST [ n ] and the light emitting enable signal EM [ n ]. In the second stage P2, the third detection transistor T3, the fourth detection transistor T4, and the fifth detection transistor T5 may commonly supply the second detection signal SD2 having the first level to the voltage stabilizing node NDB based on the normal timings of the scan signal SN [ n ], the reset signal RST [ n ], and the light emitting enable signal EM [ n ]. The first detection signal SD1 and the second detection signal SD2 both have a high level. Therefore, the level at the regulated node NDB is maintained at a high level. The transistor T6 will be turned off. The voltage value at the control terminal of the transistor T8 is pulled down to a low level by the pull-down circuit 234. Accordingly, the transistor T8 is turned on to output the received light emission enable signal EM [ n ] to the driving circuit DC.

Referring to fig. 1, 2B and 3, in the present embodiment, in the first stage P1, based on the abnormal timing of the scan signal SN [ n ], the first detection transistor T1 and the second detection transistor T2 can jointly provide the first detection signal SD1 with the second level (low level) to pull down the level at the voltage stabilizing node NDB. The transistor T6 is turned on. The transistor T6 sets the level of the second terminal of the transistor T8 to a high level using the high voltage VGH. Therefore, the enable transistor TEM of the driving circuit DC stops driving the light emitting element LE based on the high level at the second end of the transistor T8. In addition, in the second stage P2, the light emission enable signal EM [ n ] has a low level. The transistor T7 is turned on in response to the light emission enable signal EM [ n ] having a low level. The transistor T6 turns off the transistor T8 with the high voltage VGH. Therefore, the light emission enable signal EM [ n ] having a low level is turned on and is not output to the driving circuit DC.

Referring to fig. 1, 2C and 3, in the first stage P1, the first detection transistor T1 and the second detection transistor T2 may provide the first detection signal SD1 with the second level (low level) together to pull down the level at the voltage stabilizing node NDB based on the light emitting enable signal EM [ n ] with the low level. The transistor T6 is turned on. The transistor T7 is turned on in response to the light emission enable signal EM [ n ] having a low level. The transistor T6 uses the high voltage VGH to set the level of the second terminal of the transistor T8 and the control terminal of the transistor T8 to a high level. Thus, the transistor T8 is turned off. In addition, the enable transistor TEM of the driving circuit DC stops driving the light emitting element LE based on the high level at the second end of the transistor T8. In the second phase P2, the light-emitting enable signal EM n still has a low level. Thus, transistor T8 is still turned off. The light emission enable signal EM n having a low level is turned on and is not output to the driving circuit DC.

Referring to fig. 1, 2D and 3, in the second stage P2, the third detection transistor T3, the fourth detection transistor T4 and the fifth detection transistor T5 may commonly provide the second detection signal SD2 with the second level (low level) to pull down the level at the voltage stabilizing node NDB based on the abnormal timing of the scan signal SN [ n ] and the reset signal RST [ n ] with negative pulses. The transistor T6 is turned on. The transistor T7 is turned on in response to the light emission enable signal EM [ n ] having a low level. The transistor T6 uses the high voltage VGH to set the level of the second terminal of the transistor T8 and the control terminal of the transistor T8 to a high level. Thus, the transistor T8 is turned off. In addition, the enable transistor TEM of the driving circuit DC stops driving the light emitting element LE based on the high level at the second end of the transistor T8. In the second phase P2, the light-emitting enable signal EM n still has a low level. Thus, transistor T8 is still turned off. The light emission enable signal EM n having a low level is turned on and is not output to the driving circuit DC.

Referring to fig. 4, fig. 4 is a second circuit schematic of the detection circuit according to the first embodiment. In the present embodiment, the detection circuit 200 'includes a program detection circuit 210, a light emission detection circuit 220, and a determination circuit 230'. The implementation of the program detection circuit 210 and the light emission detection circuit 220 can be referred to the previous embodiments, and will not be repeated here. The judgment circuit 230 'includes a voltage stabilizing circuit 231, a pull-up circuit 232, a transmission circuit 233, and a pull-down circuit 234'. The implementation of the voltage stabilizing circuit 231, the pull-up circuit 232 and the transmission circuit 233 can be referred to the previous embodiments, and will not be repeated here. In this embodiment, the pull-down circuit 234' includes a transistor T9. A first terminal of the transistor T9 is coupled to the control terminal of the transistor T8. The second terminal of the transistor T9 and the control terminal of the transistor T9 are coupled to the low voltage VGL. The transistor T9 is used to provide an equivalent resistor between the control terminal of the transistor T8 and the low voltage VGL. In the present embodiment, the transistor T9 is exemplified by a P-type transistor, but the disclosure is not limited thereto.

Referring to fig. 5, fig. 5 is a third circuit schematic of the detection circuit according to the first embodiment. In the present embodiment, the detection circuit 200″ includes a program detection circuit 210, a light emission detection circuit 220, and a determination circuit 230″. The implementation of the program detection circuit 210 and the light emission detection circuit 220 can be referred to the previous embodiments, and will not be repeated here. The judgment circuit 230″ includes a voltage stabilizing circuit 231, a pull-up circuit 232, a transmission circuit 233, and a pull-down circuit 234". The implementation of the voltage stabilizing circuit 231, the pull-up circuit 232 and the transmission circuit 233 can be referred to the previous embodiments, and will not be repeated here. In the present embodiment, the pull-down circuit 234″ includes transistors T9, T10, T11. A first terminal of the transistor T9 is coupled to the control terminal of the transistor T8. The second terminal of the transistor T9 is coupled to the low voltage VGL. The first terminal of the transistor T10 is coupled to the high voltage VGH. The second terminal of the transistor T10 is coupled to the control terminal of the transistor T9. The control terminal of the transistor T10 is coupled to the voltage stabilizing node NDB. The first terminal of the transistor T11 is coupled to the second terminal of the transistor T10. The second terminal of the transistor T11 and the control terminal of the transistor T11 are coupled to the low voltage VGL. The transistor T11 is used to provide an equivalent resistor between the control terminal of the transistor T9 and the low voltage VGL.

In the present embodiment, when at least one of the first detection signal SD1 and the second detection signal SD2 has a low level, the level at the voltage stabilizing node NDB is a low level. The transistors T6, T10 are turned on. Thus, the transistor T6 turns off the transistor T8 with the high voltage VGH. At this time, the transistor T10 turns off the transistor T9 with the high voltage VGH. Therefore, there is no leakage current between the control terminal of the transistor T8 and the low voltage VGL.

When both the first detection signal SD1 and the second detection signal SD2 have a high level, the transistors T6, T10 are turned off. The transistor T11 pulls down the control terminal level of the transistor T9 to a low level. The transistor T9 is turned on. Accordingly, the transistor T8 is turned on to transmit the light emission enable signal EM [ n ]. In the present embodiment, the transistors T9 to T11 are exemplified by P-type transistors, respectively, but the disclosure is not limited thereto.

Referring to fig. 6, fig. 6 is a schematic diagram of an electronic device according to a second embodiment of the invention. In the present embodiment, the electronic device 30 includes a next stage driving circuit DCN and a detecting circuit 300. The detection circuit 300 includes a drive detection circuit 310, a determination circuit 320, and a correction circuit 330. The driving detection circuit 310 receives a scan signal SN [ n ] and a light emission enable signal EM [ n ] for a driving circuit (e.g., the driving circuit DC shown in fig. 1). The driving detection circuit 310 provides a driving detection signal SD3 according to the scan signal SN [ n ] and the light emitting enable signal EM [ n ]. The judging circuit 320 is coupled to the driving detecting circuit 310. The judging circuit 320 judges whether to output the scan signal SN [ n ] and the light emission enabling signal EM [ n ] to the next stage driving circuit DCN according to the driving detection signal SD3. The calibration circuit 330 is coupled to the determination circuit 320. The correction circuit 330 corrects the level of the output of the determination circuit 320 according to the scan signal SN [ n ] and the light emission enable signal EM [ n ].

In the present embodiment, the detection circuit 300 can determine whether the scan signal SN [ n ] and the light emission enable signal EM [ n ] are abnormal according to the driving detection signal SD3, and stop outputting the light emission enable signal EM [ n ] to the driving circuit DCN accordingly.

The detection circuit 300 may be applied to a display device, for example. The driving circuit is, for example, a pixel driving circuit disposed in the pixel unit (the disclosure is not limited thereto). The next stage driving circuit DCN is a gate driving circuit. In this embodiment, the next driving circuit DCN transmits the scan signal SN [ n ] and the light emission enabling signal EM [ n ] through the detecting circuit 300. The next stage driving circuit DCN generates a next stage scan signal SN [ n+1] according to the scan signal SN [ n ], and generates a next stage light emission enable signal EM [ n+1] according to the light emission enable signal EM [ n ].

In the present embodiment, the determining circuit 320 determines whether the scan signal SN [ n ] and the light emitting enable signal EM [ n ] are abnormal according to the driving detection signal SD 3. When it is determined that at least one of the scan signal SN [ n ] and the light emission enable signal EM [ n ] is abnormal, the determination circuit 320 stops outputting the scan signal SN [ n ] and the light emission enable signal EM [ n ] to the next stage driving circuit DCN. Further, the correction circuit 330 corrects the level of the output of the determination circuit 320. Therefore, the next driving circuit DCN does not generate the next scan signal SN [ n+1] and the next light emission enable signal EM [ n+1].

On the other hand, when it is determined that no abnormality occurs in both the scan signal SN [ n ] and the light emission enable signal EM [ n ], the determination circuit 320 outputs the scan signal SN [ n ] and the light emission enable signal EM [ n ] to the next stage driving circuit DCN. Therefore, the next driving circuit DCN generates the next scanning signal SN [ n+1] and the next light emission enabling signal EM [ n+1].

Referring to fig. 2A and fig. 6, in the present embodiment, the driving detection circuit 310 does not provide the driving detection signal SD3 with the second level (low level) based on the normal timing of the scan signal SN [ n ] and the light emitting enable signal EM [ n ]. Therefore, the determining circuit 320 outputs the scan signal SN [ n ] and the light emitting enable signal EM [ n ] to the next driving circuit DCN.

Referring to fig. 2C, 2D and 6, in the present embodiment, the driving detection circuit 310 provides the driving detection signal SD3 with the second level based on the abnormal timing of the scan signal SN [ n ] and/or the light emitting enable signal EM [ n ]. Therefore, the judging circuit 320 can stop outputting the scan signal SN [ n ] and the light emitting enable signal EM [ n ] to the next stage driving circuit DCN according to the driving detection signal SD3 having the second level. In addition, the correction circuit 330 corrects the level of the output of the determination circuit 320 according to the abnormal timing of the scan signal SN [ n ] and/or the light emission enable signal EM [ n ].

Referring to fig. 7, fig. 7 is a first circuit schematic of the electronic device according to the second embodiment. In the present embodiment, the electronic device 400 includes a driving detection circuit 410, a determination circuit 420, and a correction circuit 430. The driving detection circuit 410 includes a first detection transistor T1 'and a second detection transistor T2'. The first terminal of the first detection transistor T1' is coupled to the low voltage VGL. The control terminal of the first detection transistor T1' receives the light emission enabling signal EM n. The first terminal of the second detection transistor T2 'is coupled to the second terminal of the first detection transistor T1'. The second terminal of the second detection transistor T2 'is coupled to the voltage stabilizing node NDB'. The control terminal of the second detection transistor T2' receives the scan signal SN [ n ].

The judging circuit 420 includes a voltage stabilizing circuit 421, a pull-up circuit 422, a transmitting circuit 423, and a pull-down circuit 424. The voltage stabilizing circuit 421 is coupled to the voltage stabilizing node NDB'. The voltage stabilizing circuit 421 provides voltage stabilization to the voltage stabilizing node NDB'. The pull-up circuit 422 is coupled to the voltage stabilizing node NDB'. The transmission circuit 423 is coupled to the pull-up circuit 422. The pull-down circuit 424 is coupled to the transmission circuit 423. In this embodiment, the pull-up circuit 422 is disabled in response to the first level (e.g., high level) at the voltage stabilizing node NDB', so that the transmission circuit 423 is turned on by the pull-down circuit 424 to output the scan signal SN [ n ] and the light emitting enable signal EM [ n ] to the next driving circuit DCN. The pull-up circuit 422 is enabled in response to the second level (e.g., low level) at the voltage stabilizing node NDB', so that the transmission circuit 423 is turned off to stop outputting the light emitting enable signal EM n to the next stage driving circuit DCN.

In the present embodiment, the voltage stabilizing circuit 421 includes a capacitor C2. The capacitor C2 is coupled between the high voltage VGH and the regulated node NDB'. The voltage stabilizing circuit 421 can bias the voltage stabilizing node NDB' with the high voltage VGH. The pull-up circuit 422 includes a transistor T4'. The first terminal of the transistor T4' is coupled to the high voltage VGH. The second terminal of the transistor T4' is coupled to the transmission circuit 423. The control terminal of the transistor T4 'is coupled to the voltage stabilizing node NDB'. The transmission circuit 423 includes transistors T5', T6'. The first terminal of the transistor T5' receives the scan signal SN [ n ]. The second terminal of the transistor T5' is coupled to the next stage driving circuit DCN. The second terminal of the transistor T5' is used as the first output terminal of the judging circuit 420. The control terminal of the transistor T5 'is coupled to the second terminal of the transistor T4'. The first terminal of the transistor T6' receives the light emission enable signal EM n. The second terminal of the transistor T6' is coupled to the next stage driving circuit DCN. A second terminal of the transistor T6' is used as a second output terminal of the judging circuit 420. The control terminal of the transistor T6 'is coupled to the second terminal of the transistor T4'. Pull-down circuit 424 includes resistor R2. The resistor R2 is coupled between the control terminals of the transistors T5', T6' and the low voltage VGL.

In the present embodiment, the correction circuit 430 includes transistors T7', T8', T9', T10'. The first terminal of the transistor T7' is coupled to the high voltage VGH. The control terminal of the transistor T7' receives the light emission enabling signal EM n. The first terminal of the transistor T8 'is coupled to the second terminal of the first detection transistor T7'. The second terminal of the transistor T8 'is coupled to the second terminal of the transistor T5'. The control terminal of the transistor T8' receives the scan signal SN [ n ]. The first terminal of the transistor T9' is coupled to the high voltage VGH. The control terminal of the transistor T9' receives the light emission enabling signal EM n. The first terminal of the transistor T10 'is coupled to the second terminal of the first detection transistor T9'. A second terminal of the transistor T10 'is coupled to a second terminal of the transistor T6'. The control terminal of the transistor T10' receives the scan signal SN [ n ].

Referring to fig. 2A, 6 and 7, in the present embodiment, based on the normal timing of the scan signal SN [ n ] and the light-emitting enable signal EM [ n ], the scan signal SN [ n ] and the light-emitting enable signal EM [ n ] do not have low levels at the same time. The first detection transistor T1 'and the second detection transistor T2' are not turned on at the same time. The driving detection signal SD3 having the second level (low level) is not supplied to the voltage stabilizing node NDB'. Therefore, the level at the regulated node NDB' is maintained at a high level. The transistor T4' will be turned off. The voltage values at the control terminals of the transistors T5', T6' are pulled down to a low level by the pull-down circuit 424. Accordingly, the transistor T5' is turned on to output the received scan signal SN [ n ] to the driving circuit DCN. The transistor T6' is turned on to output the received light emission enable signal EM n to the driving circuit DCN.

In addition, the scan signal SN [ n ] and the light emission enable signal EM [ n ] do not have low level at the same time based on the normal timing of the scan signal SN [ n ] and the light emission enable signal EM [ n ]. Transistors T7', T8' are not turned on at the same time. The transistors T9', T10' are not turned on at the same time. Therefore, the correction circuit 430 does not correct the level at the second terminal of the transistor T5 'and the second terminal of the transistor T6' to the high level by the high voltage VGH.

Referring to fig. 2C, 2D, 6 and 7, in the present embodiment, based on the abnormal timing of the scan signal SN [ n ] and the light-emitting enable signal EM [ n ], the scan signal SN [ n ] and the light-emitting enable signal EM [ n ] have low levels at the same time. Therefore, the first detection transistor T1' and the second detection transistor T2' provide the driving detection signal SD3 having the second level to pull down the level at the voltage stabilizing node NDB '. The transistor T4' is turned on and the control terminal of the transistor T5', T6' is set to a high level by the high voltage VGH. Thus, transistors T5', T6' are turned off. The transistor T5' is turned off to stop outputting the received scan signal SN [ n ] to the driving circuit DCN. The transistor T6' is turned off to stop outputting the received light emission enable signal EM n to the driving circuit DCN.

In addition, based on the abnormal timing of the scan signal SN [ n ] and the light emission enable signal EM [ n ]. Transistors T7', T8', T9', T10' are turned on simultaneously. Therefore, the correction circuit 430 corrects the level at the second terminal of the transistor T5 'and the level at the second terminal of the transistor T6' to the high level by the high voltage VGH.

In addition, the electronic device 400 further includes a reset circuit 440. The reset circuit 440 is coupled to the voltage stabilizing node NDB'. The reset circuit 440 resets the level at the regulated node NDB' based on a specific timing. In the present embodiment, the reset circuit 440 resets the level at the voltage stabilizing node NDB' based on the timing of the light emission enable signal EM [ n ]. The reset circuit 440 includes a transistor T3'. The first terminal of the transistor T3' receives the light emission enable signal EM n. The second terminal of the transistor T3' and the control terminal of the transistor T3' are coupled to the voltage stabilizing node NDB '. When the light-emitting enable signal EM n is at a high level, the reset circuit 440 resets the level at the voltage stabilizing node NDB' to a high level to allow the pull-up circuit 422 to return to a normal operation state. In the present embodiment, the first detecting transistor T1', the second detecting transistor T2', and the transistors T3 'to T10' are respectively exemplified by P-type transistors, but the disclosure is not limited thereto.

Referring to fig. 8, fig. 8 is a second circuit schematic of the electronic device according to the second embodiment. In the present embodiment, the electronic device 400 'includes a driving detection circuit 410, a determination circuit 420', a correction circuit 430, and a reset circuit 440. The implementation of the driving detection circuit 410, the correction circuit 430 and the reset circuit 440 is the same as the previous embodiments, and will not be repeated here. The judging circuit 420 'includes a voltage stabilizing circuit 421, a pull-up circuit 422, a transmitting circuit 423, and a pull-down circuit 424'. The implementation of the voltage stabilizing circuit 421, the pull-up circuit 422, and the transmission circuit 423 are similar to the previous embodiments, and will not be repeated here. In this embodiment, the pull-down circuit 424 'includes a transistor T11'. The first terminal of the transistor T11' is coupled to the control terminal of the transistor T5', T6 '. The second terminal of the transistor T11 'and the control terminal of the transistor T11' are coupled to the low voltage VGL. The transistor T11' is used to provide an equivalent resistor between the control terminal of the transistor T5', T6' and the low voltage VGL. In the present embodiment, the transistor T11' is exemplified by a P-type transistor, but the disclosure is not limited thereto.

Referring to fig. 9, fig. 9 is a third circuit schematic of the electronic device according to the second embodiment. In the present embodiment, the electronic device 400″ includes a driving detection circuit 410, a determination circuit 420", a correction circuit 430 and a reset circuit 440. The implementation of the driving detection circuit 410, the correction circuit 430 and the reset circuit 440 is the same as the previous embodiments, and will not be repeated here. The determination circuit 420″ includes a voltage stabilizing circuit 421, a pull-up circuit 422, a transmission circuit 423, and a pull-down circuit 424". The implementation of the voltage stabilizing circuit 421, the pull-up circuit 422, and the transmission circuit 423 are similar to the previous embodiments, and will not be repeated here.

In this embodiment, the pull-down circuit 424 "includes transistors T11', T12', T13'. The first terminal of the transistor T11' is coupled to the control terminal of the transistor T5', T6'. The second terminal of the transistor T11' is coupled to the low voltage VGL. The first terminal of the transistor T12' is coupled to the high voltage VGH. The second terminal of the transistor T12 'is coupled to the control terminal of the transistor T11'. The control terminal of the transistor T12 'is coupled to the voltage stabilizing node NDB'. The first terminal of the transistor T13 'is coupled to the second terminal of the transistor T12'. The second terminal of the transistor T13 'and the control terminal of the transistor T13' are coupled to the low voltage VGL. The transistor T13 'is used to provide an equivalent resistor between the control terminal of the transistor T11' and the low voltage VGL.

In the present embodiment, when the level at the voltage stabilizing node NDB ' is low, the transistors T4', T12' are turned on. Thus, transistor T4' turns off transistors T5', T6' with a high voltage VGH. At this time, the transistor T12 'turns off the transistor T11' with the high voltage VGH. Therefore, there is no leakage current between the control terminals of the transistors T5', T6' and the low voltage VGL.

When the level at the regulated node NDB ' is high, the transistors T4', T12' are turned off. The transistor T13 'pulls down the control terminal level of the transistor T11' to a low level. The transistor T11' is turned on. Thus, the transistor T5' is turned on to transmit the scan signal SN [ n ]. The transistor T6' is turned on to transmit the light emission enable signal EM [ n ]. In the present embodiment, the transistors T11 'to T13' are exemplified by P-type transistors, respectively, but the disclosure is not limited thereto.

Referring to fig. 10, fig. 10 is a schematic diagram of an electronic device according to a third embodiment of the invention. In the present embodiment, the electronic device 40 includes a pixel unit PU, a next stage driving circuit DCN, and

detection circuits

100 and 300. In the present embodiment, the detection circuit 100 receives a scan signal SN [ n ], a reset signal RST [ n ], and a light emission enable signal EM [ n ] for the driving circuit DC. The detection circuit 100 provides a first detection signal SD1 in a first stage and a second detection signal SD2 in a second stage according to the scan signal SN [ n ], the reset signal RST [ n ] and the light-emitting enable signal EM [ n ]. The detection circuit 100 determines whether to output the light emission enabling signal EM [ n ] to the driving circuit DC in the pixel unit PU according to the first detection signal SD1 and the second detection signal SD2. The detection circuit 300 receives a scan signal SN [ n ] and a light emission enable signal EM [ n ] for the driving circuit DC. The detection circuit 300 provides a driving detection signal SD3 according to the scan signal SN [ n ] and the light emitting enable signal EM [ n ]. The detection circuit 300 outputs the scan signal SN [ n ] and the light emission enable signal EM [ n ] to the next stage driving circuit DCN according to the driving detection signal SD3. The implementation details of the detection circuit 100 may be sufficiently taught in the embodiments of fig. 1, 3, 4, and 5 and are not repeated here. The implementation details of the detection circuit 300 may be sufficiently taught in the embodiments of fig. 6, 7, 8, and 9 and are not repeated here.

In some embodiments, detection circuit 300 or portions of the circuitry of detection circuit 300 may be integrated into detection circuit 100. In some embodiments, detection circuit 100 or portions of the circuitry of detection circuit 100 may be integrated into detection circuit 300.

Based on the foregoing, the present disclosure proposes various aspects of an electronic device. The electronic device detects the plurality of signals to provide at least one detection signal, and judges whether to output the signals to the driving circuit according to the at least one detection signal. In this way, the electronic device of the present disclosure can determine whether the plurality of signals are abnormal according to the at least one detection signal, and stop outputting the plurality of signals to the related driving circuit accordingly.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, but not limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that the electronic device comprises:

detection circuit, including:

a programming detection circuit configured to receive a scan signal, a reset signal, and a light-emitting enable signal for driving a circuit, and provide a first-stage the first detection signal of

a light-emitting detection circuit configured to receive the scan signal, the reset signal, and the light-emitting enable signal, and provide a second the second detection signal of the stage; and

A judging circuit, coupled to the programming detection circuit and the light-emitting detection circuit, configured to judge whether to output the light-emitting enable signal to the driver according to the first detection signal and the second detection signal circuit.

2. The electronic device according to claim 1, characterized in that:

The driving circuit is a pixel driving circuit arranged in the pixel unit,

the first stage is a data input stage for the driver circuit, and

The second phase is a light emitting phase for the driving circuit.

3. The electronic device according to claim 1, characterized in that:

The judging circuit judges whether an abnormality occurs in the first stage and the second stage according to the first detection signal and the second detection signal, and

When it is determined that at least one of the first stage and the second stage is abnormal, the judging circuit stops outputting the light-emitting enabling signal to the driving circuit.

4. The electronic device according to claim 3, wherein when the judging circuit judges that neither the first stage nor the second stage has When an abnormality occurs, the light-emitting enabling signal is output to the driving circuit.

5. The electronic device according to claim 1, wherein the programming detection circuit comprises:

A first detection transistor, wherein the first terminal of the first detection transistor and the control terminal of the first detection transistor receive the reset signal, wherein the second terminal of the first detection transistor is coupled to a voltage stabilizing node ;as well as

A second detection transistor, wherein the first terminal of the second detection transistor is coupled to the voltage regulation node, wherein the second terminal of the second detection transistor receives the light-emitting enable signal, wherein the second detection The control terminal of the transistor receives the scanning signal.

6. The electronic device according to claim 5, wherein the light emitting detection circuit comprises:

a third detection transistor, wherein a first terminal of the third detection transistor is coupled to the voltage stabilizing node, wherein a control terminal of the third detection transistor receives the scan signal;

a fourth detection transistor, wherein a first terminal of the fourth detection transistor is coupled to the voltage stabilizing node, wherein a control terminal of the fourth detection transistor receives the reset signal; and

A fifth detection transistor, wherein the first terminal of the fifth detection transistor is coupled to the second terminal of the third detection transistor and the second terminal of the fourth detection transistor, wherein the first terminal of the fifth detection transistor Two terminals are coupled to a low gate voltage, wherein the control terminal of the fifth detection transistor receives the light-emitting enabling signal.

7. The electronic device according to claim 5, wherein the judging circuit comprises:

a voltage stabilizing circuit coupled to the voltage stabilizing node and configured to provide a bias voltage to the voltage stabilizing node;

a pull-up circuit coupled to the voltage regulator node;

a transmission circuit coupled to the pull-up circuit; and

a pull-down circuit coupled to the transmission circuit,

wherein the pull-up circuit is disabled in response to the first level of the voltage stabilizing node, so that the transmission circuit is turned on by the pull-down circuit to output the light-emitting enabling signal to the driving circuit, and

The pull-up circuit is enabled in response to the second level of the voltage stabilizing node, so that the transmission circuit is disconnected and stops outputting the light-emitting enabling signal to the driving circuit.

8. An electronic device, characterized in that the electronic device comprises:

next stage drive circuit; and

detection circuit, including:

a driving detection circuit configured to receive a scanning signal and a light-emitting enabling signal for the driving circuit, and provide a driving detection signal according to the scanning signal and the light-emitting enabling signal;

A judging circuit, coupled to the driving detection circuit, configured to judge whether to output the scanning signal and the light-emitting enabling signal to the next-level driving circuit according to the driving detection signal; and

The correction circuit, coupled to the judgment circuit, is configured to correct the output level of the judgment circuit according to the scanning signal and the light-emitting enabling signal.

9. The electronic device according to claim 8, wherein the driving circuit is a pixel driving circuit arranged in a pixel unit, and

The next-stage driving circuit is a gate driving circuit.

10. The electronic device according to claim 8, characterized in that:

The judging circuit judges whether the scanning signal and the light-emitting enabling signal are abnormal according to the driving detection signal, and

When it is judged that at least one of the scanning signal and the light-emitting enabling signal is abnormal, the judging circuit stops outputting the scanning signal and the light-emitting enabling signal to the next-level driving circuit, so The correction circuit corrects the level of the output of the judgment circuit.