KR102635757B1 - Organic light emitting display device and method for driving the same - Google Patents

Abstract

The present invention relates to an organic light emitting display device that can shorten the sensing time for external compensation and a driving method thereof. The organic light emitting display device according to an embodiment of the present invention is connected to a data line, a scan line, and a reference voltage line, and includes a display panel provided with pixels including organic light emitting diodes, and a scan signal output that supplies a scan signal to the scan line. It includes a data voltage supply unit that supplies a data voltage to a data line, and a timing control unit that controls the scan signal output unit and the data voltage supply unit in a normal mode or AGP mode according to a data enable signal input from the outside. The scan signal output unit outputs the second scan signal to the scan line in both the active period and blank period of the frame period in the automatically generated pattern mode. The data voltage supply unit generates the first sensing data voltage according to the first sensing image data in both the active period and blank period of the frame period in the automatic generation pattern mode and supplies it to the data line.

Description

Organic light emitting display device and driving method thereof {ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to an organic light emitting display device and a method of driving the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, recently, various display devices such as liquid crystal display (LCD), plasma display panel (PDP), and organic light emitting display (OLED) have been used. Among these, organic light emitting display devices can be driven at low voltage, are thin, have excellent viewing angles, and have fast response speeds.

An organic light emitting display device includes a display panel including data lines, scan lines, pixels formed at intersections of the data lines and scan lines, a scan driver that supplies scan signals to the scan lines, and a data voltage to the data lines. It includes a data driver that supplies data. Each pixel includes an organic light emitting diode, a driving transistor that controls the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, and data in the data line in response to the scan signal of the scan line. It includes a scan transistor that supplies voltage to the gate electrode of the driving transistor.

The threshold voltage of the driving transistor may vary for each pixel due to reasons such as process deviation during manufacturing of the organic light emitting display device or deterioration of the driving transistor due to long-term operation. In other words, when the same data voltage is applied to the pixels, the current supplied to the organic light emitting diode must be the same. However, due to the difference in the threshold voltage of the driving transistor between the pixels, the current supplied to the organic light emitting diode must be the same even if the same data voltage is applied to the pixels. The supplied current may vary for each pixel. Additionally, organic light emitting diodes may also deteriorate due to long-term operation, and in this case, the luminance of the organic light emitting diode may vary for each pixel. Accordingly, even if the same data voltage is applied to the pixels, the luminance emitted by the organic light emitting diode may vary for each pixel. To solve this problem, a compensation method was proposed to compensate for the threshold voltage and electron mobility of the driving transistor and the deterioration of the organic light emitting diode.

The threshold voltage and electron mobility of the driving transistor can be compensated by an external compensation method. The external compensation method supplies a preset data voltage to the pixel, senses the source voltage of the driving transistor according to the preset data voltage through a predetermined sensing line, and uses an analog digital converter to convert the sensed voltage to This is a method of converting digital data into sensing data and compensating the digital image data to be supplied to the pixels according to the sensing data.

One frame period includes an active period in which data voltages are supplied to pixels to display an image and a blank period in which an image is idle. Sensing for external compensation is performed during the blank period in order to not affect pixels during the active period for displaying images. Due to this, in an organic light emitting display device that has a FHD (full high definition) resolution of 1920 In other words, there is a problem that sensing for external compensation takes a long time.

The present invention provides an organic light emitting display device and a driving method thereof that can shorten the sensing time for external compensation.

The organic light emitting display device according to an embodiment of the present invention is connected to a data line, a scan line, and a reference voltage line, and includes a display panel provided with pixels including organic light emitting diodes, and a scan signal output that supplies a scan signal to the scan line. It includes a data voltage supply unit that supplies a data voltage to a data line, and a timing control unit that controls the scan signal output unit and the data voltage supply unit in a normal mode or AGP mode according to a data enable signal input from the outside. The scan signal output unit outputs the second scan signal to the scan line in both the active period and blank period of the frame period in the automatically generated pattern mode. The data voltage supply unit generates the first sensing data voltage according to the first sensing image data in both the active period and blank period of the frame period in the automatic generation pattern mode and supplies it to the data line.

A method of driving an organic light emitting display device according to an embodiment of the present invention includes controlling the display panel in a normal mode or automatically generated pattern mode according to a data enable signal input from the outside, and controlling the display panel in the active period of the frame period in the normal mode. Supplying a first scan signal to a scan line and supplying a light emitting data voltage to a data line of a display panel, supplying a second scan signal to the scan line during a blank period of the frame period in the normal mode, and supplying a light emitting data voltage to the data line of the display panel. Supplying a first sensing data voltage, supplying a second scan signal to the scan line in both the active period and blank period of the frame period in the automatically generated pattern mode, and supplying the first sensing data voltage to the data line. Includes.

In an embodiment of the present invention, when an abnormal data enable signal is input and the device is driven in AGP mode, both the active period and blank period are controlled in sensing mode. As a result, embodiments of the present invention can shorten the sensing time for external compensation.

1 is a block diagram showing an organic light emitting display device according to an embodiment of the present invention.
FIG. 2 is an example diagram showing the lower substrate, source drive ICs, timing control unit, data compensation unit, flexible films, source circuit board, flexible cable, and control circuit board of the display panel of FIG. 1.
FIG. 3 is a block diagram showing the source drive IC of FIG. 2 in detail.
FIG. 4 is a circuit diagram showing the pixel of FIG. 1 in detail.
FIG. 5 is a block diagram showing the timing control unit of FIG. 1 in detail.
FIGS. 6A to 6E are exemplary diagrams showing a data enable signal that is normally input and a data enable signal that is input abnormally.
FIGS. 7A and 7B are exemplary diagrams showing the active period and blank period of one frame period in normal mode and AGP mode.
Figure 8 is a waveform diagram showing the scan signal and sensing signal supplied to the pixel, the first and second switch control signals supplied to the first and second switches, and the gate voltage and source voltage of the driving transistor in the display mode. .
9A and 9B are exemplary diagrams showing the operation of a pixel during first and second periods in a display mode.
10 is a waveform showing the scan signal and sensing signal supplied to the pixel in the first sensing mode, the first and second switch control signals supplied to the first and second switches, and the gate voltage and source voltage of the driving transistor. It's a degree.
FIGS. 11A to 11C are exemplary diagrams showing the operation of a pixel during first to third periods in the first sensing mode.
12 is a waveform showing the scan signal and sensing signal supplied to the pixel in the second sensing mode, the first and second switch control signals supplied to the first and second switches, and the gate voltage and source voltage of the driving transistor. It's a degree.
FIGS. 13A and 13B are exemplary diagrams showing the operation of a pixel during first and second periods in a second sensing mode.

Like reference numerals refer to substantially the same elements throughout the specification. In the following description, detailed descriptions of configurations and functions known in the technical field of the present invention and cases not related to the core configuration of the present invention may be omitted. The meaning of terms described in this specification should be understood as follows.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

“X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted as only geometrical relationships in which the relationship between each other is vertical, and should not be interpreted as a wider range within which the configuration of the present invention can function functionally. It can mean having direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, “at least one of the first, second, and third items” means each of the first, second, or third items, as well as two of the first, second, and third items. It can mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing an organic light emitting display device according to an embodiment of the present invention. FIG. 2 is an example diagram showing the lower substrate, source drive ICs, timing control unit, flexible films, source circuit board, flexible cable, and control circuit board of the display panel of FIG. 1. FIG. 3 is a block diagram showing the source drive IC of FIG. 2 in detail.

1 to 3, an organic light emitting display device according to an embodiment of the present invention includes a display panel 10, a data driver 20, flexible films 22, a scan driver 40, and a source circuit board ( 50), a timing control unit 60, a reference voltage supply unit 50, a flexible cable 91, and a control circuit board 90.

The display panel 10 includes a display area (AA) and a non-display area (NDA) provided around the display area (AA). The display area AA is an area where pixels P are formed to display an image. The display panel 10 includes data lines (D1 to Dm, m is a positive integer of 2 or more), reference voltage lines (R1 to Rp, p is a positive integer of 2 or more), and scan lines (S1 to Sn, n is a positive integer of 2 or more), and sensing signal lines (SE1 to SEn) are provided. The data lines (D1 to Dm) and the reference voltage lines (R1 to Rp) may intersect the scan lines (S1 to Sn) and the sensing signal lines (SE1 to SEn). The data lines (D1 to Dm) and the reference voltage lines (R1 to Rp) may be parallel to each other. The scan lines (S1 to Sn) and the sensing signal lines (SE1 to SEn) may be parallel to each other.

Each of the pixels (P) is one of the data lines (D1 to Dm), one of the reference voltage lines (R1 to Rp), one of the scan lines (S1 to Sn), and one of the sensing signal lines ( It can be connected to any one of SE1~SEn). Each of the pixels P of the display panel 10 may include an organic light emitting diode (OLED) and a plurality of transistors for supplying current to the organic light emitting diode (OLED), as shown in FIG. 4 . A detailed description of each of the pixels P in the display area will be described later with reference to FIG. 4 .

The data driver 20 may include a plurality of source drive ICs 21 as shown in FIG. 2 . Each of the source drive ICs 21 may be mounted on each of the flexible films 22. Each of the flexible films 22 may be a tape carrier package or a chip on film. Each of the flexible films 22 can be curved or bent. Each of the flexible films 22 may be attached to the lower substrate 11 and the source circuit board 50. Each of the flexible films 22 can be attached to the lower substrate 11 using a tape automated bonding (TAB) method using an anisotropic conductive film, and as a result, the source drive IC 21 is connected to the data line. It can be connected to fields (D1~Dm). The source circuit board 50 may be connected to the control circuit board 90 by a flexible cable 91. The source circuit board 50 may be a printed circuit board.

Each of the source drive ICs 21 includes a data voltage supply unit 120 and a sensing unit 130 as shown in FIG. 3 . The sensing unit 130 may include a sensing data output unit 140 and first and second switches SW1 and SW2. In FIG. 3, for convenience of explanation, one source drive IC 21 has w (w is a positive integer satisfying 1≤w≤m) data lines (D1 to Dw) and z (z is 1≤m). The explanation focuses on being connected to (positive integer) reference voltage lines (R1 to Rz) that satisfy z≤p.

The data voltage supply unit 120 is connected to the data lines D1 to Dw and supplies data voltages. The data voltage supply unit 120 receives one of compensation image data (CDATA), first and second sensing image data (PDATA1, PDATA2), and a data control signal (DCS) from the timing control unit 60.

The data voltage supply unit 120 converts the compensation video data (CDATA) into light-emitting data voltages according to the data control signal (DCS) in the display mode and supplies them to the data lines (D1 to Dw). The display mode is a mode in which pixels P emit light to display an image. The light emission data voltage is a voltage for the organic light emitting diode (OLED) of the pixel (P) to emit light with a predetermined brightness.

The data voltage supply unit 120 converts the first sensing image data PDATA1 into a first sensing data voltage according to the data control signal DCS in the first sensing mode and supplies it to the data lines D1 to Dw. The first sensing mode is a mobility compensation mode that senses the source voltage of the driving transistor (DT) to compensate for the electron mobility of the driving transistor of each pixel (P).

The data voltage supply unit 120 converts the second sensing image data PDATA2 into a second sensing data voltage according to the data control signal DCS in the second sensing mode and supplies it to the data lines D1 to Dw. The second sensing mode is a threshold voltage compensation mode that senses the source voltage of the driving transistor (DT) to compensate for the threshold voltage of the driving transistor of each pixel (P).

The sensing unit 130 supplies a reference voltage to the reference voltage lines (R1 to Rz) in the display mode, and controls the voltage of the pixels (P) through the reference voltage lines (R1 to Rz) in the first and second sensing modes. The source voltages of the driving transistors are sensed, and the sensed voltages are converted into sensing data, which is digital data, and output. The sensing unit 130 may include a sensing data output unit 140 and first and second switches SW1 and SW2.

That is, the sensing unit 130 may supply a reference voltage to the reference voltage lines (R1 to Rz) during the active period (ACT) of the frame period in the normal mode as shown in FIG. 7A. In addition, the sensing unit 130 uses reference voltage lines in both the blank period (VBI) of the frame period in the normal mode and the active period (ACT) and blank period (VBI) of the frame period in the AGP mode, as shown in FIGS. 7A and 7B. The source voltages of the driving transistors of the pixels (P) can be sensed through (R1 to Rz), and the sensed voltages can be converted into sensing data, which is digital data, and output.

The sensing data output unit 140 may be an analog digital converter. The sensing data output unit 140 senses the source voltages of the driving transistors of the pixels (P) through the reference voltage lines (R1 to Rz) in the first and second sensing modes, and converts the sensed voltages into digital data. It is converted into data (SD1, SD2) and output to the timing control unit 60.

The first switch SW1 is connected between the reference voltage lines (R1 to Rz) and the voltage supply unit 80 and switches the connection between the reference voltage lines (R1 to Rz) and the voltage supply unit 80. The first switch SW1 may be turned on and off by the first switch control signal SCS1 input from the timing controller 60. When the first switch (SW1) is turned on by the first switch control signal (SCS1), the reference voltage lines (R1 to Rz) are connected to the voltage supply unit 80, so the reference voltage of the voltage supply unit 80 is It may be supplied to the reference voltage lines (R1 to Rz).

The second switches (SW2) are connected between the reference voltage lines (R1 to Rz) and the sensing data output unit 140 to switch the connection between the reference voltage lines (R1 to Rz) and the sensing data output unit 140. do. The second switches SW2 may be turned on and off by the second switch control signal SCS2 input from the timing controller 60. When the second switches (SW2) are turned on by the second switch control signal (SCS2), the reference voltage lines (R1 to Rz) are connected to the sensing data output unit 140, so the reference voltage lines (R1 to Rz) are connected to the sensing data output unit 140. The source voltage of the driving transistor of each pixel (P) can be sensed through each Rz).

The scan driver 40 includes a scan signal output unit 41 and a sensing signal output unit 42.

The scan signal output unit 41 supplies scan signals to the scan lines S1 to Sn according to the scan control signal SCS input from the timing controller 60. The scan signal output unit 41 generates first scan signals according to the scan control signal (SCS) in the display mode and supplies them to the scan lines (S1 to Sn). Additionally, the scan signal output unit 41 supplies second scan signals to the scan lines S1 to Sn according to the scan control signal SCS in the first sensing mode. Additionally, the scan signal output unit 41 supplies third scan signals to the scan lines S1 to Sn according to the scan control signal SCS in the second sensing mode. The pulse width of the first scan signal, the pulse width of the second scan signal, and the pulse width of the third scan signal may be different from each other.

The sensing signal output unit 42 supplies sensing signals to the sensing signal lines SE1 to SEn according to the sensing control signal SENCS input from the timing control unit 60. The sensing signal output unit 42 generates first sensing signals according to the sensing control signal SENCS in the display mode and supplies them to the sensing signal lines SE1 to SEn. The sensing signal output unit 42 generates second sensing signals according to the sensing control signal (SENCS) in the first sensing mode and supplies them to the sensing signal lines (SE1 to SEn). The sensing signal output unit 42 generates third sensing signals according to the sensing control signal (SENCS) in the second sensing mode and supplies them to the sensing signal lines (SE1 to SEn). The pulse width of the first sensing signal, the pulse width of the second sensing signal, and the pulse width of the third sensing signal may be different from each other.

The scan signal output unit 41 and the sensing signal output unit 42 may include a plurality of transistors and be formed directly in the non-display area (NDA) of the display panel 10 using a gate driver in panel (GIP) method. Alternatively, the scan signal output unit 41 and the sensing signal output unit 42 may be formed in the form of a driving chip and mounted on a flexible film (not shown) connected to the display panel 10.

The timing control unit 60 receives digital image data (DATA) and timing signals (TS) from the outside. Timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing control unit 60 controls the data driver 20, the scan signal output unit 41, and the sensing unit in one of the normal mode and the auto generation pattern mode (hereinafter referred to as “AGP”) according to the data enable signal. The operation of the signal output unit 42 can be controlled. The timing control unit 60 may control the operations of the data driver 20, the scan signal output unit 41, and the sensing signal output unit 42 in the display mode during the active period of the frame period in the normal mode. The timing control unit 60 may control the operations of the data driver 20, the scan signal output unit 41, and the sensing signal output unit 42 in the first sensing mode during the blank period of the frame period in the normal mode. The timing control unit 60 may control the operations of the data driver 20, the scan signal output unit 41, and the sensing signal output unit 42 in the second sensing mode during the blank period of the frame period in the AGP mode.

The display mode is a mode in which the pixels (P) emit light by supplying light emission data voltages according to the compensation image data (CDATA) to the pixels (P). In normal mode, the active period of the frame period can be controlled by the display mode.

The first sensing mode supplies first sensing data voltages according to the first sensing image data (PDATA1) to the pixels (P) and supplies predetermined voltages to the pixels (P) through the reference voltage lines (R1 to Rp). This is a sensing mode. The first sensing mode is a mode in which the source voltage of the driving transistor of each pixel P is sensed to compensate for the electron mobility of the driving transistor. The source voltage of the driving transistor sensed in the first sensing mode may be converted into first sensing data SD1 by the sensing data output unit 140 and stored in the memory of the timing control unit 60. The organic light emitting display device can be controlled to the first sensing mode as soon as the power is turned on, and as a result, the first sensing data SD1 stored in the memory of the timing controller 60 can be updated. Additionally, the blank period of the frame period in the normal mode can be controlled by the first sensing mode. Additionally, in AGP mode, the active period and blank period of the frame period can be controlled by the first sensing mode.

The second sensing mode supplies second sensing data voltages according to the second sensing image data (PDATA2) to the pixels (P) and supplies predetermined voltages to the pixels (P) through the reference voltage lines (R1 to Rp). This is a sensing mode. The first and second sensing image data PDATA1 and PDATA2 may be different data or the same data. The second sensing mode is a mode in which the source voltage of the driving transistor is sensed to compensate for the threshold voltage of the driving transistor of each pixel (P). The source voltage of the driving transistor sensed in the second sensing mode may be converted into second sensing data SD2 by the sensing data output unit 140 and stored in the memory of the timing control unit 60. The organic light emitting display device can be controlled to the second sensing mode before being turned off, and thus the second sensing data SD2 stored in the memory of the timing control unit 60 can be updated.

The timing control unit 60 generates correction data to correct digital image data (DATA) using the first and second sensing data (SD1, SD2) in normal mode, and applies the correction data to the digital image data (DATA). This generates compensated image data (CDATA). The timing control unit 60 stores first sensed image data (PDATA1) and second sensed image data (PDATA2) in memory. In addition, the timing control unit 60 is driven in the display mode during the active period of the frame period in the normal mode, and in the first sensing mode during the blank period of the frame period in the normal mode and in the active period and blank period of the frame period in the AGP mode. Preferably, a data control signal (DCS) for controlling the operation timing of the data driver 20, a scan control signal (SCS) for controlling the operation timing of the scan signal output unit 41, and a sensing signal output unit 42. Generates a sensing control signal (SENCS) to control the operation timing.

The timing control unit 60 outputs compensated image data (CDATA), first sensed image data (PDATA1), or second sensed image data (PDATA2) and a data control signal (DCS) to the data driver 20. The timing control unit 60 outputs a scan control signal (SCS) to the scan signal output unit 41 and outputs a sensing control signal (SENCS) to the sensing signal output unit 42. In addition, the timing control unit 60 provides first and second switch control signals (SCS1, SCS2) for controlling the first and second switches (SW1, SW2) of the data driver 20. It can be output as .

The voltage supply unit 80 generates a reference voltage and supplies it to the source drive ICs 21 of the data driver 20. The voltage supply unit 80 may generate driving voltages necessary for driving the organic light emitting display device in addition to the reference voltage and supply them to necessary components.

The timing control unit 60 and the voltage supply unit 80 may be mounted on a control circuit board. The control circuit board 90 may be connected to the source circuit board 50 by a flexible cable 91. The control circuit board 90 may be a printed circuit board.

As discussed above, the organic light emitting display device according to an embodiment of the present invention converts digital image data (DATA) into compensated image data (CDATA) using the first and second sensing data (SD1, SD2) sensed in the sensing mode. ) is converted to As a result, the embodiment of the present invention can compensate for the threshold voltage and electron mobility of the driving transistor of each pixel.

FIG. 4 is a circuit diagram showing the pixel of FIG. 1 in detail.

In Figure 4, for convenience of explanation, the jth (j is a positive integer satisfying 1≤j≤m) data line (Dj) and the uth (u is a positive integer satisfying 1≤u≤p) reference voltage. Sub-pixel, voltage supply unit 80, data connected to the line Ru, the kth (k is a positive integer satisfying 1≤k≤n) scan line (Sk), and the kth sensing signal line (SEk) Only the voltage supply unit 120, the ADC 140, and the switch (SW) connected between the u-th reference voltage line (Ru) and the voltage supply unit 80 are shown.

Referring to FIG. 4, the pixel P of the display panel 10 includes an organic light emitting diode (OLED), a driving transistor (DT), first and second switching transistors (ST1, ST2), and a storage capacitor (Cst). may include.

Organic light-emitting diodes (OLEDs) emit light according to the current supplied through a driving transistor (DT). An organic light emitting diode (OLED) may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. there is. When voltage is applied to the anode and cathode electrodes of an organic light-emitting diode (OLED), holes and electrons are moved to the organic light-emitting layer through the hole transport layer and electron transport layer, respectively, and combine with each other in the organic light-emitting layer to emit light. The anode electrode of the organic light emitting diode (OLED) may be connected to the source electrode of the driving transistor (DT), and the cathode electrode may be connected to a second power line (VSL) to which a second power lower than the first power is supplied.

The driving transistor (DT) adjusts the current flowing from the first power line (EVL) to the organic light emitting diode (OLED) according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor (DT) is connected to the first electrode of the first switching transistor (ST1), the source electrode is connected to the anode electrode of the organic light-emitting diode (OLED), and the drain electrode is connected to the first power line (EVL). can be connected to.

The first switching transistor ST1 is turned on by the kth scan signal of the kth scan line Sk to connect the jth data line Dj to the gate electrode of the driving transistor DT. The gate electrode of the first switching transistor (T1) is connected to the kth scan line (Sk), the first electrode is connected to the gate electrode of the first driving transistor (DT1), and the second electrode is connected to the jth data line (Dj). ) can be accessed.

The second switching transistor ST2 is turned on by the kth sensing signal of the kth sensing signal line SEk to connect the uth reference voltage line Ru to the source electrode of the driving transistor DT. The gate electrode of the second switching transistor (ST3) is connected to the k-th sensing signal line (SEk), the first electrode is connected to the u-th reference voltage line (Ru), and the second electrode is the source of the driving transistor (DT). It can be connected to an electrode.

The first electrode of each of the first and second switching transistors ST1 and ST2 may be a source electrode, and the second electrode may be a drain electrode, but it should be noted that they are not limited thereto. That is, the first electrode of each of the first and second switching transistors ST1 and ST2 may be a drain electrode, and the second electrode may be a source electrode.

The storage capacitor (Cst) is formed between the gate electrode and the source electrode of the driving transistor (DT). The storage capacitor (Cst) stores the difference voltage between the gate voltage and source voltage of the driving transistor (DT).

The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed as thin film transistors. In addition, in FIG. 4, the driving transistor (DT) and the first and second switching transistors (ST1, ST2) are explained with a focus on being formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but please note that it is not limited thereto. shall. The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of a P-type MOSFET. In this case, the timing diagrams of FIGS. 9, 11, and 13 can be appropriately modified to suit the characteristics of the P-type MOSFET.

The operation of the pixel P in the display mode will be described later in conjunction with FIGS. 9, 10A, and 10B, and the operation of the pixel P in the first sensing mode will be described later in conjunction with FIGS. 11 and 12A to 12C. do. The operation of the pixel P in the second sensing mode will be described later in conjunction with FIGS. 13, 14A, and 14B.

FIG. 5 is a block diagram showing the timing control unit of FIG. 1 in detail.

Referring to FIG. 5, the timing control unit 60 includes an input signal processor 161, an internal timing signal generator 162, a data compensation unit 163, a data control signal generator 164, and a scan control signal generator ( 165), and a sensing control signal generator 166.

The input signal processor 161 receives digital image data (DATA) and timing signals from the outside. Timing signals include a vertical sync signal (Vsync1), a horizontal sync signal (Hsync1), a data enable signal (DE1), and a dot clock (CLK1). The vertical synchronization signal (Vsync1) is a signal indicating one frame period. The horizontal synchronization signal (Hsync1) is a signal indicating one horizontal period. The data enable signal DE1 is a signal that indicates the period during which valid video data (DATA) is input. The dot clock (CLK1) is a clock signal with a predetermined period.

The input signal processor 161 determines whether a normal data enable signal DE1 is input. The input signal processor 161 counts the number of pulses of the data enable signal DE1 input during one frame period and determines whether the count value corresponds to the set value. If the count value corresponds to the set value, the input signal processor 161 may determine that the normal data enable signal DE1 is input as shown in FIG. 6A. Additionally, the input signal processor 161 may determine that an abnormal data enable signal DE1 is input as shown in FIGS. 6B to 6D when the count value is not the set value. The abnormal data enable signal DE1 may not contain pulses as shown in FIG. 6b, may contain a number of pulses less than the set value as shown in FIG. 6c, or may contain a number of pulses greater than the set value as shown in FIG. 6d. You can.

When it is determined that a normal data enable signal (DE1) is input, the input signal processor 161 outputs digital image data (DATA), a vertical synchronization signal (Vsync1), a horizontal synchronization signal (Hsync1), and a data enable signal (DE1). , and a dot clock (CLK1) are output to the data compensation unit 163. In addition, when the input signal processing unit 161 determines that the normal data enable signal DE1 is input, it generates a mode signal MODE of the first logic level voltage to communicate with the internal timing signal generating unit 162 and the data compensation unit. It can be output as (163). The mode signal MODE of the first logic level voltage may indicate a normal mode.

When the input signal processing unit 161 determines that an abnormal data enable signal (DE1) is input, digital image data (DATA), a vertical synchronization signal (Vsync1), a horizontal synchronization signal (Hsync1), and a data enable signal (DE1) are input. , and the dot clock (CLK1) is not output to the data compensation unit 163. In addition, when the input signal processor 161 determines that an abnormal data enable signal DE1 is input, the input signal processor 161 generates a mode signal MODE of the second logic level voltage to communicate with the internal timing signal generator 162 and the data compensation unit. It can be output as (163). The mode signal (MODE) of the second logic level voltage may indicate the AGP mode.

The internal timing signal generator 162 includes an oscillator and generates internal timing signals having a predetermined frequency. The internal timing signals may be an internal vertical synchronization signal (Vsync2), an internal horizontal synchronization signal (Hsync2), an internal data enable signal (DE2), and an internal dot clock (CLK2). The internal vertical synchronization signal (Vsync2) is a signal indicating one frame period. The internal horizontal synchronization signal (Hsync2) is a signal indicating one horizontal period. The internal data enable signal DE2 is a signal that indicates the period during which valid video data (DATA) is input. The internal dot clock (CLK2) is a clock signal with a predetermined period.

The internal timing signal generator 162 generates an internal vertical synchronization signal (Vsync2), an internal horizontal synchronization signal (Hsync2), and an internal data enable signal (DE2) in AGP mode in which the mode signal (MODE) of the second logic level voltage is input. , and the internal dot clock (CLK2) are output to the data compensation unit 163.

That is, in an embodiment of the present invention, when an abnormal data enable signal DE1 is input, the timing signals input from the outside are determined to be abnormal, and the digital image data (DATA) and timing signals input from the outside are transmitted to the data compensation unit. Instead of outputting to 163, the internal timing signals generated by the internal timing signal generator 162 are output.

The data compensation unit 163 provides correction data to correct the digital image data (DATA) using the first and second sensing data (SD1, SD2) in the general mode in which the mode signal (MODE) of the first logic level voltage is input. Generate and apply correction data to digital image data (DATA) to generate compensated image data (CDATA). The data compensation unit 163 stores first sensed image data (PDATA1) and second sensed image data (PDATA2) in memory. The data compensation unit 163 compensates for compensation image data (CDATA), first sensing image data (PDATA1), or second sensing image data (PDATA2) and timing signals (Vsync1, Hsync1, DE1, CLK1) in normal mode. It is output to the control signal generator 164. Additionally, the data compensation unit 163 outputs timing signals (Vsync1, Hsync1, DE1, CLK1) to the scan control signal generator 165 and the sensing control signal generator 166.

The data compensation unit 163 uses the first sensing image data (PDATA1) and the internal timing signals (Vsync2, Hsync2, DE2, CLK2) as data control signals in the AGP mode in which the mode signal (MODE) of the second logic level voltage is input. It is output to the generation unit 164. The data compensation unit 163 outputs internal timing signals (Vsync2, Hsync2, DE2, CLK2) to the scan control signal generator 165 and the sensing control signal generator 166.

The data control signal generator 164 generates a data control signal (DCS) using timing signals (Vsync1, Hsync1, DE1, and CLK1) in normal mode. Each of the normal mode frame periods (F(N), F(N+1)) may include an active period (ACT) and a blank period (VBI) as shown in FIGS. 7A and 7B.

The data control signal generator 164 outputs the compensated image data (CDATA) and the data control signal (DCS) to the data driver 20 during the active period (ACT) of the frame period in the normal mode. Additionally, the data control signal generator 164 outputs the first sensing image data PDATA1 and the data control signal DCS to the data driver 20 during the blank period (VBI) of the frame period in the normal mode. Additionally, the data control signal generator 164 outputs the second sensing image data PDATA2 and the data control signal DCS to the data driver 20 before the organic light emitting display device is turned off. That is, in the normal mode, the blank period (VBI) of the frame period operates as a sensing period driven in the first sensing mode, as shown in FIG. 7A.

The data control signal generator 164 generates a data control signal (DCS) using internal timing signals (Vsync2, Hsync2, DE2, and CLK2) in AGP mode. Each of the frame periods (F(N), F(N+1)) of the AGP mode may include an active period (ACT) and a blank period (VBI), as shown in FIGS. 7A and 7B. The data control signal generator 164 transmits the first sensed image data (PDATA1) and the data control signal (DCS) to the data driver 20 in both the active period (ACT) and blank period (VBI) of the frame period of the AGP mode. Print out. That is, in AGP mode, the active period (ACT) and blank period (VBI) of the frame period operate as a sensing period driven in the first sensing mode, as shown in FIG. 7B.

The scan control signal generator 165 generates a scan control signal (GCS) using the timing signals (Vsync1, Hsync1, DE1, and CLK1) during the active period (ACT) of the frame period in the normal mode. For this reason, the scan signal output unit 41 may generate first scan signals according to the scan control signal GCS during the active period of the frame period in the normal mode and supply them to the scan lines S1 to Sn.

In addition, the scan control signal generator 165 generates internal timing signals (Vsync2, Hsync2, DE2, CLK2) is used to generate the scan control signal (GCS). For this reason, the scan signal output unit 41 generates signals according to the scan control signal (GCS) in the blank period (VBI) of the frame period in the normal mode and in the active period (ACT) and blank period (VBI) of the frame period in the AGP mode. 2 Scan signals can be generated and supplied to the scan lines (S1 to Sn).

The sensing control signal generator 166 generates a sensing control signal (SENCS) using the timing signals (Vsync1, Hsync1, DE1, and CLK1) during the active period (ACT) of the frame period in the normal mode. Due to this, the sensing signal output unit 42 can generate first sensing signals according to the sensing control signal (SENCS) during the active period (ACT) of the frame period in normal mode and supply them to the sensing lines (SE1 to SEn). .

In addition, the sensing control signal generator 166 generates internal timing signals (Vsync2, Hsync2, DE2, CLK2) is used to generate a sensing control signal (SENCS). For this reason, the sensing signal output unit 42 generates signals according to the sensing control signal (SENCS) in the blank period (VBI) of the frame period in the normal mode and in the active period (ACT) and blank period (VBI) of the frame period in the AGP mode. 2 Sensing signals can be generated and supplied to the sensing lines (SE1 to SEn).

As discussed above, the embodiment of the present invention uses digital video data (DATA) and timing signals (Vsync1, Hsync1, DE1, CLK1) input from the outside in a normal mode in which a normal data enable signal (DE1) is input. It generates a source control signal (DCS), a scan control signal (SCS), and a sensing control signal (SENCS). In an embodiment of the present invention, the active period of the frame period in the normal mode can be controlled by the display mode, and the blank period can be controlled by the sensing period driven in the first sensing mode. Accordingly, an embodiment of the present invention can sense the source voltage of the driving transistors of the pixels P in real time during each blank period.

In addition, in an embodiment of the present invention, instead of digital video data (DATA) and timing signals (Vsync1, Hsync1, DE1, CLK1) input from the outside in AGP mode in which an abnormal data enable signal (DE1) is input, the first Source control signal (DCS), scan control signal (SCS), and sensing control signal (SENCS) are generated using sensing image data (PDATA1) and internal timing signals (Vsync2, Hsync2, DE2, CLK2). As a result, the embodiment of the present invention can control both the active period and the blank period of the frame period of the AGP mode as the sensing period driven in the first sensing mode. Accordingly, embodiments of the present invention can shorten the sensing time for external compensation.

Meanwhile, as will be described later in FIGS. 10, 11A, and 11B, in the first sensing mode, the organic light emitting diode of the pixel P does not emit light, and in the AGP mode, the active period (ACT) and blank period (VBI) of the frame period Since operates as a sensing period, the organic light emitting diode of each pixel P does not emit light.

Figure 8 is a waveform diagram showing the scan signal and sensing signal supplied to the pixel, the switch control signal supplied to the switch, and the gate voltage and source voltage of the driving transistor in the display mode.

Referring to FIG. 8, one frame period in the display mode may include a first period (t1) and a second period (t2). The first period (t1) is a period in which the emission data voltage (EVdata) is supplied to the gate electrode of the driving transistor (DT) and the source electrode is initialized to the reference voltage (VREF). The second period (t2) is a period in which the organic light emitting diode (OLED) emits light according to the current (Ids) of the driving transistor (DT). The first period (t1) may be one horizontal period. 1 horizontal period refers to the period during which data voltages are supplied to the pixels (P) of 1 horizontal line.

The first scan signal (SCAN1) of the kth scan line (Sk) and the first sensing signal (SENS1) of the kth sensing signal line (SEk) are supplied as a gate-on voltage (Von) during the first period (t1), It is supplied as a gate-off voltage (Voff) during the second period (t2). The first and second switching transistors ST1 and ST2 of the pixel P may be turned on by the gate-on voltage Von and turned off by the gate-off voltage Voff.

The first switch control signal SCS1 may be supplied as a first logic level voltage V1 during the first and second periods t1 and t2. The second switch control signal SCS2 may be supplied as a second logic level voltage V2 during the first and second periods t1 and t2. Each of the first and second switches SW1 and SW2 may be turned on by a first logic level voltage and turned off by a second logic level voltage.

9A and 9B are exemplary diagrams showing the operation of a pixel during first and second periods in a display mode. Below, the operation of the pixel P in the display mode will be examined in detail in conjunction with FIGS. 8, 9A, and 9B.

During the first and second periods (t1, t2) of the display mode, the first switch (SW1) is turned on by the first switch control signal (SCS1) of the first logic level voltage (V1), and the second switch (SW2) is turned off by the second switch control signal (SCS2) of the second logic level voltage (V2). For this reason, in the display mode, the reference voltage VREF is supplied from the voltage supply unit 80 to the u-th reference voltage line Ru.

First, as shown in FIG. 9A, during the first period t1, the first switching transistor ST1 is turned on by the first scan signal SCAN1 of the gate-on voltage Von supplied to the kth scan line Sk. -It comes on. During the first period t1, the second switching transistor ST2 is turned on by the first sensing signal SENS1 of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the first period t1, the light emission data voltage EVdata of the j-th data line Dj is supplied to the gate electrode of the driving transistor DT due to the turn-on of the first switching transistor ST1. During the first period t1, the reference voltage VREF of the u-th reference voltage line Ru is supplied to the source electrode of the driving transistor DT due to the turn-on of the second switching transistor ST2.

Second, as shown in FIG. 9B, during the second period t2, the first switching transistor ST1 is turned on by the first scan signal SCAN1 of the gate-off voltage Voff supplied to the kth scan line Sk. -It turns off. During the second period t2, the second switching transistor ST2 is turned off by the first sensing signal SENS1 of the gate-off voltage Voff supplied to the kth sensing signal line SEk.

During the second period t2, the current Ids according to the voltage difference between the gate voltage Vg and the source voltage Vs of the driving transistor DT flows to the organic light emitting diode (OLED). Because of this, the organic light emitting diode (OLED) emits light. Hereinafter, for convenience of explanation, “current (Ids) flowing through the driving transistor (DT) according to the voltage difference between the gate voltage (Vg) and source voltage (Vs) of the driving transistor (DT)” is referred to as “current of the driving transistor (DT).” (Ids)".

As described above, the embodiment of the present invention supplies the light emission data voltage (EVdata) to the pixel (P) in the display mode. The emission data voltage (EVdata) is a data voltage generated according to the compensated video data (CDATA) obtained by compensating the digital video data (DATA) after sensing the source voltage of the driving transistor (DT) in sensing mode. As a result, in the embodiment of the present invention, the organic light emitting diode (OLED) of the pixel (P) can emit light according to the current (Ids) of the driving transistor (DT) without depending on the threshold voltage of the driving transistor (DT). Accordingly, the embodiment of the present invention can increase the luminance uniformity of the pixels (P).

10 is a waveform showing the scan signal and sensing signal supplied to the pixel in the first sensing mode, the first and second switch control signals supplied to the first and second switches, and the gate voltage and source voltage of the driving transistor. It's a degree.

Referring to FIG. 10, in the first sensing mode, one frame period may include first and second periods t1" and t2". The first period (t1") is a period for initializing the source electrode of the driving transistor (DT) to the reference voltage (VREF). The second period (t2") is a period for initializing the first sensing data voltage to the gate electrode of the driving transistor (DT). This is the period during which (SVdata1) is applied and the source voltage of the driving transistor (DT) is sensed.

The second scan signal (SCAN2) of the kth scan line (Sk) is supplied as the gate-on voltage (Von) during the second period (t2"). In Figure 10, the second scan signal (SCAN2) of the kth scan line (Sk) Although SCAN2) is illustrated as being supplied with the gate-off voltage (Voff) during the first period (t1"), it may also be supplied with the gate-on voltage (Von). The second sensing signal SENS2 of the kth sensing signal line SEk is supplied as the gate-on voltage Von during the first and second periods t1" and t2". The first and second switching transistors ST1 and ST2 of the pixel P may be turned on by the gate-on voltage Von and turned off by the gate-off voltage Voff.

The first switch control signal SCS1 is supplied as a first logic level voltage V1 during a first period t1" and as a second logic level voltage V2 during a second period t2". The second switch control signal SCS2 is supplied as the second logic level voltage V2 during the first period t1" and is supplied as the first logic level voltage V1 during the second period t2". Each of the first and second switches SW1 and SW2 may be turned on by a first logic level voltage and turned off by a second logic level voltage.

FIGS. 11A and 11B are exemplary diagrams showing the operation of a pixel during first and second periods in the first sensing mode. Below, the operation of the pixel P in the first sensing mode will be examined in detail in conjunction with FIGS. 10, 11A, and 11B.

First, as shown in FIG. 11A, during the first period (t1"), the first switching transistor (ST1) is switched on by the second scan signal (SCAN2) of the gate-off voltage (Voff) supplied to the kth scan line (Sk). It is turned off, and the second switching transistor (ST2) is turned on by the second sensing signal (SENS2) of the gate-on voltage (Von) supplied to the k-th sensing signal line (SEk). The first period (t1) "), the first switch (SW1) is turned on by the first switch control signal (SCS1) of the first logic level voltage (V1), and the second switch (SW2) is turned on by the first switch control signal (SCS1) of the first logic level voltage (V2). It is turned off by the second switch control signal (SCS2).

During the first period (t1"), the reference voltage (VREF) is supplied to the u-th reference voltage line (Ru) from the voltage supply unit 80 due to the turn-on of the first switch (SW1). The first period (t1") ), the reference voltage (VREF) of the u-th reference voltage line (Ru) is supplied to the source electrode of the driving transistor (DT) due to the turn-on of the second switching transistor (ST2). That is, the source electrode of the driving transistor (DT) is initialized to the reference voltage (VREF).

Second, as shown in FIG. 11B, during the second period (t2"), the first switching transistor (ST1) is switched on by the second scan signal (SCAN2) of the gate-on voltage (Von) supplied to the kth scan line (Sk). Turned on, the second switching transistor ST2 is turned on by the second sensing signal SENS2 of the gate-on voltage Von supplied to the kth sensing signal line SEk. The second period t2 "), the first switch (SW1) is turned off by the first switch control signal (SCS1) of the second logic level voltage (V2), and the second switch (SW2) is turned on by the first switch control signal (SCS1) of the second logic level voltage (V1) It is turned on by the second switch control signal (SCS2).

Due to the turn-off of the first switch (SW1) during the second period (t2"), the reference voltage (VREF) is not supplied to the u-th reference voltage line (Ru). Also, during the second period (t2") 2 Due to the turn-on of the switch (SW2), the reference voltage line (Ru) is connected to the ADC (140). During the second period (t2"), the first sensing data voltage (SVdata1) is supplied to the gate electrode of the driving transistor (DT) due to the turn-on of the first switching transistor (ST1). During the second period (t2") Due to the turn-on of the second switching transistor (ST2), the source electrode of the driving transistor (DT) is connected to the ADC (140) through the u-th reference voltage line (Ru).

Since the voltage difference (Vgs=SVdata2-VREF) between the gate electrode and the source electrode of the driving transistor (DT) during the second period (t2") is greater than the threshold voltage (Vth) of the driving transistor (DT), the driving transistor (DT) causes current to flow. The second period (t2") in FIG. 10 is shorter than the second period (t2') in FIG. 7.

At this time, the current of the driving transistor DT can be defined as Equation 1.

In Equation 1, “Ids” is the current of the driving transistor (DT), “K” is the electron mobility, “Cox” is the capacitance of the insulating film, “W” is the channel width of the driving transistor (DT), and “L” is This refers to the channel length of the driving transistor (DT).

Since the current of the driving transistor (DT) is proportional to the electron mobility (K) of the driving transistor (DT) as shown in Equation 1, the increase in the source voltage (Vs) of the driving transistor (DT) during the second period (t2") is proportional to the electron mobility (K) of the driving transistor (DT). That is, the greater the electron mobility of the driving transistor (DT), the higher the source voltage (Vs) of the driving transistor (DT) during the second period (t2"). The amount of rise becomes even greater.

Ultimately, the amount of increase in the source voltage (Vs) of the driving transistor (DT) varies depending on the electron mobility (K) of the driving transistor (DT) during the second period (t2"). In FIG. 9, the electron mobility (K) The amount of increase in the source voltage (Vs) according to During (t2"), a voltage reflecting the electron mobility (K) of the driving transistor (DT) is sensed at the source electrode of the driving transistor (DT).

Meanwhile, even if the source voltage of the driving transistor DT rises to “VREF+α”, “VREF+α” is lower than the threshold voltage of the organic light emitting diode (OLED), so the organic light emitting diode (OLED) does not emit light.

As described above, the embodiment of the present invention can sense the source voltage “VREF+α” of the driving transistor reflecting the electron mobility (K) of the driving transistor DT in the first sensing mode.

12 is a waveform showing the scan signal and sensing signal supplied to the pixel in the second sensing mode, the first and second switch control signals supplied to the first and second switches, and the gate voltage and source voltage of the driving transistor. It's a degree.

Referring to FIG. 12, in the second sensing mode, one frame period may include first to third periods (t1' to t3'). The first period (t1') is a period for initializing the source electrode of the driving transistor (DT) to the reference voltage (VREF). The second period t2' is a period during which the second sensing data voltage SVdata2 is supplied to the gate electrode of the driving transistor DT. The third period t3' is a period for sensing the source voltage of the driving transistor DT.

The third scan signal SCAN3 of the kth scan line Sk is supplied as the gate-on voltage Von during the second and third periods t2' and t3'. 12 illustrates that the third scan signal SCAN3 of the kth scan line Sk is supplied as the gate-off voltage Voff during the first period t1', but it may also be supplied as the gate-on voltage Von. there is. The third sensing signal SENS3 of the kth sensing signal line SEk is supplied as the gate-on voltage Von during the first to third periods t1' to t3'. The first and second switching transistors ST1 and ST2 of the pixel P may be turned on by the gate-on voltage Von and turned off by the gate-off voltage Voff.

The first switch control signal (SCS1) is supplied as a first logic level voltage (V1) during the first period (t1'), and is supplied as a second logic level voltage (V1) during the second and third periods (t2' and t3') V2) is supplied. The second switch control signal SCS2 is supplied as a second logic level voltage V2 during the first and second periods t1' and t2', and is supplied as a first logic level voltage V2 during the third period t3'. It is supplied to V1). Each of the first and second switches SW1 and SW2 may be turned on by a first logic level voltage and turned off by a second logic level voltage.

FIGS. 13A to 13C are exemplary diagrams showing the operation of a pixel during first to third periods in a second sensing mode. Hereinafter, the operation of the pixel P in the second sensing mode will be examined in detail in conjunction with FIGS. 12 and 13A to 13C.

First, as shown in FIG. 13A, during the first period t1', the first switching transistor ST1 is switched on by the third scan signal SCAN3 of the gate-off voltage Voff supplied to the kth scan line Sk. It is turned off, and the second switching transistor (ST2) is turned on by the third sensing signal (SENS3) of the gate-on voltage (Von) supplied to the k-th sensing signal line (SEk). During the first period t1', the first switch SW1 is turned on by the first switch control signal SCS1 of the first logic level voltage V1, and the second switch SW2 is turned on at the second logic level voltage V1. It is turned off by the second switch control signal (SCS2) of the voltage (V2).

Due to the turn-on of the first switch SW1 during the first period t1', the reference voltage VREF is supplied from the voltage supply unit 80 to the u-th reference voltage line Ru. During the first period t1', the reference voltage VREF of the u-th reference voltage line Ru is supplied to the source electrode of the driving transistor DT due to the turn-on of the second switching transistor ST2. That is, the source electrode of the driving transistor (DT) is initialized to the reference voltage (VREF).

Second, as shown in FIG. 13B, during the second period t2', the first switching transistor ST1 is switched on by the third scan signal SCAN3 of the gate-on voltage Von supplied to the kth scan line Sk. It is turned on, and the second switching transistor (ST2) is turned on by the third sensing signal (SENS3) of the gate-on voltage (Von) supplied to the k-th sensing signal line (SEk). During the second period t2', the first switch SW1 is turned off by the second switch control signal SCS2 of the second logic level voltage V2, and the second switch SW2 is turned off at the second logic level voltage V2. It is turned off by the second switch control signal (SCS2) of the voltage (V2).

During the second period t2', the reference voltage VREF is not supplied to the u-th reference voltage line Ru due to the turn-off of the first switch SW1. Additionally, since the first switching transistor ST1 is turned on during the second period t2', the second sensing data voltage SVdata2 is supplied to the gate electrode of the driving transistor DT.

Since the voltage difference (Vgs=SVdata1-VREF) between the gate electrode and the source electrode of the driving transistor (DT) during the second period (t2') is greater than the threshold voltage (Vth) of the driving transistor (DT), the driving transistor (DT) flows current until the voltage difference (Vgs) between the gate electrode and the source electrode reaches the threshold voltage (Vth). Because of this, the source voltage of the driving transistor DT rises to “SVdata1-Vth” as shown in FIG. 12. That is, the threshold voltage of the driving transistor DT is sensed by the source electrode of the driving transistor DT during the second period t2'.

Third, as shown in FIG. 13C, during the third period t3', the first switching transistor ST1 is switched on by the third scan signal SCANk of the gate-on voltage Von supplied to the kth scan line Sk. It is turned on, and the second switching transistor (ST2) is turned on by the third sensing signal (SENS3) of the gate-on voltage (Von) supplied to the k-th sensing signal line (SEk). During the third period t3', the first switch SW1 is turned off by the second switch control signal SCS2 of the second logic level voltage V2, and the second switch SW2 is turned off at the first logic level voltage V2. It is turned on by the second switch control signal (SCS2) of the voltage (V1).

During the third period t3', the u-th reference voltage line Ru is connected to the ADC 140 due to the turn-on of the second switch SW2. Due to the turn-on of the second switching transistor ST2 during the third period t3', the source electrode of the driving transistor DT is connected to the ADC 140 through the u-th reference voltage line Ru. Accordingly, the ADC 140 can sense the source voltage of the driving transistor DT, that is, “SVdata1-Vth”.

As discussed above, the embodiment of the present invention can sense the source voltage “SVdata1-Vth” of the driving transistor (DT) reflecting the threshold voltage of the driving transistor (DT) in the second sensing mode.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

10: display panel 20: data driver
21: source drive IC 22: flexible film
40: Scan driving unit 41: Scan signal output unit
42: Sensing signal output unit 50: Source circuit board
60: timing controller 80: voltage supply unit
90: Control circuit board 91: Flexible cable
120: data voltage supply unit 130: sensing unit
140: analog digital converter 161: input signal processing unit
162: Internal timing signal generation unit 163: Data compensation unit
164: data control signal generator 165: scan control signal generator
166: Sensing control signal generator

Claims (11)

a display panel connected to a data line, a scan line, and a reference voltage line, and provided with pixels including organic light emitting diodes;
a scan signal output unit that supplies a scan signal to the scan line;
a data voltage supply unit that supplies a data voltage to the data line; and
A timing control unit that controls the scan signal output unit and the data voltage supply unit in a normal mode or an automatically generated pattern mode according to a data enable signal input from an external source,
The scan signal output unit outputs a second scan signal to the scan line in both the active period and blank period of the frame period in the automatically generated pattern mode,
The data voltage supply unit generates a first sensing data voltage according to first sensing image data in both the active period and the blank period of the frame period in the automatic generation pattern mode and supplies the first sensing data voltage to the data line. Luminous display device. According to claim 1,
The data voltage supply unit generates an emission data voltage according to compensation image data in the active period of the frame period in the normal mode and supplies it to the data line, and supplies the first emission data voltage according to the first sensed image data in the blank period. An organic light emitting display device characterized in that it generates a sensing data voltage and supplies it to the data line. According to claim 1,
The scan signal output unit,
In the normal mode, outputting a first scan signal to the scan line in the active period of the frame period and outputting the second scan signal to the scan line in the blank period,
An organic light emitting display device, characterized in that the second scan signal is output to the scan line in both the active period and the blank period of the frame period in the automatically generated pattern mode. According to claim 1,
In the automatically generated pattern mode, sensing a predetermined voltage from the pixel through the reference voltage line in both the active period and the blank period of the frame period and then outputting the sensed voltage as first sensing data, which is digital data. An organic light emitting display device further comprising: According to claim 4,
The sensing unit supplies a reference voltage to the reference voltage line during the active period of the frame period in the normal mode, and senses the predetermined voltage from the pixel through the reference voltage line during the blank period of the frame period. An organic light emitting display device characterized in that the sensed voltage is then output as the first sensing data. According to claim 1,
An organic light emitting display device, wherein the organic light emitting diode does not emit light in the automatically generated pattern mode. According to claim 1,
The timing control unit,
If the count value counted by counting the pulses of the data enable signal is equal to the set value, the data enable signal is determined to be normal, and if the count value is different from the set value, the data enable signal is determined to be abnormal. And
a scan signal output unit that supplies a scan signal to the scan line;
a data voltage supply unit that supplies a data voltage to the data line; and
When the data enable signal is normal, the scan signal output unit and the data voltage supply unit are controlled to the normal mode, and when the data enable signal is abnormal, the scan signal output unit and the data voltage supply unit are controlled to the automatically generated pattern. An organic light emitting display device characterized by control by mode. Controlling the normal mode or automatically generated pattern mode according to a data enable signal input from an external source;
supplying a first scan signal to a scan line of a display panel and supplying an emission data voltage to a data line of the display panel during an active period of a frame period in the normal mode;
Supplying a second scan signal to the scan line and supplying a first sensing data voltage to the data line during a blank period of the frame period in the normal mode; and
In the automatically generated pattern mode, supplying the second scan signal to the scan line and supplying the first sensing data voltage to the data line during both the active period and the blank period of the frame period. How to drive a light emitting display device. According to claim 8,
supplying a reference voltage to a reference voltage line of the display panel during the active period of the frame period in the normal mode; and
Driving an organic light emitting display device further comprising sensing a predetermined voltage from a pixel through the reference voltage line during the blank period of the frame period in the normal mode and then outputting the sensed voltage as sensing data, which is digital data. method. According to claim 8,
Sensing a predetermined voltage from a pixel through a reference voltage line of the display panel in both the active period and the blank period of the frame period in the automatically generated pattern mode, and then outputting the sensed voltage as sensing data, which is digital data. A method of driving an organic light emitting display device further comprising: According to claim 8,
The step of controlling to the normal mode or the automatically generated pattern mode according to the data enable signal,
A method of driving an organic light emitting display device, characterized in that controlling in the normal mode when the data enable signal is determined to be normal, and controlling in the automatically generated pattern mode when it is determined that the data enable signal is abnormal.

Images