CN116248052B - Low noise amplifier and radio frequency chip - Google Patents
Low noise amplifier and radio frequency chipInfo
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- CN116248052B CN116248052B CN202310216385.4A CN202310216385A CN116248052B CN 116248052 B CN116248052 B CN 116248052B CN 202310216385 A CN202310216385 A CN 202310216385A CN 116248052 B CN116248052 B CN 116248052B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a low-noise amplifier and a radio frequency chip, wherein the low-noise amplifier comprises a signal input end, a cascode low-noise amplifying link with an active level negative feedback inductance, an output matching network, an output resistor attenuation network, a signal output end, a first switch, a third switch, a fourth switch, a bypass matching circuit, a transistor bias access circuit and a control logic circuit, the output matching network comprises a first output matching circuit and a second output matching circuit, the cascode low-noise amplifying link comprises a first inductance, a second switch, a first capacitor, a first transistor, a second inductance and a third inductance, and the control logic circuit is used for respectively controlling the switching actions of the transistor bias access circuit, the first switch, the second switch, the third switch and the fourth switch. Compared with the related art, the mode function of the technical scheme is various, the out-of-band narrowband suppression of the single frequency band is effectively realized, the anti-interference capability is high, and the sensitivity is high.
Description
Technical Field
The present invention relates to the field of amplifier circuits, and in particular, to a low noise amplifier and a radio frequency chip.
Background
With the advent of the information age, wireless communication technology has been rapidly developed, and from cellular phones, wireless local area networks, bluetooth, etc., have become an integral part of social life and development. The progress of wireless communication technology has not been separated from the development of radio frequency circuits. In a wireless transceiver system, a low noise amplifier of radio frequency is one of important components, and after the low noise amplifier amplifies power of a signal to obtain enough radio frequency power, the signal can be fed to an antenna to radiate. The gain and return loss of the low noise amplifier are important performance indexes.
The related art low noise amplifier generally includes an input matching circuit, a cascode amplifier, and an output matching circuit. The low-noise amplifier processes the power signal input by the input matching circuit through the common-gate common-source amplifier and then outputs the power signal through the output matching circuit, thereby realizing the function of low noise.
However, the low noise amplifier of the related art amplifies a signal by a cascode amplifier, outputs a fixed low noise power signal, has a single function, and has poor reliability. In addition, the receiving path of the low-noise amplifier can be simultaneously applied to the 5GHz WiFi frequency band and the 2.4GHz WiFi frequency band, but when the receiving path of the 5GHz WiFi frequency band is applied, the low-noise amplifier in the related art cannot perform channel suppression on the 2.4GHz WiFi frequency band, so that the anti-interference capability of a receiving link is poor, and the sensitivity of a downlink in communication is low.
Therefore, it is necessary to provide a new low noise amplifier and radio frequency chip to solve the above problems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the low-noise amplifier and the radio frequency chip which have various mode functions, high anti-interference capability and high sensitivity and effectively realize out-of-band narrowband suppression of an independent frequency band.
In order to solve the technical problem, in a first aspect, an embodiment of the present invention provides a low noise amplifier, which includes a signal input terminal, a cascode low noise amplifying link including an active stage negative feedback inductance, an output matching network, an output resistor attenuation network, and a signal output terminal connected in sequence,
The low-noise amplifier further comprises a first switch, a third switch, a fourth switch, a bypass matching circuit and a transistor bias access circuit, wherein the output matching network comprises a first output matching circuit for realizing filtering of an individual frequency band and a second output matching circuit for converting output impedance to preset target output impedance;
the second end of the first inductor is respectively connected to the first end of the first switch and the first end of the second switch;
The second end of the first switch is connected to the input end of the bypass matching circuit and the first end of the fourth switch respectively;
the second end of the third switch is respectively connected to the output end of the first output matching circuit and the input end of the second output matching circuit;
A second end of the second switch is connected to a first end of the first capacitor; a second end of the first capacitor is connected to the grid electrode of the first transistor;
The source electrode of the first transistor is connected to the first end of the second inductor, the second end of the second inductor is connected to the first end of the transistor bias access circuit, the second end of the transistor bias access circuit is grounded, the third end of the transistor bias access circuit is used for being connected to an external control logic circuit, and the control logic circuit is used for respectively controlling actions of the transistor bias access circuit, the first switch, the second switch, the third switch and the fourth switch;
The drain electrode of the first transistor is connected to the source electrode of the second transistor, and the grid electrode of the second transistor is grounded;
The drain electrode of the second transistor is respectively connected to the input end of the first output matching circuit and the first end of the third inductor;
The output end of the second output matching circuit is connected to the first end of the output resistor attenuation network, the second end of the output resistor attenuation network is connected to the signal output end, and the third end of the output resistor attenuation network is grounded.
Preferably, the low noise amplifier further comprises a third capacitor, a first end of the third capacitor is connected to the gate of the second transistor, and a second end of the third capacitor is grounded.
Preferably, the low noise amplifier further comprises a second resistor, a first end of the second resistor is connected to the gate of the second transistor, and a second end of the second resistor is used for being connected to a second bias voltage.
Preferably, the low noise amplifier further comprises a first resistor, a first end of the first resistor is connected to the gate of the first transistor, and a second end of the first resistor is used for being connected to a first bias voltage.
Preferably, the bypass matching circuit comprises a second capacitor, wherein a first end of the second capacitor is used as an input end of the bypass matching circuit, and a second end of the second capacitor is used as an output end of the bypass matching circuit.
Preferably, the first output matching circuit comprises a third resistor, a fifth capacitor, a sixth capacitor, a fifth switch, a sixth switch and a seventh switch, and the second output matching circuit comprises a seventh capacitor, an eighth switch and a ninth switch;
The first end of the fifth capacitor is used as an input end of the first output matching circuit, and the first end of the fifth capacitor is respectively connected to the first end of the third resistor, the first end of the sixth capacitor and the first end of the eighth capacitor; the second end of the third resistor is connected with the first end of the fifth switch, and the second end of the fifth switch is grounded; the second end of the sixth capacitor is connected with the first end of the sixth switch, and the second end of the sixth switch is grounded;
A second end of the fifth capacitor is connected to a second end of the seventh switch; the first end of the seventh switch is used as the output end of the first output matching circuit, and the first end of the seventh switch is connected to the first end of the seventh capacitor;
The second end of the eighth switch is used as the output end of the second output matching circuit, and the second end of the eighth switch is connected to the first end of the ninth switch;
a second terminal of the ninth switch is connected to a second terminal of the eighth capacitor.
Preferably, the output resistor attenuation network includes a tenth switch, an eleventh switch, a twelfth switch, a ninth capacitor, a fourth resistor, a fifth resistor, and a sixth resistor;
the first end of the fourth resistor is used as the first end of the output resistor attenuation network, and the first end of the fourth resistor is respectively connected to the first end of the twelfth switch and the first end of the ninth capacitor;
the second end of the ninth capacitor is connected to the first end of the tenth switch;
The second end of the fourth resistor is connected to the first end of the fifth resistor and the first end of the sixth resistor respectively;
A second end of the fifth resistor is used as a second end of the output resistor attenuation network, and the second end of the fifth resistor is connected to a second end of the twelfth switch;
A second terminal of the sixth resistor is connected to a first terminal of the eleventh switch;
The second terminal of the eleventh switch is used as a third terminal of the output resistor attenuation network, and the second terminal of the eleventh switch is grounded.
Preferably, the transistor bias access circuit comprises a third transistor, wherein the source electrode of the third transistor is used as the second end of the transistor bias access circuit, the drain electrode of the third transistor is used as the first end of the transistor bias access circuit, and the grid electrode of the third transistor is used as the third end of the transistor bias access circuit.
Preferably, the first transistor, the second transistor and the third transistor are all NMOS transistors.
In a second aspect, embodiments of the present invention further provide a radio frequency chip, where the radio frequency chip includes a low noise amplifier as provided in the embodiments of the present invention.
Compared with the related art, the low-noise amplifier and the radio frequency chip realize a plurality of bypass mode functions and amplification mode functions by arranging the cascode low-noise amplifying link with the source-level negative feedback inductor, the first switch, the second switch, the third switch, the fourth switch, the transistor bias access circuit and the bypass matching circuit, connecting the bypass matching circuit at two ends of the cascode low-noise amplifying link, and controlling the on-off of the bypass matching circuit through the on-off actions of the transistor bias access circuit, the first switch, the second switch, the third switch and the fourth switch, so that the return loss of the working frequency of the low-noise amplifier is smaller and the reliability is high. In addition, the low-noise amplifier and the radio frequency chip are provided with the first output matching circuit for filtering the single frequency band and the second output matching circuit for converting the output impedance to the preset target output impedance, and the first output matching circuit generates a low impedance point at a low frequency, so that the filtering of the single frequency band is realized, for example, the channel inhibition of the 2.4GHz WiFi frequency band is realized in a receiving path of the 5GHz WiFi, and the out-of-band narrow-band inhibition of the single frequency band is effectively realized. More preferably, in the working frequency band, after the signals sequentially pass through the first output matching circuit and the second output matching circuit, the output impedance is converted to a preset target output impedance, so that the low-noise amplifier and the radio frequency chip reduce the return loss, and the low-noise amplifier and the radio frequency chip have strong anti-interference capability and high sensitivity.
Drawings
The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description taken in conjunction with the accompanying drawings. In the drawings of which there are shown,
Fig. 1 is a circuit block diagram of a low noise amplifier according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a low noise amplifier according to an embodiment of the present invention;
FIG. 3 is an equivalent circuit diagram of a bypass mode of a low noise amplifier according to an embodiment of the present invention;
FIG. 4 is a graph of S21 versus frequency for a bypass mode of a low noise amplifier of the related art;
Fig. 5 is a graph of S21 versus frequency for a bypass mode of a low noise amplifier according to an embodiment of the invention.
Detailed Description
The following describes in detail the embodiments of the present invention with reference to the drawings.
The detailed description/examples set forth herein are specific embodiments of the application and are intended to be illustrative and exemplary of the concepts of the application and are not to be construed as limiting the scope of the application. In addition to the embodiments described herein, those skilled in the art will be able to adopt other obvious solutions based on the disclosure of the claims and specification, including any obvious alterations and modifications to the embodiments described herein, all within the scope of the present application.
The present invention provides a low noise amplifier 100.
Referring to fig. 1 to 2, fig. 1 is a circuit block diagram of a low noise amplifier 100 according to an embodiment of the invention, and fig. 2 is a circuit schematic diagram of the low noise amplifier 100 according to an embodiment of the invention.
Specifically, the low noise amplifier 100 includes a signal input terminal RFin, a cascode low noise amplifying link 1 including a source stage negative feedback inductor, an output matching network 4, an output resistor attenuation network 5, and a signal output terminal RFout, which are sequentially connected.
The low noise amplifier 100 further includes a first switch S1, a third switch S3, a fourth switch S4, a bypass matching circuit 2, and a transistor bias access circuit 3 control logic circuit.
The cascode low-noise amplification link 1 includes a first inductor L1, a second switch S2, a first capacitor C1, a first transistor M1, a second transistor M2, a second inductor L2, and a third inductor L3. Wherein, the first inductance L1 and the second inductance L2 are commonly used in the art. The third inductor L3 is a radio frequency choke inductor, and is configured to provide a dc operating point. The first transistor M1 is a common-source amplifier, and the second transistor M2 is a common-gate amplifier. The first capacitor C1 is a blocking capacitor, and is used for isolating direct current from passing through.
In this embodiment, the first transistor M1 and the second transistor M2 are both NMOS transistors. Of course, the first transistor M1 and the second transistor M2 may be PMOS transistors, and the corresponding circuit structure may be modified correspondingly according to the circuit of the PMOS transistors, specifically, the circuit structure may be adjusted according to the design requirement, which is not described in detail herein.
The bypass matching circuit 2 comprises a second capacitor C2. The first end of the second capacitor C2 is used as the input end of the bypass matching circuit 2. The second end of the second capacitor C2 is used as the output end of the bypass matching circuit 2.
The transistor bias access circuit 3 comprises a third transistor M3. The source of the third transistor M3 serves as a second terminal of the transistor bias access circuit 3. The drain of the third transistor M3 serves as a first terminal of the transistor bias access circuit 3. The gate of the third transistor M3 is used as the third terminal of the transistor bias access circuit 3, and the third terminal of the transistor bias access circuit 3 is used for being connected to an external control logic circuit, and the control logic circuit is used for controlling the actions of the transistor bias access circuit 3, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 respectively.
In this embodiment, the third transistor M3 is an NMOS transistor.
The control logic circuit is configured to control on or off switching actions of the transistor bias access circuit 3, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, respectively. The control logic circuit is a digital logic circuit, and the specific circuit is designed and generated according to the design requirement, and the process adopts the prior art without improvement on circuit algorithm or method and improvement on software. Of course, the control logic circuit is not limited thereto and may also be implemented using a processor. In other embodiments, the low noise amplifier 100 is connected to the control logic circuit and fabricated as a module circuit.
The output matching network 4 comprises a first output matching circuit 41 for implementing filtering of the individual frequency bands and a second output matching circuit 42 for converting the output impedance to a preset target output impedance.
Specifically, the first output matching circuit 41 includes a third resistor R3, a fifth capacitor C5, a sixth capacitor C6, a fifth switch S5, a sixth switch S6, and a seventh switch S7. The second output matching circuit 42 includes a seventh capacitor C7, an eighth capacitor C8, an eighth switch S8, and a ninth switch S9. The control logic circuit is further configured to control on or off switching actions of the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8, and the ninth switch S9, respectively.
The connection relation of the internal circuits of the output matching network 4 is as follows:
The first end of the fifth capacitor C5 is used as the input end of the first output matching circuit 41, and the first end of the fifth capacitor C5 is connected to the first end of the third resistor R3, the first end of the sixth capacitor C6, and the first end of the eighth capacitor C8, respectively. The second end of the third resistor R3 is connected to the first end of the fifth switch S5, and the second end of the fifth switch S5 is grounded to GND. The second end of the sixth capacitor C6 is connected to the first end of the sixth switch S6, and the second end of the sixth switch S6 is grounded GND.
A second terminal of the fifth capacitor C5 is connected to a second terminal of the seventh switch S7. A first terminal of the seventh switch S7 serves as an output terminal of the first output matching circuit 41, and the first terminal of the seventh switch S7 is connected to the first terminal of the seventh capacitor C7. The first end of the seventh capacitor C7 is used as the input end of the second output matching circuit 42.
A second terminal of the seventh capacitor C7 is connected to a first terminal of the eighth switch S8. A second terminal of the eighth switch S8 serves as an output terminal of the second output matching circuit 42, and the second terminal of the eighth switch S8 is connected to the first terminal of the ninth switch S9.
A second terminal of the ninth switch S9 is connected to a second terminal of the eighth capacitor C8.
In this embodiment, the first output matching circuit 41, the second output matching circuit 42, and the third switch S3 are interconnected so that nodes are connected in a Y-shape. Of course, without being limited thereto, in another embodiment, the first output matching circuit 41, the second output matching circuit 42, and the third switch S3 are interconnected such that the nodes are delta-connected, i.e., the first output matching circuit 41 and the second output matching circuit 42 may be together in another embodiment.
The output resistor attenuation network 5 includes a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a ninth capacitor C9, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The eleventh switch S11, the twelfth switch S12, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 form a resistor attenuation network for realizing a resistor attenuation function. Wherein the tenth switch S10 and the twelfth switch S12 are turned on in the amplifying mode and turned off in the bypass mode, and the eleventh switch S11 is turned off in the amplifying mode and turned on in the bypass mode. The control logic circuit is further configured to control on or off switching actions of the tenth switch S10, the eleventh switch S11, and the twelfth switch S12, respectively.
The connection relation of the internal circuits of the output resistor attenuation network 5 is as follows:
The first end of the fourth resistor R4 is used as the first end of the output resistor attenuation network 5, and the first end of the fourth resistor R4 is connected to the first end of the twelfth switch S12 and the first end of the ninth capacitor C9, respectively.
A second terminal of the ninth capacitor C9 is connected to a first terminal of the tenth switch S10. The second terminal of the tenth switch S10 is grounded GND.
The second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5 and the first end of the sixth resistor R6, respectively.
A second terminal of the fifth resistor R5 serves as a second terminal of the output resistor attenuation network 5, and the second terminal of the fifth resistor R5 is connected to the second terminal of the twelfth switch S12.
A second terminal of the sixth resistor R6 is connected to a first terminal of the eleventh switch S11.
A second terminal of the eleventh switch S11 serves as a third terminal of the output resistor attenuation network 5, and a second terminal of the eleventh switch S11 is grounded GND.
The circuit connection relationship of the low noise amplifier 100 is as follows:
The signal input terminal RFin is connected to a first terminal of the first inductance L1. The second end of the first inductor L1 is connected to the first end of the first switch S1 and the first end of the second switch S2, respectively.
The second terminal of the first switch S1 is connected to the input terminal of the bypass matching circuit 2 and the first terminal of the fourth switch S4, respectively. The second terminal of the fourth switch S4 is grounded GND.
An output terminal of the bypass matching circuit 2 is connected to a first terminal of the third switch S3. The second terminal of the third switch S3 is connected to the output terminal of the first output matching circuit 41 and the input terminal of the second output matching circuit 42, respectively.
A second terminal of the second switch S2 is connected to a first terminal of the first capacitor C1. The second end of the first capacitor C1 is connected to the gate of the first transistor M1.
The source of the first transistor M1 is connected to the first end of the second inductor L2. A second terminal of the second inductance L2 is connected to a first terminal of the transistor bias access circuit 3. The transistor biases the second terminal of the access circuit 3 to ground GND. The third terminal of the transistor bias access circuit 3 is for connection to an output of an external control logic circuit.
The drain of the first transistor M1 is connected to the source of the second transistor M2. The gate of the second transistor M2 is grounded GND.
The drain of the second transistor M2 is connected to the input of the first output matching circuit 41 and the first end of the third inductance L3, respectively. The second end of the third inductor L3 is configured to be connected to the power supply voltage VDD.
An output of the second output matching circuit 42 is connected to a first end of the output resistor attenuation network 5. A second terminal of the output resistor attenuation network 5 is connected to the signal output terminal RFout. The third end of the output resistor attenuation network 5 is grounded GND.
In this embodiment, the low noise amplifier 100 further includes a third capacitor C3. The first end of the third capacitor C3 is connected to the gate of the second transistor M2. The second end of the third capacitor C3 is grounded GND. The third capacitor C3 makes the gate of the second transistor M2 implement blocking, so that the second transistor M2 operates stably.
In this embodiment, the low noise amplifier 100 further includes a first resistor R1. A first end of the first resistor R1 is connected to the gate of the first transistor M1. The second end of the first resistor R1 is configured to be connected to a first bias voltage Vb1. The first resistor R1 is connected to the first bias voltage Vb1, so that the first bias voltage Vb1 is output to the gate of the first transistor M1 after being reduced by the first resistor R1, and the overall circuit stability is high.
In this embodiment, the low noise amplifier 100 further includes a second resistor R2. The first end of the second resistor R2 is connected to the gate of the second transistor M2. The second end of the second resistor R2 is for connection to a second bias voltage Vb2. The second resistor R2 is connected to the second bias voltage Vb2, so that the second bias voltage Vb2 is output to the gate of the second transistor M2 after being reduced by the second resistor R2, and the overall circuit stability is high.
The working principle of the low noise amplifier 100 is as follows:
The radio frequency signal input by the signal input terminal RFin enters through the first inductor L1, the first switch S1 and the third switch S3 are turned off when the low noise amplifier 100 operates in the amplifying mode, the second switch S2 and the fourth switch S4 are turned on, the gate of the third transistor M3 is set to a high level to enable the common-source common-gate amplifier of the common-source common-gate low noise amplifying link 1 to normally operate, the signal is input to the first transistor M1 serving as a common-source amplifying tube through the first capacitor C1 serving as a blocking capacitor, and the signal is amplified by the first transistor M1 and then amplified by the second transistor M2 serving as a common-gate amplifying tube and then output. The third inductor L3, which is a radio frequency choke inductor, provides a dc operating point and forces the radio frequency signal into the first output matching circuit 41 and the second output matching circuit 42, and finally to the signal output RFout via the output resistor attenuation network 5.
When the low noise amplifier 100 operates in the bypass mode, the first switch S1 and the third switch S3 are turned on, the second switch S2 and the fourth switch S4 are turned off, the gate of the third transistor M3 is set to a low level, and the cascode circuit of the cascode low noise amplifier link 1 is turned off, and the parasitic capacitance to ground after the first inductor L1 is reduced. The radio frequency signal is input into the bypass matching circuit 2 through the first inductor L1, after being subjected to bypass matching by the bypass matching circuit 2, the first output matching circuit 41 resonates with the third inductor L3 in a bypass mode, so that a low impedance point is generated at a low frequency, filtering of an independent frequency band is achieved, for example, a receiving channel of 5GHz WiFi performs channel suppression on a 2.4GHz WiFi frequency band, in an operating frequency band, a series structure of the first output matching circuit 41 and the third inductor L3 can be equivalent to an inductor to ground, and finally, after passing through the second output matching circuit 42, the output impedance is converted to a preset target output impedance, so that return loss can be reduced, and finally, the signal is sequentially output through the output resistor attenuation network 5 and the signal output end RFout.
Referring to fig. 3, fig. 3 is an equivalent circuit diagram of a bypass mode of the low noise amplifier 100 according to an embodiment of the invention. The branch circuit formed by the fifth capacitor C5 and the third inductor L3 presents low impedance in the suppression frequency band and presents inductive impedance in the working frequency band, so that a bypass path for suppressing a fixed low frequency point and conducting the working frequency band can be obtained.
Specifically, when the low noise amplifier 100 operates in the amplifying mode, the first switch S1, the third switch S3, the seventh switch S7, the eighth switch S8, and the eleventh switch S11 are all turned off, and the second switch S2, the fourth switch S4, the fifth switch S5, the sixth switch S6, the ninth switch S9, the tenth switch S10, and the twelfth switch S12 are all turned on, and the first bias voltage Vb1 and the second bias voltage Vb2 normally output to provide the correct bias voltages for the first transistor M1 and the second transistor M2, and the gate of the third transistor M3 is set to a high level to normally operate the first transistor M1 and the second transistor M2. The radio frequency signal reaches the grid electrode of the first transistor M1 through the first inductor L1 and the first capacitor C1, is amplified by the first transistor M1 serving as a common source amplifying tube, is amplified by the second transistor M2 serving as a common gate amplifying tube again, serves as a source negative feedback inductor, serves as a part of input matching to provide a real part of input impedance, and forms output matching together with the third inductor L3, the third resistor R3, the sixth capacitor C6, the seventh capacitor C7 and the ninth capacitor C9 serving as radio frequency choke inductors, and transmits the signal from the drain electrode of the second transistor M2 to the signal output end RFout.
When the low noise amplifier 100 operates in the bypass mode, the first switch S1, the third switch S3, the seventh switch S7, the eighth switch S8 and the eleventh switch S11 are all turned on, the second switch S2, the fourth switch S4, the fifth switch S5, the sixth switch S6, the ninth switch S9, the tenth switch S10 and the twelfth switch S12 are all turned off, the first bias voltage Vb1 and the second bias voltage Vb2 are set at low level, the gate of the third transistor M3 is set at low level to turn off the cascode low noise amplifying link 1, at this time, the first transistor M1 and the second transistor M2 enter the cut-off region, the input signal sequentially reaches the intermediate node of the seventh switch S7 and the seventh capacitor C7 via the first inductor L1 and the second capacitor C2, the fifth capacitor C5 and the third inductor L3 together form an LC series resonant branch, the resonant frequency is set at a frequency band outside the band, the inductive equivalent is exhibited in the band, and finally the input signal is output to the RFout via the seventh capacitor C7.
In order to verify the performance of the bypass mode of the low noise amplifier 100, verification is performed by performing simulation comparison with the performance of the bypass mode of the low noise amplifier of the related art. As a result of the simulation, please refer to fig. 4 to 5, fig. 4 is a graph of S21 versus frequency for the bypass mode of the low noise amplifier of the related art, and fig. 5 is a graph of S21 versus frequency for the bypass mode of the low noise amplifier 100 of the embodiment of the invention. S21 is insertion loss in dB.
The graph in fig. 4 is an insertion loss curve of the related art low noise amplifier configured in the bypass mode at 5-6GHz, and the value of the A1 point is 2.45GHz, -20.0452dB. The value at point A2 is 5.5GHZ, -2.30987dB. As can be seen from fig. 4, the passband attenuation of the low noise amplifier of the related art is between about 2.3 dB and about 2.7dB, and the attenuation for the 2.4 GHz band and 2.5GHz band is about 20dB.
The graph in fig. 5 is the insertion loss curve of the low noise amplifier of the present invention in the bypass mode operation at 5-6GHz, with the value at point A3 being 2.45GHz, -35.8599dB. The value at point A4 is 5.5GHZ, -2.75073dB. As can be obtained from FIG. 5, the passband attenuation is about 2.7-3.4dB, and the attenuation of the 2.4-2.5GHz frequency band is about 35dB, so that the low-noise amplifier of the invention provides an extra 15dB out-of-band interference suppression capability on the basis of the low-noise amplifier of the related technology, and the anti-interference capability can be greatly improved, and the sensitivity is high.
The embodiment of the invention also provides a radio frequency chip. The radio frequency chip comprises the low noise amplifier 100.
The radio frequency chip provided by the embodiment of the present invention can implement each implementation manner and corresponding beneficial effects in the embodiment of the low noise amplifier 100, and in order to avoid repetition, the description is omitted here.
It should be noted that, the related circuit modules, resistors, capacitors, inductors and transistors adopted in the present invention are all commonly used in the art, and the corresponding specific indexes and parameters are adjusted according to practical applications, so detailed descriptions are omitted herein.
Compared with the related art, the low-noise amplifier and the radio frequency chip realize a plurality of bypass mode functions and amplification mode functions by arranging the cascode low-noise amplifying link with the source-level negative feedback inductor, the first switch, the second switch, the third switch, the fourth switch, the transistor bias access circuit and the bypass matching circuit, connecting the bypass matching circuit at two ends of the cascode low-noise amplifying link, and controlling the on-off of the bypass matching circuit through the on-off actions of the transistor bias access circuit, the first switch, the second switch, the third switch and the fourth switch, so that the return loss of the working frequency of the low-noise amplifier is smaller and the reliability is high. In addition, the low-noise amplifier and the radio frequency chip are provided with the first output matching circuit for filtering the single frequency band and the second output matching circuit for converting the output impedance to the preset target output impedance, and the first output matching circuit generates a low impedance point at a low frequency, so that the filtering of the single frequency band is realized, for example, the channel inhibition of the 2.4GHz WiFi frequency band is realized in a receiving path of the 5GHz WiFi, and the out-of-band narrow-band inhibition of the single frequency band is effectively realized. More preferably, in the working frequency band, after the signals sequentially pass through the first output matching circuit and the second output matching circuit, the output impedance is converted to a preset target output impedance, so that the low-noise amplifier and the radio frequency chip reduce the return loss, and the low-noise amplifier and the radio frequency chip have strong anti-interference capability and high sensitivity.
It should be noted that the above embodiments described above with reference to the drawings are only for illustrating the present invention and not for limiting the scope of the present invention, and it should be understood by those skilled in the art that modifications or equivalent substitutions to the present invention are intended to be included in the scope of the present invention without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words occurring in the singular form include the plural form and vice versa. In addition, unless specifically stated, all or a portion of any embodiment may be used in combination with all or a portion of any other embodiment.
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310216385.4A CN116248052B (en) | 2023-02-27 | 2023-02-27 | Low noise amplifier and radio frequency chip |
| PCT/CN2024/073945 WO2024179236A1 (en) | 2023-02-27 | 2024-01-25 | Low noise amplifier and radio-frequency chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310216385.4A CN116248052B (en) | 2023-02-27 | 2023-02-27 | Low noise amplifier and radio frequency chip |
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| CN116248052A CN116248052A (en) | 2023-06-09 |
| CN116248052B true CN116248052B (en) | 2025-08-12 |
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| CN202310216385.4A Active CN116248052B (en) | 2023-02-27 | 2023-02-27 | Low noise amplifier and radio frequency chip |
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| WO (1) | WO2024179236A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116248052B (en) * | 2023-02-27 | 2025-08-12 | 深圳飞骧科技股份有限公司 | Low noise amplifier and radio frequency chip |
| CN117439549B (en) * | 2023-12-13 | 2024-03-15 | 深圳飞骧科技股份有限公司 | Gain-adjustable linear low noise amplifier |
| CN117595800B (en) * | 2024-01-10 | 2024-04-12 | 深圳飞骧科技股份有限公司 | Low noise amplifier and RF power amplifier module |
| CN118826656A (en) * | 2024-07-01 | 2024-10-22 | 博瑞集信(西安)电子科技股份有限公司 | RF low noise amplifier chip with bypass function |
| CN119945343B (en) * | 2025-04-10 | 2025-07-04 | 深圳飞骧科技股份有限公司 | Low noise amplifier circuit and RF power amplifier module |
| CN120934463B (en) * | 2025-10-14 | 2026-01-13 | 成都嘉纳海威科技有限责任公司 | A low-noise amplifier circuit that improves stability and bypass linearity |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381713A (en) * | 2021-06-07 | 2021-09-10 | 武汉大学 | Dual-band low-noise amplifier based on reconfigurable inductor |
| CN115296620A (en) * | 2022-09-29 | 2022-11-04 | 深圳飞骧科技股份有限公司 | Multi-band adjustable gain low-noise amplifier |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10147990B2 (en) * | 2016-08-26 | 2018-12-04 | Skyworks Solutions, Inc. | Low-noise amplifier with low-loss bypass mode |
| CN110752829B (en) * | 2019-09-23 | 2023-03-24 | 航天科工微电子系统研究院有限公司 | Bias circuit and amplifier circuit applied to 5G WiFi communication low-noise amplifier |
| US11616475B2 (en) * | 2021-01-05 | 2023-03-28 | Psemi Corporation | Amplifier gain-tuning circuits and methods |
| CN115441838A (en) * | 2022-09-15 | 2022-12-06 | 深圳飞骧科技股份有限公司 | Low noise amplifier and radio frequency chip |
| CN115441839A (en) * | 2022-09-16 | 2022-12-06 | 深圳飞骧科技股份有限公司 | Multi-band low noise amplifier, integrated circuit chip and electronic device |
| CN115567006A (en) * | 2022-10-21 | 2023-01-03 | 深圳飞骧科技股份有限公司 | Low noise amplifier and radio frequency chip |
| CN116232238B (en) * | 2023-02-27 | 2025-08-05 | 深圳飞骧科技股份有限公司 | Low noise amplifier and RF chip |
| CN116248052B (en) * | 2023-02-27 | 2025-08-12 | 深圳飞骧科技股份有限公司 | Low noise amplifier and radio frequency chip |
-
2023
- 2023-02-27 CN CN202310216385.4A patent/CN116248052B/en active Active
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- 2024-01-25 WO PCT/CN2024/073945 patent/WO2024179236A1/en not_active Ceased
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381713A (en) * | 2021-06-07 | 2021-09-10 | 武汉大学 | Dual-band low-noise amplifier based on reconfigurable inductor |
| CN115296620A (en) * | 2022-09-29 | 2022-11-04 | 深圳飞骧科技股份有限公司 | Multi-band adjustable gain low-noise amplifier |
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| CN116248052A (en) | 2023-06-09 |
| WO2024179236A1 (en) | 2024-09-06 |
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