CN107707203A - A kind of ultra-wideband amplifier circuit using inductance cancellation technology - Google Patents

Abstract

The invention discloses an ultra-broadband amplifier circuit using inductance cancellation technology, which includes an active bias circuit, an inductance cancellation element, a power supply VDD and a cascode structure in which two transistors are stacked, wherein the active bias circuit and Power supply VDD connection. The inductance canceling element includes inductor L2 and inductor L3. The two transistors in the cascode structure are transistor M1 and transistor M2 respectively. The source of transistor M1 is grounded through inductor L2. The gate of transistor M1 is connected with resistor R1 in series to input gate voltage . The source of the transistor M2 is connected to the drain of the transistor M1, the gate of the transistor M2 is grounded through the capacitor C2, the gate voltage of the transistor M2 is connected in series with the resistor R3, and the drain of the transistor M3 is connected in series with the inductor L3 and connected to the active bias circuit. The operating frequency of the invention covers megahertz (MHz) to gigahertz (GHz), the bandwidth is equivalent to that of a distributed amplifier, and the unit circuit gain performance, power consumption and chip area are superior to the distributed structure.

Description

A UWB Amplifier Circuit Using Inductance Cancellation Technology

technical field

The invention relates to the technical field of wireless radio frequency communication, in particular to an ultra-wideband amplifier circuit using inductance cancellation technology.

Background technique

In recent years, with the development of high-speed data transmission, optical fiber communication, broadband electromagnetic spectrum monitoring, software radio, cognitive radio system, etc., radio frequency transceivers have become more and more widely used. As one of the most important functional modules in the RF transceiver, the broadband amplifier is used as a power amplifier in the transmitter, and its performance determines the transmission power and efficiency of the transmitter; as a low-noise amplifier in the receiver, it is located at the front end of the receiver. Its performance directly determines the sensitivity and dynamic range of the receiver. In view of the current application requirements for broadband amplifiers, the traditional solution is to use multiple amplifiers covering different frequency ranges in parallel to achieve the purpose of covering continuous bandwidth. When the traditional solution is applied, due to the inclusion of multiple amplifiers covering different frequency ranges, the equipment is bulky, the corresponding cost is high, and the reliability of the equipment is reduced; in addition, due to the need for multiple amplifiers to work at the same time, the power consumption is often large .

To address the shortcomings of traditional solutions, some existing technologies try to use a single amplifier circuit to cover a wide frequency range, that is, use an ultra-wideband amplifier to cover all required frequency ranges. Some methods currently proposed to expand the bandwidth of amplifiers include distributed structures, transformer feedback, parallel feedback composed of inductors and resistors, and so on. However, except for the distributed structure, almost none of these technologies can ensure that the operating frequency of the amplifier covers from a low frequency close to DC to a high frequency exceeding tens of gigahertz (GHz). However, the amplifier with distributed structure has the disadvantages of low unit circuit gain, power consumption and large chip area. Therefore, it is of great significance to carry out research on ultra-wideband amplifiers whose bandwidth is comparable to that of distributed amplifiers, and whose unit circuit gain performance, power consumption, and chip area are superior to distributed structures. However, few related circuit structures have been proposed so far.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, and provides an ultra-wideband amplifier circuit using inductance cancellation technology, its operating frequency covers megahertz (MHz) to gigahertz (GHz), and its bandwidth is equivalent to that of a distributed amplifier. Unit circuit gain performance, power consumption and chip area are superior to distributed structures.

The purpose of the present invention is mainly achieved through the following technical solutions: an ultra-broadband amplifier circuit using inductance cancellation technology, including an active bias circuit, an inductance cancellation element, a power supply VDD and a cascode-cascode structure in which two transistors are stacked. The active bias circuit is connected to the power supply VDD; the inductance canceling element includes an inductor L2 and an inductor L3, and the two transistors in the cascode structure are respectively a transistor M1 and a transistor M2, and the source of the transistor M1 The gate voltage of the transistor M1 is connected to the ground through the inductor L2, and the gate voltage of the transistor M1 is connected in series with the resistor R1; the source of the transistor M2 is connected to the drain of the transistor M1, the gate of the transistor M2 is grounded through the capacitor C2, and the gate of the transistor M2 is connected in series with the resistor R3 to input Gate voltage, the transistor M3 drain is connected in series with the inductor L3 and connected to the active bias circuit; the inductor L2 and the inductor L3 are coupled through a transformer to offset the influence of the inductor L2 on the high-frequency gain; the transistor M1 The gate is connected with an input port, and the line between the inductor L3 and the active bias circuit is provided with an output port.

In the design of broadband amplifiers, the parasitic capacitances from the gate to the source, from the gate to the drain, and from the drain to the source of the transistor are the main factors that determine the characteristic frequency of the transistor and limit the expansion of the circuit bandwidth. The expansion of the low-frequency bandwidth is mainly limited by the capacitance from the gate to the source. The specific performance is that the quality factor of the input matching network is very high at low frequencies, and it is difficult to achieve wide-band coverage; while the expansion of the high-frequency bandwidth is mainly determined by the gate. The pole-to-drain capacitance (ie, Miller capacitance) and the drain-to-source capacitance, specifically, the presence of these two capacitances causes the high-frequency gain of the transistor to roll off rapidly with frequency.

In the present invention, the source of the transistor M1 is grounded through the inductor L2 to form a common-source transistor, and the gate of the transistor M2 is grounded through the capacitor C2 to form a common-gate transistor. When the present invention is applied, the cascode structure composed of the transistor M1 and the transistor M2 can significantly reduce the roll-off of the high-frequency gain caused by the Miller capacitor, thereby realizing the expansion of the high-frequency bandwidth.

The inductance L2 connected in series with the source of the common source transistor can make the high-frequency input match better. The principle is that the inductance L2 partly offsets the capacitance from the gate to the source, thereby reducing the quality factor of the input matching network. However, because the inductance essentially introduces negative feedback, the frequency response characteristics of the inductance determine that it will seriously deteriorate the high-frequency gain of the amplifier; and the inductance L3 connected in series with the drain of the common-gate transistor can compensate for the capacitance from the drain to the source , to increase the high frequency gain of the amplifier. The present invention introduces coupling between the inductance connected in series with the source of the common-source transistor and the drain of the common-gate transistor, which can maintain the input matching effect of the inductance connected in series with the source of the common-source transistor, and eliminate the source of the common-source transistor The inductance deteriorates the high-frequency gain and realizes the widening of the high-frequency bandwidth.

When the present invention is applied, the signal is input through the input port, amplified by the common-source-common-gate structure in which two transistors are stacked, and then output through the output port.

Further, an ultra-wideband amplifier circuit using inductance cancellation technology further includes a feedback circuit, one end of the feedback circuit is connected to the gate of the transistor M1, and the other end is connected to the line between the inductor L3 and the output port. When the present invention is applied, the capacitor C1 is used to block the DC signal, and the function of the feedback circuit is to reduce the quality factor of the input matching network (that is, to weaken the influence of the parasitic capacitance from the grid to the source of the transistor on the bandwidth expansion), so as to realize the amplifier's The working bandwidth is extended to the low frequency end.

Further, an ultra-wideband amplifier circuit using inductance cancellation technology further includes an input matching circuit, the input matching circuit includes an inductance L1, and the inductance L1 is connected in series on the line between the gate of the transistor M1 and the input port. When the present invention is applied, the matching of the circuit is completed jointly by the inductance L1 and the inductance L2 connected in series with the source of the common source transistor, and the inductance L2 can make the high frequency band of the circuit realize better matching.

Further, the active bias circuit includes a transistor M3, an inductor L4, a resistor R4 and a capacitor C3, the source of the transistor M3 is connected to the inductor L3, the drain of the transistor M3 is connected to the power supply VDD after being connected in series with the inductor L4, and the transistor M3 The drain is grounded through the capacitor C3, and the two ends of the resistor R4 are respectively connected to the gate and the drain of the transistor M3.

The bias circuit of a traditional monolithic integrated amplifier circuit is implemented by an inductor or a resistor or a network composed of the two. When the operating frequency of the circuit needs to be extended to a lower frequency (such as below 1GHz), the inductor or resistor bias circuit structure requires The inductance value is large, and the chip area occupied by the on-chip implementation is relatively large, and the cost is relatively high. In addition, additional DC power consumption will be added. The traditional operating bandwidth is extended to the amplifier monolithic integrated circuit close to DC, and some of them implement the bias circuit off-chip. This method is very inconvenient in practical application because it involves gold wire bonding, etc., and at the same time Increased costs.

The impedance value when the active bias circuit of the present invention is used as a load can be adjusted by changing the resistor R4, and the capacitor C3 and the inductance L4 in the active bias circuit are supplements to the bias circuit formed by the transistor 3 and the resistor R4, mainly It is used to compensate the shortcoming that the bias circuit formed by the transistor 3 and the resistor R4 has poor choke characteristics at high frequencies. By introducing an improved active bias circuit, the present invention can ensure better choke characteristics in the frequency range from low frequency close to direct current to high frequency reaching tens of gigahertz, thereby effectively avoiding the shortcomings of traditional bias circuits .

Further, the transistors in the cascode structure are any one of N-channel transistors, P-channel transistors, high electron mobility transistors and pseudo high electron mobility transistors.

In summary, the present invention has the following advantages compared with the existing broadband circuit topology: the frequency coverage of the present invention can range from low frequencies close to direct current to high frequencies that are more than half of the process characteristic frequency, and the octave bandwidth can reach 200 Above, its bandwidth can be compared with the distributed structure with the widest bandwidth that can be realized at present, and the chip area and gain are far superior to the distributed structure. As an option, it can replace distributed amplifiers and is widely used in system diagrams such as optical fiber communication and software radio.

Description of drawings

The drawings described here are used to provide a further understanding of the embodiments of the present invention, constitute a part of the application, and do not limit the embodiments of the present invention. In the attached picture:

Fig. 1 is the schematic circuit diagram of embodiment 1;

Fig. 2 is the block diagram of the circuit structure of the amplifier circuit shown in Fig. 1 in cascaded three stages;

Fig. 3 is the schematic circuit diagram of Fig. 2;

Fig. 4 is the parameter simulation result of the three-stage cascaded amplifier shown in Fig. 2 .

detailed description

In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the examples and accompanying drawings. As a limitation of the present invention.

Example 1:

As shown in Figure 1, an ultra-wideband amplifier circuit using inductance cancellation technology includes an active bias circuit, an inductance cancellation component, an input matching circuit, a feedback circuit, a power supply VDD, and a cascode structure in which two transistors are stacked , wherein, the inductance canceling element of this embodiment includes an inductor L2 and an inductor L3, and the transistors in the cascode structure are N-channel transistors, P-channel transistors, high electron mobility transistors and pseudo high electron mobility transistors Any one of the N-channel transistors shown in Figure 1. The two transistors in the cascode structure of this embodiment are a transistor M1 and a transistor M2 respectively, the source of the transistor M1 is grounded, and the inductor L2 is connected in series on the line between the source of the transistor M1 and the ground. In this embodiment, the source of the transistor M2 is connected to the drain of the transistor M1, the gate of the transistor M2 is grounded through the capacitor C2, and the drain of the transistor M3 is connected to the active bias circuit after being connected in series with the inductor L3. In this embodiment, the gate of the transistor M1 is connected in series with a resistor R1, and the gate of the transistor M2 is connected in series with a resistor R3. When this embodiment is applied, the gate of the transistor M1 and the gate of the transistor M2 are biased directly through the resistor R1 and the resistor R3 respectively. . In this embodiment, the inductance L2 and the inductance L3 are coupled through a transformer, the coupling coefficient is k, and the coupling is used to offset the influence of the inductance L2 on the high-frequency gain. In this embodiment, the gate of the transistor M1 is connected to an input port, and the line between the inductor L3 and the active bias circuit is provided with an output port.

The feedback circuit of this embodiment includes a capacitor C1 and a resistor R2 connected in series with the capacitor C1. One end of the feedback circuit is connected to the gate of the transistor M1, and the other end is connected to the line between the inductor L3 and the output port. Wherein, the function of the capacitor C1 is to block the DC signal, and prevent the drain bias voltage of the transistor M1 from affecting the gate bias voltage of the transistor M1.

The input matching circuit of this embodiment includes an inductor L1, wherein the inductor L1 is connected in series on the line between the gate of the transistor M1 and the input port.

The active bias circuit of this embodiment includes a transistor M3, an inductor L4, a resistor R4, and a capacitor C3, wherein the inductor L4 is connected to the drain of the transistor M3, the drain of the transistor M3 is grounded through the capacitor C3, and both ends of the resistor R4 are connected to the transistor M3 respectively. the gate and drain connections. The active bias circuit of this embodiment is specifically connected to the inductor L3 through the source of the transistor M3, and connected to the power supply VDD through the other end of the inductor L4 opposite to the drain of the transistor M3. In order to reduce power consumption during implementation of this embodiment, the size of the transistor M3 is generally selected to be smaller. The resistance value of the resistor R4 is selected according to the drain current of the circuit. The introduction of the improved active bias circuit of this embodiment can effectively avoid the introduction of an inductance with a larger inductance value (corresponding to a larger size in a monolithic integrated circuit) when the operating frequency of the circuit is extended to a low frequency close to DC. In turn, the chip area is reduced, and the cost is reduced; at the same time, additional parasitic parameters caused by larger inductance are avoided, and circuit performance is improved.

When this embodiment is applied, the cascode-cascode transistor is used to reduce the Miller effect that affects the expansion of the high-frequency bandwidth, so as to realize the expansion of the high-frequency bandwidth; the inductance canceling element is used to reduce the effect of the transistor source inductance on the high-frequency gain The degeneration effect expands the high-frequency bandwidth of the amplifier; the feedback circuit is used to reduce the quality factor of the input matching network and expand the low-frequency bandwidth; the input matching circuit is completed by the series inductor L1 at the input end, so that the circuit has better return loss; active The bias circuit is composed of the transistor M3 and the passive components inductor L4, resistor R4 and capacitor C3 to overcome the shortcomings of traditional inductor or resistor bias circuits in size or power consumption when the frequency coverage is close to DC. The basic idea of this embodiment is to use various technologies to offset the negative impact of the above parasitic capacitance, so as to realize the expansion of the bandwidth of the amplifier.

When the circuit structure proposed in this embodiment is used in the design of integrated circuits in processes such as CMOS or GaAs, the bandwidth of the amplifier can exceed more than half of the characteristic frequency of the transistor, and can be widely used in systems such as optical fiber communication, software radio, and broadband electromagnetic spectrum monitoring. middle.

Example 2:

This embodiment makes the following further limitations on the basis of Embodiment 1: This embodiment cascades the amplifier circuit units in the three-stage implementation case 1 (amplifiers in practice generally have to be multi-stage cascaded to meet the requirements for gain, etc. The requirements of the index, each cascaded circuit is usually called an amplifier circuit unit), and its simulation results are given. Figure 2 is a block diagram of the circuit structure of the cascaded three-stage amplifier circuit shown in Figure 1, which includes ultra-wideband amplifier circuit unit I using inductance cancellation technology, ultra-wideband amplifier circuit unit II using inductance cancellation technology and UWB amplifier circuit unit III, Fig. 3 is a circuit schematic diagram corresponding to the block diagram shown in Fig. 2 . As shown in Figure 3, the ultra-wideband amplifier circuit unit I using inductance cancellation technology, the ultra-wideband amplifier circuit unit II using inductance cancellation technology and the ultra-wideband amplifier circuit unit III using inductance cancellation technology each contain a amplifier circuit. Between ultra-wideband amplifier circuit unit I using inductance cancellation technology and ultra-wideband amplifier circuit unit II using inductance cancellation technology, between ultra-wideband amplifier circuit unit II using inductance cancellation technology and ultra-wideband amplifier circuit unit III using inductance cancellation technology A capacitor is respectively connected in series between them, and the function of these two capacitors is to block direct current and ensure that each circuit unit is biased in a correct bias state.

For the circuit structure shown in Figure 3, the simulation verification is carried out based on the 0.15μm GaAsp pHEMT process, and the characteristic frequency of the transistor of this process is 95GHz. Figure 4 shows the simulation results for gain and input return loss. It can be seen from FIG. 4 that the UWB amplifier of this embodiment achieves a bandwidth of 0.1 MHz to greater than 50 GHz, that is, the octave bandwidth reaches 500, and the absolute bandwidth exceeds half of the characteristic frequency of the transistor. The gain within the bandwidth is greater than 20dB, and the return loss is better than 10dB, that is, higher gain and better matching are realized.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (5)

1. a kind of ultra-wideband amplifier circuit using inductance cancellation technology, it is characterised in that including active bias circuit, inductance The cascode structure of element, power vd D and two transistor stacks is offset, the active bias circuit connects with power vd D Connect；The inductance, which offsets element, includes inductance L2 and inductance L3, and two transistors in the cascode structure are respectively brilliant Body pipe M1 and transistor M2, the transistor M1 source electrodes are grounded by inductance L2, are inputted after transistor M1 grid series resistors R1 Grid voltage；The transistor M2 source electrodes are connected with transistor M1 drain electrodes, and transistor M2 grids are grounded by electric capacity C2, transistor M2 grid Grid voltage is inputted after the series resistor R3 of pole, is connected after transistor M3 drain electrode tandem electric inductances L3 with active bias circuit；The inductance L2 Coupled between inductance L3 by transformer, to offset influences of the inductance L2 to high-frequency gain；The grid of the transistor M1 Pole is connected with input port, and the circuit between inductance L3 and active bias circuit is provided with output port.

2. a kind of ultra-wideband amplifier circuit using inductance cancellation technology according to claim 1, it is characterised in that also Including feedback circuit, the feedback circuit include electric capacity C1 and with electric capacity C1 series winding resistance R2, described feedback circuit one end with Transistor M1 grids are connected, and its other end is connected on the circuit between inductance L3 and output port.

3. a kind of ultra-wideband amplifier circuit using inductance cancellation technology according to claim 1, it is characterised in that also Including input matching circuit, the input matching circuit includes inductance L1, the inductance L1 be serially connected with transistor M1 grids with it is defeated On circuit between inbound port.

A kind of 4. ultra-wideband amplifier circuit using inductance cancellation technology according to claim 1, it is characterised in that institute Stating active bias circuit includes transistor M3, inductance L4, resistance R4 and electric capacity C3, and the transistor M3 source electrodes connect with inductance L3 Connect, be connected after transistor M3 drain electrode tandem electric inductances L4 with power vd D, transistor M3 drain electrodes are grounded by electric capacity C3, resistance R4 two End connects with transistor M3 grid and drain electrode respectively.

5. a kind of ultra-wideband amplifier circuit using inductance cancellation technology according to any one in Claims 1 to 4, Characterized in that, the transistor in the cascode structure is N-channel transistor, p channel transistor, high electron mobility Any one in transistor and counterfeit HEMT.