Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a sensing element and a pressure sensor.
The technical scheme adopted by the invention is as follows:
a sensing element, comprising:
a first substrate having first and second surfaces opposite to each other in a thickness direction thereof;
a second substrate covering the first surface of the first substrate; having opposite first and second surfaces in a thickness direction of the second substrate, wherein the second surface of the second substrate is in contact with the first surface of the first substrate; at least one piezoresistor area is arranged in the second substrate, the piezoresistor area is close to the first surface of the second substrate, the piezoresistor area is provided with a piezoresistor connection area, and the piezoresistor connection area is electrically contacted with a contact area;
at least one protective layer covering the first surface of the second substrate;
the voltage dependent resistor area and the voltage dependent resistor connecting area are positioned on the inner side of the protection ring;
the shielding layer is arranged on the surface of the protective layer or between the protective layer and the piezoresistor area;
wherein at least one of the first substrate, the guard ring, and the shielding layer is connected to an external circuit through the contact region.
In some embodiments, the doping concentration of the second substrate is less than the doping concentration of the first substrate.
In some embodiments, the shielding layer is disposed on the surface of the protective layer, and the material of the shielding layer is one of a doped polysilicon layer, an aluminum layer, a silicon-chromium alloy layer, a platinum layer, a titanium layer and a nickel layer with doping substances.
In some embodiments, the shielding layer is disposed between the protective layer and the varistor region, the shielding layer being a doped layer with a dopant species.
In some embodiments, the dopant is one of boron, indium, arsenic, phosphorus, and antimony.
In some embodiments, the contact region has a conductive interconnect region for electrically biasing the varistor region through the contact region.
In some embodiments, the conductivity type of the first substrate is opposite to the conductivity type of the varistor region.
In some embodiments, the protective layer is a single layer, the protective layer is SiO 2 A layer.
In some embodiments, the protective layer is a multilayer, the protective layer comprising at least one layer of SiO 2 A layer and at least one SiN layer.
In some embodiments, the second surface of the first substrate is open to hollow regions.
A pressure sensor comprising a signal processing unit and at least one sensing element as described above, the signal processing unit converting a pressure signal of the sensing element into an output electrical signal.
In some embodiments, the sensing elements are plural, and the plural sensing elements are coupled by a sensor adjustment circuit.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the sensing element is used for fixing the potential below the piezoresistor region through the first protective ring arranged between the piezoresistor region and the second surface of the substrate, and is in combined action with the second protective ring arranged between the protective layer and the first protective ring, and the potential is fixed on the shielding layer around the piezoresistor region, so that the influence of free charges generated by the outside and the substrate on the piezoresistor region is reduced.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the invention and practice it.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the embodiments, read in conjunction with the accompanying drawings. The directional terms mentioned in the following embodiments are, for example: upper, lower, left, right, front or rear, etc., are merely references to the directions of the drawings. Thus, directional terminology is used for the purpose of illustration and is not intended to be limiting of the invention, and furthermore, like reference numerals refer to like elements throughout the embodiments.
Example 1:
as shown in fig. 2, a sensing element includes:
a first substrate 1 having opposite first and second surfaces in a thickness direction thereof;
a second substrate 2 covering the first surface of the first substrate 1; having opposite first and second surfaces in the thickness direction of the second substrate 2, wherein the second surface of the second substrate 2 is in contact with the first surface of the first substrate 1; at least one piezoresistor region 4 is arranged in the second substrate 2, the piezoresistor region 4 is close to the first surface of the second substrate 2, the piezoresistor region 4 is provided with a piezoresistor connection region 5, and the piezoresistor connection region 5 is electrically contacted with at least two contact regions 801;
at least one protective layer covering the first surface of the second substrate 2;
at least one guard ring 3 disposed in the second substrate 2, and the varistor region 4 and the varistor connecting region 5 are located inside the guard ring 3;
a shielding layer 9 disposed on the surface of the protective layer or between the protective layer and the varistor region 4;
wherein at least one of the first substrate 1, guard ring 3 and shielding layer 9 is connected to an external circuit through a contact region 801. It will be appreciated that the second substrate 2 and guard ring 3 and the shielding layer 9 form an enclosure for the varistor region 4 and the varistor-connection region 5.
In the present embodiment, the doping concentration of the second substrate 2 is smaller than that of the first substrate 1. Specifically, the doping concentration of the first substrate 1 is greater than 5×10 18 /cm 3 Therefore, the conductive material has high conductivity and can play a role of fixing potential; the doping concentration of the second substrate 2 is less than 1×10 19 /cm 3 It can be seen that the doping concentration of the second substrate 2 is smaller than the doping concentration of the first substrate 1.
In this embodiment, the manufacturing process of the second substrate 2 is as follows: first a layer of a low-doped second substrate 2 is grown on a first substrate 1, the doping concentration of the second substrate 2 is less than 1 x 10 19 /cm 3 。
In this embodiment, the material of the shielding layer 9 is a doped polysilicon layer with a doping substance. Specifically, the doping substance is one of boron, indium, arsenic, phosphorus and antimony.
In this embodiment, each contact region 801 has a conductive interconnect region 8, the conductive interconnect region 8 being used to electrically bias the varistor region 4 through the contact region 801.
In this embodiment, the conductivity type of the substrate 1 is opposite to the conductivity type of the varistor region 4. Specifically, the conductivity type of the substrate 1 may be p-type and the conductivity type of the varistor region 4 may be n-type, or the conductivity type of the substrate 1 may be n-type and the conductivity type of the varistor region 4 may be p-type.
In the present embodiment, the protective layers have two layers, which are respectively defined as a first protective layer 6 and a second protective layer 7 for convenience of description, wherein the first protective layer 6 is SiO 2 The layer, the second protective layer 7, is a SiN layer. It should be noted that the protective layer may be provided with only one SiO layer 2 The layer may be a protective layer having a certain insulation property.
In this embodiment, the second surface of the substrate 1 is provided with a hollow region 10, and the hollow region 10 may be formed by a groove or a notch provided on the second surface of the substrate 1.
Example 2:
as shown in fig. 3, the difference from embodiment 1 is that the first substrate 1 and the guard ring 3 are both connected to an external circuit through a contact region 801.
Example 3:
as shown in fig. 4, the difference from embodiment 1 is that the first substrate 1 is not connected to the guard ring 3 and the shielding layer 9, and is not connected to the external circuit through the contact region 801, in which case, since the second substrate 2 and the guard ring 3 and the shielding layer 9 form an enclosure for the varistor region 4 and the varistor connecting region 5, the enclosure can still have a certain absorption capacity for free charges, although the guard ring 3, the shielding layer 9 and the external circuit are not connected.
Example 4:
as shown in fig. 5, the difference from embodiment 1 is that the first substrate 1 is connected only to an external circuit through a contact region 801.
Example 5:
as shown in fig. 6, the difference from embodiment 1 is that the first substrate 1 and the shielding layer 9 are connected and connected to an external circuit through a contact region 801.
The manufacturing method of the sensing element of embodiment 1 to embodiment 5 is as follows:
s1, a layer of second substrate 2 is epitaxially grown on the first substrate 1, wherein the doping concentration of the first substrate 1 is more than 5 multiplied by 10 18 /cm 3 The doping concentration of the second substrate 2 is less than 1×10 19 /cm 3 。
S2, forming a piezoresistor region 4, a piezoresistor connecting region 5 and a protection ring 3 through multiple photoetching and injection or doping processes. The doping substance of the guard ring 3 may be one of boron, indium, arsenic, phosphorus and antimony, and the doping substance of the varistor region 4 is the same as the doping substance of the varistor connecting region 5, and the doping substance may be one of boron, indium, arsenic, phosphorus and antimony.
S3, forming a first protective layer 6 of 30-1500 nm, namely SiO, by using methods such as hot oxygen, LPCVD (low pressure vapor deposition) or PECVD (plasma enhanced vapor deposition) 2 A layer.
Forming a second protective layer 7 of SiN layer of 30nm-3000nm by LPCVD/PECVD, etc., wherein the protective layer can have only one SiO layer 2 Layers, and thus steps, are not necessary.
S4, forming a 100-1500 nm polycrystalline silicon layer by LPCVD or PECVD and the like, and removing the polycrystalline silicon layer by photoetching to form a shielding layer 9;
and S5, exposing the conductive interconnection area 8 through photoetching.
S6, photoetching and sputtering or evaporating a 100-1500 nm aluminum layer or a silicon-chromium alloy layer or a platinum layer or a titanium layer or a nickel layer or a doped polysilicon layer, and stripping to form a contact area 801, or sputtering or evaporating a 100-1500 nm aluminum layer or a silicon-chromium alloy layer or a platinum layer or a titanium layer or a nickel layer or a doped polysilicon layer, and removing by photoetching to form a contact area 801.
And S7, etching a window on the second surface of the first substrate 1 by photoetching and etching a hollow region 10 by etching or deep silicon etching.
Example 6:
as shown in fig. 7, the difference from embodiment 1 is that: a shielding layer 9 disposed between the protective layer and the varistor region 4; specifically, the shielding layer 9 is formed by photolithography and implantation or doping processes to form a doped layer different from the doped material in the varistor region 4, and thus the position of the shielding layer 9 is different from that of the shielding layer 9 in embodiments 1 to 5.
Wherein the first substrate 1, guard ring 3 and shielding layer 9 are connected and connected to an external circuit via contact areas 801.
Example 7:
as shown in fig. 8, the difference from embodiment 6 is that the first substrate 1 and the guard ring 3 are both connected to an external circuit through a contact region 801.
Example 8:
as shown in fig. 9, the difference from embodiment 6 is that the first substrate 1 is not connected to the guard ring 3 and the shielding layer 9, and is not connected to the external circuit through the contact region 801, in which case, since the second substrate 2 and the guard ring 3 and the shielding layer 9 form an enclosure for the varistor region 4 and the varistor connecting region 5, the enclosure can still have a certain absorption capacity for free charges, although the guard ring 3, the shielding layer 9 and the external circuit are not connected.
Example 9:
as shown in fig. 10, the difference from embodiment 6 is that the first substrate 1 is connected to only an external circuit through a contact region 801.
Example 10:
as shown in fig. 11, the difference from embodiment 6 is that the first substrate 1 and the shielding layer 9 are connected and connected to an external circuit through a contact region 801.
The manufacturing method of the sensing element of embodiment 6-embodiment 10 is as follows:
s1, a layer of second substrate 2 is epitaxially grown on the first substrate 1, wherein the doping concentration of the first substrate 1 is more than 5 multiplied by 10 18 /cm 3 The doping concentration of the second substrate 2 is less than 1×10 19 /cm 3 。
S2, forming a piezoresistor region 4, a piezoresistor connecting region 5 and a protection ring 3 through multiple photoetching and injection or doping processes. Wherein, the doping material of the protection ring 3 can be one of boron, indium, arsenic, phosphorus and antimony; the doping material of the varistor region 4 is the same as the doping material of the varistor connecting region 5 and may be one of boron, indium, arsenic, phosphorus and antimony.
S3, forming a doped layer, namely a shielding layer 9, which is different from the piezoresistive region through photoetching and implantation or doping processes, wherein the doping substance can be one of boron, indium, arsenic, phosphorus and antimony.
S4, forming a first protective layer 6 of 30-1500 nm, namely SiO, by using methods such as hot oxygen, LPCVD (low pressure vapor deposition) or PECVD (plasma enhanced vapor deposition) 2 And (3) a protective layer.
Forming a second protective layer 7 of SiN with a thickness of 30nm-3000nm by LPCVD/PECVD, etc., wherein the protective layer can be formed of only one SiO layer 2 A protective layer, and thus a step is not necessary.
And S5, exposing the conductive interconnection area 8 through photoetching.
S6, photoetching and sputtering or evaporating a 100-1500 nm aluminum layer or a silicon-chromium alloy layer or a platinum layer or a titanium layer or a nickel layer or a doped polysilicon layer, and stripping to form a contact area 801, or sputtering or evaporating a 100-1500 nm aluminum layer or a silicon-chromium alloy layer or a platinum layer or a titanium layer or a nickel layer or a doped polysilicon layer, and removing by photoetching to form a contact area 801.
And S7, etching a window on the second surface of the first substrate 1 by photoetching and etching a hollow region 10 by etching or deep silicon etching.
Example 11:
as shown in fig. 12, the difference from embodiment 1 is that the shielding layer 9 is an aluminum layer.
Wherein the first substrate 1, guard ring 3 and shielding layer 9 are connected simultaneously and via contact area 801 to an external circuit.
Example 12:
as shown in fig. 13, embodiment 11 is different in that the first substrate 1 and the guard ring 3 are connected, and are connected to an external circuit through a contact region 801.
Example 13:
as shown in fig. 14, the difference from embodiment 11 is that the first substrate 1 is not connected to the guard ring 3 and the shielding layer 9, and is not connected to the external circuit through the contact region 801, and in this case, since the second substrate 2 and the guard ring 3 and the shielding layer 9 form an enclosure for the varistor region 4 and the varistor connecting region 5, the enclosure can still have a certain absorption capacity for free charges although the guard ring 3, the shielding layer 9 and the external circuit are not connected.
Example 14:
as shown in fig. 15, the difference from embodiment 11 is that the first substrate 1 is connected only to an external circuit through a contact region 801.
Example 15:
as shown in fig. 16, the difference from embodiment 11 is that the first substrate 1 and the shielding layer 9 are connected and connected to an external circuit through a contact region 801.
The manufacturing method of the sensing element of embodiment 11-embodiment 15 is as follows:
s1, a layer of second substrate 2 is epitaxially grown on the first substrate 1, wherein the doping concentration of the first substrate 1 is more than 5 multiplied by 10 18 /cm 3 The doping concentration of the second substrate 2 is less than 1×10 19 /cm 3 。
S2, forming a piezoresistor region 4, a piezoresistor connecting region 5 and a protection ring 3 through multiple photoetching and injection or doping processes. Wherein, the doping material of the protection ring 3 can be one of boron, indium, arsenic, phosphorus and antimony; the doping material of the varistor region 4 is the same as the doping material of the varistor connecting region 5 and may be one of boron, indium, arsenic, phosphorus and antimony.
S3, forming a first protective layer 6 of 30-1500 nm, namely SiO, by using methods such as hot oxygen, LPCVD (low pressure vapor deposition) or PECVD (plasma enhanced vapor deposition) 2 And (3) a protective layer.
A second protective layer 7 of 30nm to 3000nm, i.e. SiN protective layer, is formed by means of LPCVD or PECVD or the like, which is not necessary since the protective layer may have only one SiO2 layer.
And S4, exposing the conductive interconnection area 8 through photoetching.
S5, photoetching and sputtering or evaporating a 100-1500 nm aluminum layer or a silicon-chromium alloy layer or a platinum layer or a titanium layer or a nickel layer or a doped polysilicon layer, and stripping to form a contact area 801 and a shielding layer 9, or sputtering or evaporating a 100-1500 nm aluminum layer or a silicon-chromium alloy layer or a platinum layer or a titanium layer or a nickel layer or a doped polysilicon layer, and removing by photoetching and etching to form the contact area 801 and the shielding layer 9.
S6, etching a window on the second surface of the substrate 1 by photoetching and etching a hollow region 10 by etching or deep silicon etching.
To sum up:
the difference between examples 1-5 is that: the first substrate 1 is connected to an external circuit.
The difference between examples 6-10 is that: the first substrate 1 is connected to an external circuit. Example 6-example 10 has the advantage over the other examples that the residual stress created in the film region above the hollow region 10 is less, and because the film region is relatively thin, the stress created by the pressure in the film is greater, and the sensitivity is correspondingly greater.
The difference between examples 11-15 is: the first substrate 1 is connected to an external circuit. In example 11-example 15, the shielding layer 9 and the contact region 801 are formed integrally, and the manufacturing method has fewer steps and lower cost compared with other examples.
In still other embodiments, a pressure sensor includes a signal processing unit and at least one sensing element as provided in any one of embodiments 1-15, the signal processing unit converting a pressure signal of the sensing element into an output electrical signal. Of course, there may be multiple sensing elements coupled by the sensor conditioning circuit.
Because uncertainty exists in the test process and the test cost is high at one time, the resistance values of the piezoresistive areas of the sensing element provided by the invention and the sensing element without the shielding layer, the sensing element with the shielding layer and the sensing element with the second protection ring under different external electric fields are compared through process simulation, and as shown in fig. 17, the resistance value change of the sensing element without the shielding layer is the largest; the sensing element with the shielding layer and the second protection ring, namely the prior art disclosed in the literature, is used for providing relatively gentle resistance change of the existing sensor, so that the influence of an electric field on the resistance value of the piezoresistor is effectively reduced due to the existence of the shielding layer; the resistance change rate of the sensing element provided by the invention is further reduced, which indicates that the influence of free charge on the resistance of the piezoresistor is further reduced.
In the description of the embodiments of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.