CN101005097A - Semiconductor piezoresistive sensor and method of operation thereof - Google Patents
Semiconductor piezoresistive sensor and method of operation thereof Download PDFInfo
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Abstract
Description
技术领域technical field
本发明涉及一种半导体传感器,特别是涉及一种半导体压阻式传感器及其操作方法。The invention relates to a semiconductor sensor, in particular to a semiconductor piezoresistive sensor and an operating method thereof.
背景技术Background technique
压力传感器被广泛地应用于各领域,其中压力量测的原理依据应用领域及需求之不同包括有压阻式(piezoresistive type)、压电式(piezoelectric type)及电容式(capacitive type)。其中,压阻式传感器具有高输出电压与高灵敏度等优点,其利用材料之电阻值会随应力作用而改变之效应作为量测原理。Pressure sensors are widely used in various fields, and the principle of pressure measurement includes piezoresistive type, piezoelectric type and capacitive type according to different application fields and requirements. Among them, the piezoresistive sensor has the advantages of high output voltage and high sensitivity, and uses the effect that the resistance value of the material changes with the stress as the measurement principle.
请参照图1所示,为一种习知半导体压阻式传感器1之剖面示意图,半导体压阻式传感器1包括一半导体基材10、一压阻组件11以及一电路12,其中半导体基材10(例如单晶硅基材)包括一悬膜(diaphram)101与一基材(base)102。基材102用以固定悬膜101之两端,而压阻组件11设置于悬膜101内,用以作为半导体压阻式传感器1的感测组件。电路12与压阻组件11电性连接,且电路12例如包括一互补式金氧半导体(MOS)、桥式电路、放大电路或逻辑电路等,用以接收并处理压阻组件11所输出的讯号。Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional semiconductor piezoresistive sensor 1. The semiconductor piezoresistive sensor 1 includes a semiconductor substrate 10, a piezoresistive component 11 and a circuit 12, wherein the semiconductor substrate 10 (eg single crystal silicon substrate) includes a
半导体基材10可为一n-型半导体,再藉由扩散或是离子注入工艺形成一p-型压阻组件11,于此,半导体基材10与压阻组件11之接面形成一p-n结(junction)。如图1所示,压阻组件11之两端可分别与一p+型内连接(interconnect)组件13电性连接,电路12则藉由覆盖于半导体基材10表面之一绝缘层14所开设之一开口141与p+型内连接组件13电性连接。The semiconductor substrate 10 can be an n-type semiconductor, and a p-type piezoresistive element 11 is formed by diffusion or ion implantation process, where the junction between the semiconductor substrate 10 and the piezoresistive element 11 forms a p-n junction (junction). As shown in FIG. 1, both ends of the piezoresistive element 11 can be electrically connected to a p+ type interconnect (interconnect) element 13 respectively, and the circuit 12 is opened by an insulating layer 14 covering the surface of the semiconductor substrate 10. An opening 141 is electrically connected to the p+-type internal connection element 13 .
承上所述,当施加一电压V于半导体压阻式传感器1时,在p-型压阻组件11下方形成负空间电荷(negative space charge),此负空间电荷会随时间而漂动,而造成压阻组件11之电阻值随时间改变,进而使压阻组件11输出讯号随时间漂移(drift)。另外,因覆盖压阻组件11之绝缘层14材质会束缚一些正表面电荷,由于正表面电荷亦会随时间漂动而使压阻组件11之电阻值随时间改变的现象更加严重,进而降低压阻组件11输出讯号之准确度。As mentioned above, when a voltage V is applied to the semiconductor piezoresistive sensor 1, a negative space charge (negative space charge) is formed under the p-type piezoresistive element 11, and the negative space charge will drift with time, and The resistance value of the piezoresistive element 11 changes with time, and the output signal of the piezoresistive element 11 drifts with time. In addition, because the material of the insulating layer 14 covering the piezoresistive element 11 will bind some positive surface charges, since the positive surface charge will also drift with time, the phenomenon that the resistance value of the piezoresistive element 11 changes with time is more serious, thereby reducing the voltage. The accuracy of the output signal of the resistance component 11.
为解决上述之问题,如图2所示,习知技术于半导体基材10上形成一n+型掺杂区15,再于n+型掺杂区15施以一适当电压使p-n结形成逆向偏压(reverse bias),因而限制电流于压阻组件11内部,从而改善因漏电流而降低半导体压阻式传感器1量测之准确度的现象。然而,在一般习用p-型压阻组件11的制作过程中,于n-型半导体基材10上形成n+型掺杂区15需增加额外的工序步骤与成本例如光罩、掺杂及热扩散等。In order to solve the above-mentioned problems, as shown in Figure 2, the conventional technology forms an n+ type doped region 15 on the semiconductor substrate 10, and then applies an appropriate voltage to the n+ type doped region 15 to make the p-n junction form a reverse bias (reverse bias), thus limiting the current inside the piezoresistive component 11, thereby improving the phenomenon of reducing the measurement accuracy of the semiconductor piezoresistive sensor 1 due to leakage current. However, in the production process of the conventional p-type piezoresistive device 11, forming the n+-type doped region 15 on the n-type semiconductor substrate 10 requires additional process steps and costs such as photomask, doping and thermal diffusion. wait.
有鉴于此,如何提供一种工序简单且能够有效改善压阻组件之电阻值随时间改变的现象,实为重要课题之一。In view of this, how to provide a simple process that can effectively improve the phenomenon that the resistance value of the piezoresistive element changes with time is one of the important issues.
发明内容Contents of the invention
因此,为解决上述问题,本发明提供一种半导体压阻式传感器及其操作方法藉由简易工序步骤,降低制造成本,并有效提高半导体压阻式传感器量测之准确度。Therefore, in order to solve the above-mentioned problems, the present invention provides a semiconductor piezoresistive sensor and its operation method, which can reduce the manufacturing cost and effectively improve the measurement accuracy of the semiconductor piezoresistive sensor through simple process steps.
根据本发明的目的,提出另一种半导体压阻式传感器与一电路电性连接,其包括一半导体基材、至少一压阻组件以及一导电材料层。半导体基材包括一悬膜与一基材,基材邻设于悬膜周缘;压阻组件设置于悬膜内,并与电路电性连接;导电材料层与悬膜电性连接。According to the object of the present invention, another semiconductor piezoresistive sensor is provided that is electrically connected to a circuit, which includes a semiconductor substrate, at least one piezoresistive element, and a conductive material layer. The semiconductor base material includes a suspension film and a base material. The base material is adjacent to the periphery of the suspension film; the piezoresistive component is arranged in the suspension film and electrically connected with the circuit; the conductive material layer is electrically connected with the suspension film.
根据本发明的另一目的,提出一种半导体压阻式传感器系与一电路电性连接,其包括一半导体基材、至少一压阻组件、一绝缘层以及一遮蔽层。半导体基材包括一悬膜与一基材,基材邻设于悬膜周缘;压阻组件设置于悬膜内,并与电路电性连接;绝缘层设置于半导体基材之上且覆盖压阻组件;遮蔽层设置于绝缘层之上,且覆盖至少部分之绝缘层,并与悬膜电性连接。According to another object of the present invention, a semiconductor piezoresistive sensor is provided that is electrically connected to a circuit, which includes a semiconductor substrate, at least one piezoresistive element, an insulating layer, and a shielding layer. The semiconductor substrate includes a suspension film and a base material. The base material is adjacent to the periphery of the suspension film; the piezoresistive component is arranged in the suspension film and electrically connected with the circuit; the insulating layer is arranged on the semiconductor substrate and covers the piezoresistor Component; the shielding layer is disposed on the insulating layer, covers at least part of the insulating layer, and is electrically connected to the suspension film.
为达上述目的,依据本发明之一种半导体压阻式传感器之操作方法包括下列步骤:施加一第一电压于电路以及施加一第二电压于导电材料层,其中当第一电压减掉第二电压所得之值小于压阻组件与悬膜之间的一导通电压时,压阻组件与悬膜之一接面便可形成一逆向偏压或使该接面不导通。In order to achieve the above object, a method of operating a semiconductor piezoresistive sensor according to the present invention includes the following steps: applying a first voltage to the circuit and applying a second voltage to the conductive material layer, wherein when the first voltage minus the second When the obtained value of the voltage is less than a conduction voltage between the piezoresistive component and the suspension film, a junction of the piezoresistive unit and the suspension film can form a reverse bias voltage or make the junction non-conductive.
为达上述目的,依据本发明之另一种半导体压阻式传感器之操作方法包括下列步骤:施加一第一电压于电路,施加一第二电压于导电材料层以及施加一第三电压于遮蔽层,其中当第一电压减掉第二电压所得之值小于压阻组件与悬膜之间的一导通电压时,压阻组件与悬膜之一接面便可形成一逆向偏压或使该接面不导通。另外,第三电压用以稳定该压阻组件上方之一表面电位To achieve the above object, another semiconductor piezoresistive sensor operating method according to the present invention includes the following steps: applying a first voltage to the circuit, applying a second voltage to the conductive material layer and applying a third voltage to the shielding layer , wherein when the value obtained by subtracting the second voltage from the first voltage is less than a conduction voltage between the piezoresistive component and the suspension film, a junction between the piezoresistive component and the suspension film can form a reverse bias or make the The interface is not conductive. In addition, the third voltage is used to stabilize a surface potential above the piezoresistive element
为达上述目的,依据本发明之再一种半导体压阻式传感器之操作方法包括下列步骤:施加一第一电压于电路以及施加一第二电压于遮蔽层,其中,当第一电压减掉第二电压所得之值小于压阻组件与悬膜之间的一导通电压时,压阻组件与悬膜之一接面便可形成一逆向偏压或使该接面不导通。In order to achieve the above object, another semiconductor piezoresistive sensor operating method according to the present invention includes the following steps: applying a first voltage to the circuit and applying a second voltage to the shielding layer, wherein, when the first voltage minus the second voltage When the resulting value of the two voltages is less than a conduction voltage between the piezoresistive component and the suspension film, a junction between the piezoresistive component and the suspension film can form a reverse bias voltage or make the junction non-conductive.
承上所述,因依据本发明之一种半导体压阻式传感器及其操作方法系利用一导电材料层或一遮蔽层与半导体基材之悬膜电性连接,其中导电材料层与遮蔽层系分别由导电材质与非绝缘材质所构成,将此半导体压阻式传感器架构于一电路中,藉由施加于导电材料层或遮蔽层适当电压,使压阻组件与悬膜之接面形成一逆向偏压或使该接面不导通,所以限制电流于压阻组件内,进而改善压阻组件输出讯号随时间漂移之现象。与习知技术相较,本发明不需于半导体基材上形成与压阻组件不同型式之半导体掺杂区,所以有效简化工序步骤,降低制造成本,进而提高半导体压阻式传感器量测之准确度。Based on the above, a semiconductor piezoresistive sensor and its operating method according to the present invention utilize a conductive material layer or a shielding layer to electrically connect with the suspension film of the semiconductor substrate, wherein the conductive material layer and the shielding layer are It is composed of conductive material and non-insulating material respectively. The semiconductor piezoresistive sensor is constructed in a circuit. By applying an appropriate voltage to the conductive material layer or the shielding layer, the junction of the piezoresistive component and the suspension film forms a reverse direction. The bias voltage may make the junction non-conductive, so the current is limited in the piezoresistive device, thereby improving the phenomenon that the output signal of the piezoresistive device drifts with time. Compared with the conventional technology, the present invention does not need to form a semiconductor doped region different from the piezoresistive element on the semiconductor substrate, so the process steps are effectively simplified, the manufacturing cost is reduced, and the measurement accuracy of the semiconductor piezoresistive sensor is improved. Spend.
为让本发明之上述和其它目的、特征、和优点能更明显易懂,下文特举一较佳实施例,并配合所附图式,作详细说明如下:In order to make the above-mentioned and other purposes, features, and advantages of the present invention more clearly understood, a preferred embodiment is specifically cited below, together with the accompanying drawings, and is described in detail as follows:
附图说明Description of drawings
图1与图2为一种习知半导体压阻式传感器的剖面示意图。1 and 2 are schematic cross-sectional views of a conventional semiconductor piezoresistive sensor.
图3A与图3B为依据本发明第一实施例之一种半导体压阻式传感器的剖面示意图。3A and 3B are schematic cross-sectional views of a semiconductor piezoresistive sensor according to the first embodiment of the present invention.
图4A与图4B为依据本发明第二实施例之一种半导体压阻式传感器的剖面示意图。4A and 4B are schematic cross-sectional views of a semiconductor piezoresistive sensor according to a second embodiment of the present invention.
图5A与图5B为依据本发明第三实施例之一种半导体压阻式传感器的剖面示意图。5A and 5B are schematic cross-sectional views of a semiconductor piezoresistive sensor according to a third embodiment of the present invention.
具体实施方式Detailed ways
以下将参照相关图式,说明依据本发明较佳实施例之半导体压阻式传感器及其操作方法,其中相同的组件将以相同的参照符号加以说明。The semiconductor piezoresistive sensor and its operating method according to preferred embodiments of the present invention will be described below with reference to related drawings, wherein the same components will be described with the same reference symbols.
第一实施例first embodiment
请同时参照图3A与图3B,依据本发明第一实施例之一种半导体压阻式传感器2,其包括一半导体基材20、一绝缘层23、至少一压阻组件21、至少一内连接组件24以及一导电材料层22。半导体压阻式传感器2与一电路3电性连接,电路3例如是一桥式电路或一温度补偿电路。Please refer to FIG. 3A and FIG. 3B at the same time, according to a semiconductor piezoresistive sensor 2 according to the first embodiment of the present invention, it includes a
半导体基材20包括一悬膜201与一基材202。基材202邻设于悬膜201周缘,在本实施例中,悬膜201为n型掺杂区,压阻组件21为p型掺杂区,详细来说,半导体基材20结构可由n-型外延层形成于p型晶片上所构成。其中n型掺杂剂例如是磷(phosphorus)、砷(arsenic)等,而p型掺杂剂例如是硼(boron)、镓(gallium)、二氟化硼(BF2)等。The
压阻组件21设置于悬膜201内,并与电路3电性连接,在本实施例中,压阻组件21为一p-型压阻组件21,利用扩散或离子注入等工序,将p型掺杂剂注入悬膜201内。于所形成之p-型压阻组件21与悬膜201之n型掺杂区之间形成一P-N结,所以当一待测压力施加于悬膜201时,悬膜201产生形变而使压阻组件21的电阻值产生相对应的变化。而后,利用与压阻组件21电性连接之电路3便针对此一电阻值之变化进行讯号处理,例如讯号放大及进行温度补偿等,或者,更进一步并将接收到的电阻值变化量换算成相对应之待测压力大小并显示于一外接屏幕上。The
绝缘层23设置于半导体基材20上且覆盖压阻组件21。绝缘层23之材质例如是氧化硅(silicon oxide)、氮化硅(silicon nitride)、氮氧化硅(silicon oxynitride)等或其组合。The
本实施例之半导体压阻式传感器2更包括至少一内连接组件24,如图3A和图3B所示,半导体压阻式传感器2所包括之至少一内连接组件24例如是一第一内连接组件241与一第二内连接组件242,其分别电性连接于压阻组件21之两端,其中压阻组件21藉由第一内连接组件241与电路3电性连接,例如第一内连接组件241可用于与桥式电路中之其它组件连接(图未显示)。而绝缘层23藉由开设一开口231使电路3与第一内连接组件241电性连接。在本实施例中,内连接组件24例如是一p+型半导体层。The semiconductor piezoresistive sensor 2 of this embodiment further includes at least one
如图3A所示,导电材料层22设置于绝缘层23之上,藉由绝缘层23之另一开口232而使导电材料层22与悬膜201直接接触以电性连接,而悬膜201为原先之基材掺杂质浓度(N-)。导电材料层22与悬膜201接触之方式可为欧姆接触(ohmic contact)或肖特基接触(Schottky contact)。As shown in FIG. 3A, the
或者,如图3B所示,导电材料层22接触之区域为高掺杂质浓度区(p+)25。位于导电材料层22与悬膜201之间的p型掺杂区25,相对导电材料层22设置于悬膜201内,并藉由绝缘层23之开口232与导电材料层22形成欧姆接触或肖特基接触。p型掺杂区25所用之p型掺杂剂系为高掺杂浓度,故为p+型掺杂区。在此需特别注意的是,此一p+型掺杂区25并不需要外加额外的工序来达成,可在形成内连接组件24之工序中同时进行。Alternatively, as shown in FIG. 3B , the region in contact with the
不论是图3A或是图3B之半导体压阻式传感器2,均可透过适当的施加一电压V1+来控制悬膜(N-)201的电位,使悬膜(N-)201之电位不致随时间漂移,其中电压V1+可为压阻组件21之桥式电路电压(ex.VB+)或其它高于传感器桥式电路电压之电压(ex.来自温度补偿电路之Vs+),使得压阻组件21与悬膜201之接面形成一逆向偏压(reverse bias)或使P-N结不导通(跨于PN结的电压小于导通电压),即可将电流限制在电阻组件内部并可控制悬膜201电位,更进一步,透过如此结构布局设计及安排,可达改善压阻式传感器2输出讯号时漂的目的。Whether it is the semiconductor piezoresistive sensor 2 shown in FIG. 3A or FIG. 3B, the potential of the suspension film (N-) 201 can be controlled by applying a voltage V1+ appropriately, so that the potential of the suspension film (N-) 201 will not follow the Time drift, wherein the voltage V1+ can be the bridge circuit voltage (ex. VB+) of the
第二实施例second embodiment
请同时参照图4A与图4B,依据本发明第二实施例之一种半导体压阻式传感器4,其包括一半导体基材20、一绝缘层23、至少一压阻组件21、至少一内连接组件24以及一遮蔽层(Shield layer)26。半导体压阻式传感器4与一电路3电性连接,电路3例如是一桥式电路或一温度补偿电路。在本实施例中,半导体基材20、压阻组件21、内连接组件24、绝缘层23及电路3之结构特征、材质、设置方式、连接关系与功能皆如第一实施例所述,故不再赘述。Please refer to FIG. 4A and FIG. 4B at the same time. According to the second embodiment of the present invention, a semiconductor piezoresistive sensor 4 includes a
本实施例与第一实施例之差异在于,遮蔽层26设置于绝缘层23之上,且覆盖至少部分之本实施例之半导体压阻式传感器4并不具有导电材料层22,但比第一实施例多了一遮蔽层26。遮蔽层26设置于绝缘层23之上,且覆盖至少部分之绝缘层23并与悬膜201电性连接,更详细说,绝缘层23开设一开口232,遮蔽层26则藉由开口232与悬膜201直接接触以电性连接,而悬膜201为原先之基材掺杂质浓度(N-),如图4A所示。遮蔽层26与悬膜201接触之方式可为欧姆接触(ohmic contact)或肖特基接触(Schottkycontact)。遮蔽层26之材质为非绝缘材质,且其之热膨胀系数(thermalcoefficient of expansion,TCE)较佳地为介于-15ppm/℃至+15ppm/℃。The difference between this embodiment and the first embodiment is that the
或者,如图4B所示,遮蔽层26接触之区域为高掺杂质浓度区(p+)25。位于遮蔽层26与悬膜201之间的p型掺杂区25,相对遮蔽层26设置于悬膜201内,并藉由绝缘层23之开口232与遮蔽层26形成欧姆接触或肖特基接触。p型掺杂区25所用之p型掺杂剂系为高掺杂浓度,故为p+型掺杂区。在此需特别注意的是,此一p+型掺杂区25并不需要外加额外的工序来达成,可在形成内连接组件24之工序中同时进行。Alternatively, as shown in FIG. 4B , the area in contact with the
不论是图4A或是图4B之半导体压阻式传感器4,均可透过适当的施加一电压V2+来控制悬膜(N-)201的电位,使悬膜(N-)201之电位不致漂移。另外,透过遮蔽层26将绝缘层23下方的压阻组件21适当遮蔽,并施加电压V2+,以稳定压阻组件21上方的表面电位,使表面电位不致随时间漂移。其中电压V2+可为压阻组件21之桥式电路电压(如VB+)或其它高于传感器桥式电路电压之电压(如来自温度补偿电路之Vs+),使得压阻组件21与悬膜201之接面形成一逆向偏压(reverse bias)或使P-N结不导通(跨于PN结的电压小于导通电压),即可将电流限制在电阻组件内部并可控制悬膜201电位,更进一步,透过如此结构布局设计及安排,可达改善压阻式传感器4输出讯号时漂的目的。Whether it is the semiconductor piezoresistive sensor 4 shown in FIG. 4A or FIG. 4B, the potential of the suspension film (N-) 201 can be controlled by applying a voltage V2+ appropriately, so that the potential of the suspension film (N-) 201 will not drift . In addition, the
第三实施例third embodiment
请同时参照图5A与图5B,依据本发明第三实施例之一种半导体压阻式传感器5,其包括一半导体基材20、一绝缘层23、至少一压阻组件21、至少一内连接组件24、一导电材料层22以及一遮蔽层(Shield layer)26。半导体压阻式传感器5与一电路3电性连接,电路3例如是一桥式电路或一温度补偿电路。如图5B所示,半导体压阻式传感器2更包括一p型掺杂区25设置于22与悬膜201之间,在本实施例中,p型掺杂区25相对22设置于悬膜201内,并藉由绝缘层23之开口232与22形成欧姆接触或肖特基接触,其中p型掺杂区25系为高掺杂浓度,即p+型掺杂区。在本实施例中,半导体基材20、压阻组件21、内连接组件24、绝缘层23及电路3之结构特征、材质、设置方式、连接关系与功能皆如第一实施例所述,故不再赘述。Please refer to FIG. 5A and FIG. 5B at the same time, according to a semiconductor piezoresistive sensor 5 according to the third embodiment of the present invention, it includes a
本实施例与第一及第二实施例之差异在于,本实施例之半导体压阻式传感器5同时具有导电材料层22以及遮蔽层26。导电材料层22设置于绝缘层23之上,藉由绝缘层23之另一开口232而使导电材料层22与悬膜201直接接触以电性连接,而悬膜201为原先之基材掺杂质浓度(N-)。导电材料层22与悬膜201接触之方式可为欧姆接触(ohmic contact)或肖特基接触(Schottky contact),如图5A所示。另外,本实施例之半导体压阻式传感器5更包括一遮蔽层26设置于绝缘层23之上,且覆盖至少部分之绝缘层23,其中遮蔽层26之材质为非绝缘材质,且其之热膨胀系数(thermalcoefficient of expansion,TCE)较佳地系介于-15ppm/℃至+15ppm/℃,以避免遮蔽层26与半导体基材20因热膨胀系数差异过大使半导体压阻式传感器5有较大的零点输出(offset)及热规格(如TCO),亦可避免机械迟滞(mechanical hysteresis)现象的发生。于此,如图5所示,遮蔽层26与导电材料层22不相导通,但依据电路之设计,遮蔽层26亦可与导电材料层22相互电性连接。The difference between this embodiment and the first and second embodiments is that the semiconductor piezoresistive sensor 5 of this embodiment has both a
或者,如图5B所示,导电材料层22接触之区域为高掺杂质浓度区(p+)25。位于导电材料层22与悬膜201之间的p型掺杂区25,相对导电材料层22设置于悬膜201内,并藉由绝缘层23之开口232与导电材料层22形成欧姆接触或肖特基接触。p型掺杂区25所用之p型掺杂剂系为高掺杂浓度,故为p+型掺杂区。在此需特别注意的是,此一p+型掺杂区25并不需要外加额外的工序来达成,可在形成内连接组件24之工序中同时进行。Alternatively, as shown in FIG. 5B , the region in contact with the
不论是图5A或是图5B之半导体压阻式传感器5,均可透过适当的施加一电压V4+来控制悬膜(N-)201的电位,使悬膜(N-)201之电位不致漂移。另外,透过遮蔽层26将绝缘层23下方的压阻组件21适当遮蔽,并施加电压V3+,以稳定压阻组件21上方的表面电位,使表面电位不致随时间漂移。其中电压V3+、V4+可为压阻组件21之桥式电路电压(ex.VB+)或其它高于传感器桥式电路电压之电压(ex.来自温度补偿电路之Vs+),使得压阻组件21与悬膜201之接面形成一逆向偏压(reverse bias)或使P-N结不导通(跨于PN接面的电压小于导通电压),即可将电流限制在电阻组件内部并可控制悬膜201电位,更进一步,透过如此结构布局设计及安排,可达改善压阻式传感器5输出讯号时漂的目的。Regardless of the semiconductor piezoresistive sensor 5 shown in Figure 5A or Figure 5B, the potential of the suspension film (N-) 201 can be controlled by applying a voltage V4+ appropriately, so that the potential of the suspension film (N-) 201 will not drift . In addition, the
依据本发明较佳实施例之一种半导体压阻式传感器之操作方法,其应用于如图3A与图3B所示之半导体压阻式传感器2,操作方法包括下列步骤:施加一电压V1于导电材料层22以及施加一电压V0于电路3,当电压V0减掉电压V1所得之值小于压阻组件21与悬膜201之间的导通电压时,压阻组件21与悬膜201之接面便可形成逆向偏压或使P-N结不导通,进而达到将电流限制在压阻组件21内部,可达改善压阻式传感器2输出讯号时漂的目的。其中,电压V0或电压V1可为连接半导体压阻式传感器2之桥式电路或温度补偿电路之电压,或是高于桥式电路或温度补偿电路之电压。An operating method of a semiconductor piezoresistive sensor according to a preferred embodiment of the present invention is applied to the semiconductor piezoresistive sensor 2 shown in Figure 3A and Figure 3B, the operating method includes the following steps: applying a voltage V1 to the
依据本发明较佳实施例之再一种半导体压阻式传感器之操作方法,其应用于如图4A与图4B所示之半导体压阻式传感器4,操作方法包括下列步骤:施加一电压V2于遮蔽层26以及施加一电压V0于电路3,当电压V0减掉电压V1所得之值小于压阻组件21与悬膜201之间的导通电压时,压阻组件21与悬膜201之接面便可形成逆向偏压或使P-N结不导通,同时利用施加于遮蔽层26之电压V2稳定压阻组件21上方之表面电位,进而达到将电流限制在压阻组件21内部,可达改善压阻式传感器4输出讯号时漂的目的。其中电压V0或电压V2例如是桥式电路或温度补偿电路之电压,或是高于桥式电路或温度补偿电路之电压。Another method of operating a semiconductor piezoresistive sensor according to a preferred embodiment of the present invention is applied to the semiconductor piezoresistive sensor 4 shown in FIG. 4A and FIG. 4B. The operating method includes the following steps: applying a voltage V2 to The
依据本发明较佳实施例之另一种半导体压阻式传感器之操作方法,其应用于如图5A与图5B所示之半导体压阻式传感器5,操作方法包括下列步骤:施加一电压V4于导电材料层22、施加一电压V0于电路3以及施加一电压V3于遮蔽层26,当电压V0减掉电压V4所得之值小于压阻组件21与悬膜201之间的导通电压时,压阻组件21与悬膜201之接面便可形成逆向偏压或使P-N结不导通,进而达到将电流限制在压阻组件21内部,可达改善压阻式传感器5输出讯号时漂的目的。其中电压V0、电压V3或电压V4例如是桥式电路或温度补偿电路之电压,或是高于桥式电路或温度补偿电路之电压。Another method of operating a semiconductor piezoresistive sensor according to a preferred embodiment of the present invention is applied to the semiconductor piezoresistive sensor 5 shown in FIG. 5A and FIG. 5B. The operating method includes the following steps: applying a voltage V4 to
综上所述,因依据本发明之半导体压阻式传感器及其操作方法,其利用一导电材料层或一遮蔽层与半导体基材之悬膜电性连接,其中导电材料层与遮蔽层分别由导电材质与非绝缘材质所构成,将此半导体压阻式传感器架构于一电路中,藉由施加于导电材料层或遮蔽层适当电压,使其与施加于电路上之电压差低于压阻组件与悬膜之导通电压,所以压阻组件与悬膜之接面不导通而限制电流于压阻组件内,进而改善压阻组件输出讯号随时间漂移之现象。与习知技术相较,本发明不需于半导体基材上形成与压阻组件不同型式之半导体掺杂区,所以有效简化工序步骤,降低制造成本,进而提高半导体压阻式传感器量测之准确度。In summary, according to the semiconductor piezoresistive sensor and its operating method of the present invention, it utilizes a conductive material layer or a shielding layer to be electrically connected to the suspension film of the semiconductor substrate, wherein the conductive material layer and the shielding layer are composed of Composed of conductive materials and non-insulating materials, the semiconductor piezoresistive sensor is constructed in a circuit, and by applying an appropriate voltage to the conductive material layer or shielding layer, the voltage difference between it and the circuit is lower than that of the piezoresistive component The conduction voltage with the suspension film, so the junction between the piezoresistive component and the suspension film is not conductive to limit the current in the piezoresistive component, thereby improving the phenomenon that the output signal of the piezoresistive component drifts with time. Compared with the conventional technology, the present invention does not need to form a semiconductor doped region different from the piezoresistive element on the semiconductor substrate, so the process steps are effectively simplified, the manufacturing cost is reduced, and the measurement accuracy of the semiconductor piezoresistive sensor is improved. Spend.
以上所述仅为举例性,而非为限制性者。任何未脱离本发明之精神与范畴,而对其进行之等效修改或变更,均应包含于后附之权利要求书中。The above descriptions are illustrative only, not restrictive. Any equivalent modifications or changes made without departing from the spirit and scope of the present invention shall be included in the appended claims.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102336391A (en) * | 2010-06-22 | 2012-02-01 | 罗伯特·博世有限公司 | Method for manufacturing piezoresistive sensor device and sensor device |
CN104280182A (en) * | 2013-07-02 | 2015-01-14 | 阿尔卑斯电气株式会社 | Physical quantity sensor |
CN110330675A (en) * | 2019-06-19 | 2019-10-15 | 天津市职业大学 | A kind of preparation method of pressure-sensitive film, pressure-sensitive film and pressure sensor |
CN117030078A (en) * | 2023-08-10 | 2023-11-10 | 无锡胜脉电子有限公司 | Silicon force sensitive chip and preparation method and packaging method thereof |
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CN102336391A (en) * | 2010-06-22 | 2012-02-01 | 罗伯特·博世有限公司 | Method for manufacturing piezoresistive sensor device and sensor device |
CN102336391B (en) * | 2010-06-22 | 2015-12-16 | 罗伯特·博世有限公司 | For the manufacture of method and the sensor device of the sensor device of pressure drag |
CN104280182A (en) * | 2013-07-02 | 2015-01-14 | 阿尔卑斯电气株式会社 | Physical quantity sensor |
CN104280182B (en) * | 2013-07-02 | 2017-01-04 | 阿尔卑斯电气株式会社 | Physical quantity transducer |
CN110330675A (en) * | 2019-06-19 | 2019-10-15 | 天津市职业大学 | A kind of preparation method of pressure-sensitive film, pressure-sensitive film and pressure sensor |
CN117030078A (en) * | 2023-08-10 | 2023-11-10 | 无锡胜脉电子有限公司 | Silicon force sensitive chip and preparation method and packaging method thereof |
CN117030078B (en) * | 2023-08-10 | 2024-03-15 | 无锡胜脉电子有限公司 | Silicon force sensitive chip and preparation method and packaging method thereof |
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