CN116192159A - LDPC coding and decoding method and system equipment medium based on FPGA - Google Patents
LDPC coding and decoding method and system equipment medium based on FPGA Download PDFInfo
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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Abstract
The invention discloses an LDPC coding and decoding method and system equipment medium based on an FPGA, which are characterized in that original data are stored in a local buffer area, and shift exclusive-OR calculation and exclusive-OR operation are sequentially carried out on the data in the buffer area to generate coding check data; storing the original data and the encoding verification data into a RAM0_0, and simultaneously storing the addresses of the offset polynomials into a node update RAM1 according to the loaded decoding polynomials, wherein the data in each RAM is a submatrix; performing check node update on the data in the RAM1, and writing the updated data into the RAM 1; combining the data updated by the check node in the RAM1 with the original information of the RAM0 to update the variable node, and writing the updated data into the RAM 1; and iterating the node updating until the set iteration times are reached, and outputting decoding data. It can be supported that the coding parameters are configurable, and that the submatrix size and the polynomials are not limited.
Description
Technical Field
The invention belongs to the field of encoding and decoding, and relates to an LDPC encoding and decoding method and system equipment medium based on an FPGA.
Background
In the era of the prevalence of digital communication technology, the reliability of data transmission has become a necessary research direction; in the wireless communication process, the correctness of data transmission needs to be ensured; channel coding becomes an indispensable technology in the wireless communication process, and meanwhile, in order to reduce the bandwidth resource utilization rate in the communication process, an optimal channel coding technology needs to be selected, so that the data transmission efficiency is improved; LDPC (Low-Density parity-check (Low-Density Parity Check) code) channel coding has better error correction capability and transmission efficiency, and is applied to many wireless communication systems.
The LDPC coding algorithm based on the FPGA is realized, and has the advantages of smaller coding delay, configurable coding polynomial parameters, easiness in realization, better coding gain and less FPGA resources, but the conventional LDPC coding technology polynomial configuration realized by the FPGA is limited and is not flexible enough, only has several optional parameter configurations, and the conventional FPGA realization technology is insufficient for meeting the subsequent communication system, and has higher and higher requirements on the communication system.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides an LDPC coding and decoding method and system equipment medium based on an FPGA, which can support coding and decoding parameter matching, and the size of a submatrix and a polynomial are not limited.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
an LDPC coding and decoding method based on FPGA comprises the following steps:
s1, receiving externally input bit information as original data, and respectively storing the original data into local cache areas, wherein the number of the cache areas is 12, and the size of the cache areas is Z; performing shift exclusive OR calculation on the data of each buffer area according to the coding polynomial to generate 12 coding buffer data; performing exclusive OR operation on the 12 coded cache data according to a coding algorithm to generate 12 coded check data;
s2, storing 12 original data and 12 coded check data into 24 RAM0_0 respectively according to the sequence, and simultaneously storing the 12 original data and the 12 coded check data into 76 node updating RAMs 1 according to the loaded decoding polynomials, wherein the data in each RAM is a submatrix;
s3, updating check nodes of the data in the 76 RAMs 1, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAMs 1;
s4, combining the data updated by the check nodes in the RAM1 with the original information of the RAM0 to update variable nodes, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAM 1;
s5, iterating the processes of S3 and S4 until the set iteration times are reached, and outputting decoded data.
Preferably, in S1, the length of the input original data is 12×z, the coding delay is 13×z clock cycles, and the length of the generated coded check data is 24×z.
Preferably, in S3, the number of check node updating parallel calculations is 12, that is, the number of row submatrices, and the number of serial calculations is the size of the submatrices.
Preferably, in S3, the process of updating the check node is: the number of the input data is the number of the non-zero submatrices of each row of the polynomial, the absolute value of the input data and the sign bits except the input data are accumulated, the minimum value except the input data is obtained, the minimum value information is subjected to sign conversion according to the accumulated sign bits, and updated check node information is output.
Preferably, in S4, the number of parallel computation of variable node update is 24, that is, the number of column submatrices, and the number of serial computation is the size of the submatrices.
Preferably, in S4, the variable node updating process is as follows: the number of the input data is the number of the non-zero submatrices in each column of the polynomial, all the input data are accumulated, and the accumulated data minus the current data value is the current node update value; the sign bit of the accumulated sum is the decoded data information.
Preferably, after outputting the decoded data, the check node update and the variable node update share the RAM1.
An FPGA-based LDPC coding system comprising:
the coding module is used for receiving externally input bit information as original data, and storing the original data into local cache areas respectively, wherein the number of the cache areas is 12, and the size of the cache area is Z; performing shift exclusive OR calculation on the data of each buffer area according to the coding polynomial to generate 12 coding buffer data; performing exclusive OR operation on the 12 coded cache data according to a coding algorithm to generate 12 coded check data;
the data storage module is used for storing 12 original data and 12 coded check data into 24 RAMs 0_0 respectively according to the sequence, and simultaneously storing the 12 original data and the 12 coded check data into 76 node updating RAMs 1 according to the loaded decoding polynomials, wherein the data in each RAM is a submatrix;
the check node updating module is used for updating check nodes of the data in the 76 RAMs 1, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAMs 1;
the variable node updating module is used for combining the data updated by the check node in the RAM1 with the original information of the RAM0 to update the variable node, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAM 1;
and the iteration module is used for iterating the processes of S3 and S4 until the set iteration times are reached, and outputting decoded data.
A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the FPGA-based LDPC coding method when the computer program is executed.
A computer readable storage medium storing a computer program which when executed by a processor implements the steps of the FPGA-based LDPC coding method.
Compared with the prior art, the invention has the following beneficial effects:
the invention can realize flexible configuration of the sub-matrix size and polynomials of the LDPC coding and decoding algorithm, and the coding adopts the form of sub-matrix cyclic shift accumulation to carry out coding, thereby having high coding efficiency, small delay and low resource utilization rate. When LDPC decoding is realized, a posterior probability logarithmic domain belief propagation decoding algorithm which is easy to realize is adopted, FPGA logic is easy to realize, and the resource utilization rate is low; when the node verification is carried out, a method combining serial and parallel calculation is adopted, so that the resource and the time delay reach an optimal solution; the data storage in the decoding process adopts a mode of sharing a dual-port RAM, so that the data updating and storage are more flexible; the data calculation adopts 24 bits to calculate, thereby reducing the loss of data precision and having better decoding gain.
Drawings
FIG. 1 is a schematic diagram of the composition of an LDPC encoding and decoding algorithm based on an FPGA of the present invention;
FIG. 2 is a flow chart of LDPC encoding implemented by the FPGA of the present invention;
FIG. 3 is a flow chart of LDPC decoding implemented by the FPGA of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention; all other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings, and the words "inner" and "outer" refer to directions toward or away from, respectively, the geometric center of a particular component.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in FIG. 1, the LDPC coding algorithm composition structure based on the FPGA is provided.
The LDPC coding algorithm based on the FPGA realizes coding and decoding of wireless communication transmission data, realizes an error correction function of a system and improves the accuracy of the transmission data of the system; the LDPC coding and decoding algorithm based on the FPGA mainly comprises a parameter configuration module, a coding module, a decoding module, a data storage module, a check node updating module and a variable node updating module.
The parameter configuration module mainly comprises a submatrix size (Z) parameter, a decoding iteration number parameter and a coding and decoding polynomial parameter; it is noted that the polynomial parameter value is smaller than the value of the sub-matrix size, and if it is larger, the value of the sub-matrix size needs to be subtracted until it is smaller than the value of the sub-matrix size.
The coding module performs data coding in a cyclic shift accumulation mode, the input data length is 12×Z, the coding delay is 13×Z clock cycles, and the output data length is 24×Z.
The decoding algorithm of the decoding module is a posterior probability logarithmic domain belief propagation algorithm, wherein the data storage module, the check node updating module and the variable node updating module form the whole decoding module; soft information input is adopted in decoding, and iterative decoding is carried out; the operation process is serial-parallel combination, each calculation is carried out for one row or column of each submatrix, the number of parallel calculations is 12/24, and the number of serial calculations is Z, so that the resource and the speed reach the optimal solution.
The process realized by adopting the FPGA comprises the following steps:
the FPGA implementation encoding flow diagram is shown in figure 2. The encoding module receives externally input bit information as original data, and respectively stores the bit information into local cache areas, wherein the number of the cache areas is 12, and the size of the cache areas is Z; performing shift exclusive OR calculation on the data of each buffer area according to the coding polynomial to generate 12 coding buffer data; and performing exclusive OR operation on the 12 coded cache data according to the coding algorithm to generate 12 coded check data, packaging and combining the original data and the coded check data, and outputting the packaged and combined data to an external interface.
The FPGA implementation decoding flow chart is shown in fig. 3. The decoding module receives externally input soft demodulation information, and inputs 12 original data and 12 coding verification data into the data storage module, wherein the original data and node update data of the data storage module are stored separately, so that node update in the decoding process is facilitated; the data storage module stores 24 RAMs of original data, wherein the depth is Z, and the bit width is 24 bits; the node update RAM1 is 76, the depth is Z, and the bit width is 24 bits.
Inputting 12 original data and 12 coded check data into a data storage module, and storing the data into a RAM 0-23 respectively according to the sequence, and updating the variable nodes to be used; and simultaneously storing 12 original data and 12 coded check data into a node update RAM 1-0-RAM 1-75 according to the loaded decoding polynomial, returning the address to zero when the RAM1 is Z, and writing data information for checking the initial value of the node update.
The decoding process, the check node reads the initial value information of the RAM1_0-RAM1_75, the check node is updated, and the updated data is written into the RAM1_0-RAM1_75; the variable node reads the data updated by the check node in the RAM1_0-RAM1_75 and the original information of the RAM0_0-RAM0_23 to update the variable node, and the updated data is written into the RAM1_0-RAM1_75 for the next iteration initial value.
After the decoding iteration is completed, outputting decoded data information, and updating the check node and the variable node to share the RAM1 so as to optimize the resource utilization rate, wherein the iteration times in the embodiment are 6-8 times.
Iterative decoding is adopted in the decoding process, the iterative times can be configured through parameters, the decoding process is serial-parallel combined decoding, parallel computation is carried out among each sub-matrix, and serial computation is carried out on data in each sub-matrix; the decoding process firstly carries out check node updating and then variable node updating, and one check node updating and one variable node updating are carried out as one iteration process, so that the method reduces the complexity of the algorithm, and iterative decoding is completed by using minimum decoding delay and optimal resources.
In the decoding process, the number of check node parallel calculation is 12, namely the number of row submatrices, and the number of serial calculation is the size of the submatrices; the number of parallel computation of the variable nodes is 24, namely the number of column submatrices, and the number of serial computation is the size of the submatrices.
And in the check node updating process, the number of input data is the number of non-zero submatrices of each row of polynomials, absolute values of the input data and sign bits except the input data are accumulated, the minimum value except the input data is obtained, the minimum value information is subjected to sign conversion according to the accumulated sign bits, and updated check node information is output.
In the variable node updating process, the number of input data is the number of non-zero submatrices in each column of the polynomial, all the input data are accumulated, and the accumulated data minus the current data value is the current node updating value; the sign bit of the accumulated sum is the decoded data information.
The invention adopts FPGA to realize the encoding and decoding algorithm of LDPC 1/2 code, and the size parameters of the submatrix can be matched; the configuration of coding and decoding parameters adopts external input constants for configuration, including check polynomials, submatrix sizes and decoding iteration times; the LDPC coding adopts a shift accumulation coding mode for coding, the method is simple to realize, and the resource utilization rate is low; the encoding process loads parameter constants such as encoding polynomials and submatrix sizes; the LDPC decoding algorithm adopts a simple posterior probability pair number domain belief propagation algorithm to carry out decoding operation, and has better decoding gain; the decoding algorithm FPGA is simple to realize, reduces the complexity of logic realization, and reduces a large amount of complex calculation; in the decoding process, the data storage adopts a shared dual-port RAM mode, so that the data storage is realized, and the use of logic resources is greatly reduced; the node updating process in decoding is realized in a serial-parallel combination mode, so that the resource utilization and decoding speed are improved greatly; and the check node and variable node updating are realized by adopting an accumulated and compared decoding algorithm, so that the realization is simple and the operand is small.
The invention can support the encoding and decoding parameters to be matched, and the size of the submatrix and the polynomial are not limited; the configurable decoding iteration number can be supported, and the decoding iteration number is increased or decreased according to the requirement; higher decoding gain can be obtained; fewer resources may be used to implement the decode operation and less decode latency.
When LDPC decoding is realized, a posterior probability logarithmic domain belief propagation decoding algorithm which is easy to realize is adopted, FPGA logic is easy to realize, and the resource utilization rate is low; when the node verification is carried out, a method combining serial and parallel calculation is adopted, so that the resource and the time delay reach an optimal solution; the data storage in the decoding process adopts a mode of sharing a dual-port RAM, so that the data updating and storage are more flexible; the data calculation adopts 24 bits to calculate, thereby reducing the loss of data precision and having better decoding gain.
The following are device embodiments of the present invention that may be used to perform method embodiments of the present invention. For details of the device embodiment that are not careless, please refer to the method embodiment of the present invention.
In still another embodiment of the present invention, an FPGA-based LDPC coding system is provided, which may be used to implement the above-mentioned FPGA-based LDPC coding method, and in particular, the FPGA-based LDPC coding system includes a coding module, a data storage module, a check node update module, a variable node update module, and an iteration module.
The encoding module is used for receiving externally input bit information as original data, storing the original data into local cache areas respectively, wherein the number of the cache areas is 12, and the size of the cache area is Z; performing shift exclusive OR calculation on the data of each buffer area according to the coding polynomial to generate 12 coding buffer data; and performing exclusive OR operation on the 12 coded cache data according to the coding algorithm to generate 12 coded check data.
The data storage module is used for storing 12 original data and 12 coded check data into 24 RAM0_0 respectively according to the sequence, and simultaneously storing the 12 original data and the 12 coded check data into 76 nodes for updating the RAM1 according to the loaded decoding polynomial, wherein the data in each RAM is a submatrix.
The check node updating module is used for performing check node updating on the data in the 76 RAMs 1, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAMs 1.
The variable node updating module is used for combining the data updated by the check node in the RAM1 with the original information of the RAM0 to update the variable node, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAM1.
The iteration module is used for iterating the processes of S3 and S4 until the set iteration times are reached, and outputting decoded data.
In yet another embodiment of the present invention, a terminal device is provided, the terminal device including a processor and a memory, the memory for storing a computer program, the computer program including program instructions, the processor for executing the program instructions stored by the computer storage medium. The processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf Programmable gate arrays (FPGAs) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., which are the computational core and control core of the terminal adapted to implement one or more instructions, in particular adapted to load and execute one or more instructions to implement a corresponding method flow or a corresponding function; the processor according to the embodiment of the invention can be used for the operation of the LDPC coding and decoding method based on the FPGA, and comprises the following steps: s1, receiving externally input bit information as original data, and respectively storing the original data into local cache areas, wherein the number of the cache areas is 12, and the size of the cache areas is Z; performing shift exclusive OR calculation on the data of each buffer area according to the coding polynomial to generate 12 coding buffer data; performing exclusive OR operation on the 12 coded cache data according to a coding algorithm to generate 12 coded check data; s2, storing 12 original data and 12 coded check data into 24 RAM0_0 respectively according to the sequence, and simultaneously storing the 12 original data and the 12 coded check data into 76 node updating RAMs 1 according to the loaded decoding polynomials, wherein the data in each RAM is a submatrix; s3, updating check nodes of the data in the 76 RAMs 1, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAMs 1; s4, combining the data updated by the check nodes in the RAM1 with the original information of the RAM0 to update variable nodes, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAM 1; s5, iterating the processes of S3 and S4 until the set iteration times are reached, and outputting decoded data.
In still another embodiment, the present invention also provides a computer-readable storage medium (Memory) that is a Memory device in a terminal device for storing programs and data. It will be appreciated that the computer readable storage medium herein may include both a built-in storage medium in the terminal device and an extended storage medium supported by the terminal device. The computer-readable storage medium provides a storage space storing an operating system of the terminal. Also stored in the memory space are one or more instructions, which may be one or more computer programs (including program code), adapted to be loaded and executed by the processor. The computer readable storage medium herein may be a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.
One or more instructions stored in a computer-readable storage medium may be loaded and executed by a processor to implement the respective steps of the FPGA-based LDPC coding method in the above embodiments; one or more instructions in a computer-readable storage medium are loaded by a processor and perform the steps of: s1, receiving externally input bit information as original data, and respectively storing the original data into local cache areas, wherein the number of the cache areas is 12, and the size of the cache areas is Z; performing shift exclusive OR calculation on the data of each buffer area according to the coding polynomial to generate 12 coding buffer data; performing exclusive OR operation on the 12 coded cache data according to a coding algorithm to generate 12 coded check data; s2, storing 12 original data and 12 coded check data into 24 RAM0_0 respectively according to the sequence, and simultaneously storing the 12 original data and the 12 coded check data into 76 node updating RAMs 1 according to the loaded decoding polynomials, wherein the data in each RAM is a submatrix; s3, updating check nodes of the data in the 76 RAMs 1, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAMs 1; s4, combining the data updated by the check nodes in the RAM1 with the original information of the RAM0 to update variable nodes, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAM 1; s5, iterating the processes of S3 and S4 until the set iteration times are reached, and outputting decoded data.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are incorporated herein by reference for the purpose of completeness. The omission of any aspect of the subject matter disclosed herein in the preceding claims is not intended to forego such subject matter, nor should the applicant not be considered to be a part of the disclosed subject matter.
Claims (10)
1. An LDPC coding and decoding method based on FPGA is characterized by comprising the following steps:
s1, receiving externally input bit information as original data, and respectively storing the original data into local cache areas, wherein the number of the cache areas is 12, and the size of the cache areas is Z; performing shift exclusive OR calculation on the data of each buffer area according to the coding polynomial to generate 12 coding buffer data; performing exclusive OR operation on the 12 coded cache data according to a coding algorithm to generate 12 coded check data;
s2, storing 12 original data and 12 coded check data into 24 RAM0_0 respectively according to the sequence, and simultaneously storing the 12 original data and the 12 coded check data into 76 node updating RAMs 1 according to the loaded decoding polynomials, wherein the data in each RAM is a submatrix;
s3, updating check nodes of the data in the 76 RAMs 1, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAMs 1;
s4, combining the data updated by the check nodes in the RAM1 with the original information of the RAM0 to update variable nodes, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAM 1;
s5, iterating the processes of S3 and S4 until the set iteration times are reached, and outputting decoded data.
2. The FPGA-based LDPC coding method according to claim 1, wherein in S1, the input original data length is 12×z, the coding delay is 13×z clock cycles, and the generated code check data length is 24×z.
3. The FPGA-based LDPC coding method as claimed in claim 1, wherein in S3, the number of check node updating parallel calculations is 12, that is, the number of row submatrices, and the number of serial calculations is the size of the submatrices.
4. The FPGA-based LDPC coding method of claim 1, wherein in S3, the process of updating the check node is: the number of the input data is the number of the non-zero submatrices of each row of the polynomial, the absolute value of the input data and the sign bits except the input data are accumulated, the minimum value except the input data is obtained, the minimum value information is subjected to sign conversion according to the accumulated sign bits, and updated check node information is output.
5. The FPGA-based LDPC coding method as claimed in claim 1, wherein in S4, the number of parallel calculations of variable node update is 24, that is, the number of column submatrices, and the number of serial calculations is the size of the submatrices.
6. The FPGA-based LDPC coding method of claim 1, wherein in S4, the variable node updating process is: the number of the input data is the number of the non-zero submatrices in each column of the polynomial, all the input data are accumulated, and the accumulated data minus the current data value is the current node update value; the sign bit of the accumulated sum is the decoded data information.
7. The FPGA-based LDPC coding method as claimed in claim 1, wherein after outputting the decoded data, the check node update and the variable node update share the RAM1.
8. An LDPC coding system based on an FPGA, comprising:
the coding module is used for receiving externally input bit information as original data, and storing the original data into local cache areas respectively, wherein the number of the cache areas is 12, and the size of the cache area is Z; performing shift exclusive OR calculation on the data of each buffer area according to the coding polynomial to generate 12 coding buffer data; performing exclusive OR operation on the 12 coded cache data according to a coding algorithm to generate 12 coded check data;
the data storage module is used for storing 12 original data and 12 coded check data into 24 RAMs 0_0 respectively according to the sequence, and simultaneously storing the 12 original data and the 12 coded check data into 76 node updating RAMs 1 according to the loaded decoding polynomials, wherein the data in each RAM is a submatrix;
the check node updating module is used for updating check nodes of the data in the 76 RAMs 1, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAMs 1;
the variable node updating module is used for combining the data updated by the check node in the RAM1 with the original information of the RAM0 to update the variable node, performing parallel computation among each sub-matrix, performing serial computation on the data in each sub-matrix, and writing the updated data into the RAM 1;
and the iteration module is used for iterating the processes of S3 and S4 until the set iteration times are reached, and outputting decoded data.
9. Computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the FPGA-based LDPC coding method as claimed in any of claims 1 to 7 when the computer program is executed.
10. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the steps of the FPGA-based LDPC coding method of any of claims 1 to 7.
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