CN109274460A - Multi-bit parallel structure serial cancellation decoding method and device - Google Patents

Abstract

The embodiment of the invention provides a kind of multi-bit parallel structures serially to offset interpretation method and device, f operation and g operation are carried out respectively to the data in data to decode frame, obtain corresponding operation result data, according to the first default enable signal and the second default enable signal, segmented result data are determined from operation result data, according to default acceleration computation rule and segmented result data, obtain target data, using target data as the corresponding decoding data of data to decode frame, and judge whether currently available decoding data reaches the code length for stating data to decode frame, if not, enable signal is preset according to updating target data first, and continue according to the first default enable signal and the second default enable signal, segmented result data are determined from operation result data.Based on above-mentioned processing, the merging of the calculate node of part stage is realized using default acceleration computation rule, and then can reduce the time delay of decoding.

Description

Multi-bit parallel structure serial cancellation decoding method and device

Technical field

The present invention relates to the field of communications technologies, and in particular, to a multi-bit parallel structure serial cancellation decoding method and apparatus.

Background technique

The polarization code is a constructive channel coding method that can achieve the channel capacity. The original data is encoded according to the polarization code, and the encoded data frame (which may be referred to as a data frame to be decoded) can be obtained. Correspondingly, the data frame to be decoded can be decoded according to a Successive Cancellation (SC) decoding method to obtain decoded data.

Referring to FIG. 1, FIG. 1 is a schematic diagram of a prior art serial cancellation decoding method, where i=0,1,2...7 represents the bit likelihood ratio data in the data frame to be decoded, that is, the code length of the data frame to be decoded is 8, j = 0, 1, 2...7, which represent decoded data outputted in different clock cycles. The entire decoding process is completed by compute nodes at different stages, including the compute nodes of Phase 1, Phase 2, and Phase 3. The hollow dot indicates that the calculation node performs the f operation, the solid dot indicates that the calculation node performs the g operation, and the g operation can be further divided into the g-operation and the g+ operation. The formula for f operation is: f(A, B)=sgn[A]×sgn[B]·min[|A|,|B|], and the formula for g operation is: g(A, B)=(-1 ^M A+B, A and B represent two bit likelihood ratio data in the data frame to be decoded, M is 1 for g-operation, M is 0 for g+ operation, sgn is for symbol function, min is for minimum value function. t, t+1, t+2, ... t+14 represent different clock cycles. It can be seen that the input of the g operation of the t+3 clock cycles includes the decoded data of the t+2 clock cycles. Based on Determine the operation mode of the g operation; the input of the g operation of the t+4 clock cycles includes the decoded data of the t+2 clock cycles Decoded data with t+3 clock cycles And to determine the operation of the g operation.

It can be seen that each computing node can only obtain the result of one operation in one clock cycle, and only after calculating the decoding data corresponding to the previous clock cycle, can the determined clock be determined according to the calculated decoding data. The operation of the g operation of the cycle, which in turn leads to a longer delay in the entire decoding process.

Summary of the invention

An object of the embodiments of the present invention is to provide a multi-bit parallel structure serial cancellation decoding method and apparatus, which can reduce the delay of the decoding process. The specific technical solutions are as follows:

In a first aspect, in order to achieve the above object, an embodiment of the present invention discloses a multi-bit parallel structure serial cancellation decoding method, where the method includes:

Obtaining a data frame to be decoded, performing f operation and g operation on the data in the data frame to be decoded, respectively, to obtain corresponding operation result data;

Determining candidate result data from the operation result data according to the first preset enable signal and the second preset enable signal;

And obtaining, according to the preset acceleration calculation rule and the candidate result data, the target acceleration data, wherein the preset acceleration calculation rule is obtained by simplifying operation manners of a preset number of calculation nodes;

Determining, by using the target data, the decoded data corresponding to the data frame to be decoded, and determining whether the currently obtained decoded data reaches the code length of the data frame to be decoded;

If not, updating the first preset enable signal according to the target data, and performing determining, according to the first preset enable signal and the second preset enable signal, the candidate result data from the operation result data step.

Optionally, the determining, according to the first preset enable signal and the second preset enable signal, the candidate result data from the operation result data, including:

If the second preset enable signal is currently low, determining the operation result data corresponding to the f operation as the candidate result data;

If the second preset enable signal is currently at a high level, the candidate result data is determined from the operation result data corresponding to the g operation according to the first preset enable signal.

Optionally, the obtaining the target data according to the preset acceleration calculation rule and the candidate result data, including:

Calculating the candidate result data according to a preset acceleration calculation rule to obtain accelerated calculation result data;

Performing an AND operation on the acceleration calculation result data and the preset correction data to obtain target data.

Optionally, the updating the first preset enable signal according to the target data includes:

Partially summing the target data to obtain a partial and result data;

And determining the partial and result data as the current signal value of the first preset enable signal.

Optionally, the second preset enable signal is determined according to a code length of the data frame to be decoded and a preset period algorithm.

In a second aspect, in order to achieve the above object, an embodiment of the present invention discloses a multi-bit parallel structure serial cancellation decoding apparatus, where the apparatus includes:

a calculation module, configured to acquire a data frame to be decoded, perform f operation and g operation on the data in the data frame to be decoded, respectively, to obtain corresponding operation result data;

a determining module, configured to determine candidate result data from the operation result data according to the first preset enable signal and the second preset enable signal;

An obtaining module, configured to obtain target data according to the preset acceleration calculation rule and the candidate result data, wherein the preset acceleration calculation rule is obtained by simplifying operation manners of a preset number of calculation nodes;

a determining module, configured to use the target data as the decoded data corresponding to the data frame to be decoded, and determine whether the currently obtained decoded data reaches a code length of the data frame to be decoded;

a processing module, if not, updating the first preset enable signal according to the target data, and executing the first preset enable signal and the second preset enable signal from the operation result data Determine the alternative result data steps.

Optionally, the determining module is specifically configured to: if the second preset enable signal is currently low, determine the operation result data corresponding to the f operation as the candidate result data;

If the second preset enable signal is currently at a high level, the candidate result data is determined from the operation result data corresponding to the g operation according to the first preset enable signal.

Optionally, the acquiring module is specifically configured to calculate, according to a preset acceleration calculation rule, the candidate result data, to obtain accelerated calculation result data;

Performing an AND operation on the acceleration calculation result data and the preset correction data to obtain target data.

Optionally, the processing module is specifically configured to obtain a partial sum of the target data, to obtain a partial part and result data;

And determining the partial and result data as the current signal value of the first preset enable signal.

Optionally, the second preset enable signal is determined according to a code length of the data frame to be decoded and a preset period algorithm.

In still another aspect of the present invention, in order to achieve the above object, an embodiment of the present invention discloses a terminal, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, the The memory completes communication with each other through the communication bus;

The memory is configured to store a computer program;

The processor, when used to execute a program stored on the memory, implements any of the method steps described above.

In still another aspect of the present invention, a computer readable storage medium is provided, wherein the computer readable storage medium stores instructions that, when run on a computer, cause the computer to perform the method of any of the above step.

In yet another aspect of the present invention, an embodiment of the present invention further provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method steps of any of the above.

The multi-bit parallel structure serial cancellation decoding method and device provided by the embodiment of the present invention can obtain a data frame to be decoded, and perform f operation and g operation on the data in the data frame to be decoded, respectively, to obtain a corresponding operation result. Data, according to the first preset enable signal and the second preset enable signal, determining candidate result data from the operation result data, and obtaining target data according to the preset acceleration calculation rule and the candidate result data, wherein, the preset The acceleration calculation rule is obtained by simplifying the operation mode of the preset number of calculation nodes, using the target data as the decoding data corresponding to the data frame to be decoded, and determining whether the currently obtained decoded data reaches the data frame to be decoded. The code length, if not, updates the first preset enable signal according to the target data, and continues to determine the candidate result data from the operation result data according to the first preset enable signal and the second preset enable signal. Based on the above processing, the merging of the computing nodes in the partial stages is realized by using the preset acceleration calculation rule, thereby reducing the delay of decoding.

Of course, any product or method embodying the present invention necessarily does not necessarily require all of the advantages described above to be achieved at the same time.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a schematic diagram of a prior art serial cancellation decoding method;

2 is a flowchart of a multi-bit parallel structure serial cancellation decoding method according to an embodiment of the present invention;

3 is a circuit diagram of a decoder having a code length of 8 based on the method of the present invention according to an embodiment of the present invention;

4 is a structural diagram of a PE module according to an embodiment of the present invention;

FIG. 5 is a structural diagram of a PSF module according to an embodiment of the present invention;

FIG. 6 is a structural diagram of a logic tree according to an embodiment of the present invention;

FIG. 7 is a structural diagram of a logic tree according to an embodiment of the present invention;

FIG. 8 is a comparison diagram of decoding delays according to an embodiment of the present invention; FIG.

FIG. 9 is a structural diagram of a multi-bit parallel structure serial cancellation decoding apparatus according to an embodiment of the present invention;

FIG. 10 is a structural diagram of an electronic device according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

When decoding is performed by the current technology, only after the decoded data corresponding to the previous clock cycle is calculated, the specific operation mode of the g operation of the subsequent clock cycle can be determined according to the calculated decoded data, thereby causing the whole The decoding process has a long delay.

In order to solve the above problem, an embodiment of the present invention provides a multi-bit parallel structure serial cancellation decoding method and apparatus, which can perform f operation and g operation on data in a data frame to be decoded, and obtain corresponding operation result data. Determining the candidate result data from the operation result data according to the first preset enable signal and the second preset enable signal, and obtaining the target data according to the preset acceleration calculation rule and the candidate result data, and using the target data as the to-be-translated Decoding data corresponding to the code data frame, and determining whether the currently obtained decoded data reaches the code length of the data frame to be decoded, and if not, updating the first preset enable signal according to the target data, and continuing according to the first pre- The enable signal and the second preset enable signal are set, and the candidate result data is determined from the operation result data. Based on the above processing, the merging of the computing nodes in the partial stages is realized by using the preset acceleration calculation rule, thereby reducing the delay of decoding.

Referring to FIG. 2, FIG. 2 is a flowchart of a multi-bit parallel structure serial cancellation decoding method according to an embodiment of the present invention. The embodiment is described by using an electronic device as an example, and the electronic device can be used for translating The code data frame is decoded, and the method may include the following processing steps.

S201: Acquire a data frame to be decoded, and perform f operation and g operation on the data in the data frame to be decoded, respectively, to obtain corresponding operation result data.

The data in the data frame to be decoded is usually bit likelihood ratio data.

A frame of data to be decoded typically contains 2 ^N bit likelihood ratio data (N is a positive integer), that is, the code length of the data frame to be decoded is 2 ^N . For example, a frame of data to be decoded may contain 8 bit likelihood ratio data, or a frame of data to be decoded may include 16 bit likelihood ratio data.

In an embodiment of the invention, the electronic device may acquire a data frame to be decoded, and for each frame of the data frame to be decoded, the electronic device may respectively perform f operation and g+ operation on the bit likelihood ratio data in the data frame to be decoded. And g- operations, and store the corresponding operation result data for subsequent processing.

Specifically, for the bit likelihood ratio data, the f operation can refer to formula (1):

g operation can refer to formula (2):

among them, with Representing a pair of bit likelihood ratio data, N represents the code length of a frame of data frame to be decoded, i=0, 1, 2...N-1. in case Is 0, then formula (2) represents the g+ operation, if When 1, the formula (2) represents the g-operation.

Specifically, the bit likelihood ratio data can be obtained according to formula (3):

among them, Representing a data frame to be decoded, and N is a code length of a received data frame to be decoded. Representing an estimate of the decoded data, Indicates the probability that the decoded data is judged to be 0. Indicates the probability that the decoded data is judged to be 1.

Referring to FIG. 3, FIG. 3 is a circuit diagram of a decoder with a code length of 8 according to the method of the present invention. In this embodiment, the code length of a frame to be decoded is 8 as an example. In FIG. 3, y ₀ , y ₁ ... y ₇ represent 8 bit likelihood ratio data in a frame of a data frame to be decoded, and the electronic device can perform f operation on every two bit likelihood ratio data through the PE module, g+ The operation and the g-operation are performed, and the calculation results are respectively stored in the corresponding D flip-flops.

The PE module includes a symbol operation device, an absolute value operation transposition, and a multi-bit full adder to simultaneously perform an f operation, a g+ operation, and a g-operation on a set of bit likelihood ratio data.

Referring to FIG. 4, FIG. 4 is a structural diagram of a PE module according to an embodiment of the present invention. Represents a set of bit likelihood ratio data, CLK represents the clock signal, and g-mux represents the enable signal. Express The result data of the f operation, Express The result data of the g+ operation, Express The operation result data of the g-operation is performed.

S202: Determine candidate result data from the operation result data according to the first preset enable signal and the second preset enable signal.

The first preset enable signal and the second preset enable signal may be set by a technician according to experience. Referring to FIG. 3, the first preset enable signal and the second preset enable signal are used to control the data output by the PE module to phase 2.

In an embodiment of the invention, when the next clock cycle is reached, the electronic device according to the first preset enable signal (ie, the enable signal of the first stage multiplexer in FIG. 3) and the second preset enable signal (ie, the multiplexer enable signal of the second stage in FIG. 3), the data that needs to be input to phase 2 (ie, the candidate result data) is determined from the operation result data of the PE module. Wherein, the first stage multiplexer in FIG. 3 is a multiplexer closer to the PE module, and the second stage multiplexer in FIG. 3 is a multiplexer farther from the PE module.

Optionally, the electronic device may take the following steps to determine candidate result data from the operation result data.

Step 1: If the second preset enable signal is currently low, the operation result data corresponding to the f operation is determined as the candidate result data.

In an embodiment of the invention, the electronic device may acquire the signal values of the first preset enable signal and the second preset enable signal corresponding to the current clock cycle. If the current preset signal is low, the electronic device may determine the operation result data corresponding to the f operation as the candidate result data.

Referring to FIG. 3, when the electronic device determines that the current signal value of the second preset enable signal is 0, the electronic device may perform the operation result data obtained by the f operation of the PE module as the candidate result data, and select the result data. Enter to stage 2.

Step 2: If the second preset enable signal is currently at a high level, the candidate result data is determined from the operation result data corresponding to the g operation according to the first preset enable signal.

In an embodiment of the invention, when the electronic device determines that the second preset enable signal is currently at a high level, the electronic device may determine an alternative result from the operation result data corresponding to the g operation according to the first preset enable signal. data.

For example, referring to FIG. 3, when the electronic device determines that the second preset enable signal is currently 1, the electronic device may determine a current signal value of the first preset enable signal, if the first preset enable signal is currently 0, The electronic device can perform the operation result data obtained by the g+ operation of the PE module as the alternative result data, and input the alternative result data to the stage 2.

If the first preset enable signal is currently 1, the electronic device may perform the operation result data obtained by the g-operation of the PE module as the alternative result data, and input the alternative result data to the phase 2.

S203: Obtain target data according to preset acceleration calculation rules and candidate result data.

The preset acceleration calculation rule is obtained by simplifying the operation manner of the preset number of calculation nodes.

In FIG. 3, the accelerator module is a circuit structure obtained according to a preset acceleration calculation rule, and the accelerator module is obtained by combining the calculation nodes of phase 2 and phase 3 with respect to the prior art.

According to Fig. 1, the formula (4) can be obtained.

Where f and g represent the f operation and the g operation, respectively, and h represents the decision function. Indicates the i-th bit likelihood ratio data, i=0, 1, 2, 3.

Simplify equation (4) according to a Boolean function to get:

λ ₁ and λ ₂ represent the output of the multiplexer in the accelerator module.

According to formula (5), formula (6) and formula (7), the calculation nodes of phase 2 and phase 3 in the prior art can be combined to complete the calculation in the same clock cycle.

Specifically, the bit likelihood ratio data is determined using equation (8).

among them, Representing an estimate of the decoded data, Represents bit likelihood ratio data. The decision result is output to a bit full adder or a full reducer and output to the multiplexer. Four way decision signals pass through three exclusive OR gate outputs You can get The output is XORed with the signals of the first two XOR outputs, and the result of the last two XOR operations is selected by the multiplexer. The last two bits are also output through two-stage XOR operation. with

In the embodiment of the invention, the electronic device can obtain the target data according to the preset acceleration calculation rule and the candidate result data. For example, in FIG. 3, in the second clock cycle, the electronic device can output 4 bits of target data through the accelerator module.

It should be noted that, in this embodiment, only the computing nodes in the last two phases are merged. In the actual operation, the number of phases of the merged computing nodes may be selected according to service requirements. For example, the code length of a frame of data to be decoded is 16, and correspondingly, the decoding process of the prior art is completed by four stages of computing nodes. At this time, the computing nodes of the latter two stages can be merged. The compute nodes of the last three phases can be merged. If the number of merged stages can be represented by m, the target data output by one clock cycle accelerator module includes 2 ^m bits.

Optionally, for the data frame to be decoded obtained by the polarization coding, the step of acquiring the target data by the electronic device may include the following processing steps.

In step one, according to the preset acceleration calculation rule, the candidate result data is calculated, and the accelerated calculation result data is obtained.

In the embodiment of the invention, the electronic device calculates the candidate result data according to the preset acceleration calculation rule, and uses the obtained data as the acceleration calculation result data.

For the circuit structure in FIG. 3, the electronic device can input the candidate result data obtained in the first clock cycle to the accelerator module, and the accelerator module can accelerate the calculation rule according to the preset (ie, formula (6), formula (7) ) and formula (8)), get accelerated calculation result data.

In step two, the acceleration calculation result data and the preset correction data are ANDed to obtain target data.

Among them, the preset correction data can be set by the technician according to experience. Specifically, the preset correction data may include information bit data and frozen bit data. Generally, the information bit data is 1, and the frozen bit data is 0.

In an embodiment of the invention, the electronic device may perform an AND operation on the acceleration calculation result data and the preset correction data to obtain target data.

For example, the acceleration calculation result data obtained by the electronic device is 0101, and the preset correction data corresponding to the acceleration calculation result data of 4 bits is 1011. The electronic device can perform the AND operation on the 4-bit acceleration calculation result data 0101 and the corresponding preset correction data 1011, respectively, to obtain 0001, and 0001 as the target data corresponding to 0101.

S204: The target data is used as the decoding data corresponding to the data frame to be decoded, and it is determined whether the currently obtained decoded data reaches the code length of the data frame to be decoded. If not, S205 is performed.

In an embodiment of the invention, the electronic device may use the obtained target data as the decoded data corresponding to the data frame to be decoded. After each time the target data is obtained, the electronic device can determine whether all the target data currently obtained reaches the code length of the data frame to be decoded.

For example, in FIG. 3, a frame of data to be decoded includes 8 bit likelihood ratio data, and in the second clock cycle, the electronic device can obtain 4 bits of target data. At this time, the target data obtained by the electronic device is If the code length of the data frame to be decoded is not reached, the electronic device may perform step S205.

S205: Update the first preset enable signal according to the target data, and execute step S202.

In the embodiment of the present invention, when the electronic device determines that all the target data currently obtained does not reach the code length of the data frame to be decoded, the electronic device may update the first preset enable signal according to the target data, and further may continue according to the first The preset enable signal and the second preset enable signal determine the candidate result data from the operation result data to obtain the target data again until the obtained target data reaches the code length of the data frame to be decoded. The initial signals of the first preset enable signal and the second preset enable signal are both low.

For example, in FIG. 3, in the third clock cycle, the electronic device uses the accelerator module again to obtain 4 bits of target data. At this time, the electronic device obtains 8 bits of target data to reach the code of the data frame to be decoded. long. The electronic device can use the obtained target data of 8 bits as the decoded data corresponding to the data frame to be decoded.

It can be seen that, in the prior art, for a data frame to be decoded with a code length of 8, it takes 14 clock cycles to complete decoding, and based on the method of the embodiment, only 3 clock cycles are required to complete the decoding. Similarly, for a data frame to be decoded with a code length of N, the prior art requires 2 (N-1) clock cycles to complete decoding, and based on the method of the embodiment, only N/2-1 clocks are required. The decoding can be completed in the cycle, and the delay of decoding can be reduced.

Optionally, the method for the electronic device to update the first preset enable signal may include the following processing steps.

Partial sum is obtained for the target data, and the partial and result data are obtained; the partial and result data are obtained as the current signal value of the first preset enable signal.

In an embodiment of the invention, the electronic device can obtain a partial sum of the obtained target data to obtain a partial and result data. Then, the electronic device can use the partial and result data as the current signal value of the corresponding first preset enable signal.

For example, the electronic device may be provided with a request portion and a PSF module to obtain a partial sum of the target data. See Figure 5 for a circuit diagram of the parts and modules.

among them, Indicates the output signals of the partial and feedback modules, The input signal representing the partial and feedback modules, clk represents the clock signal, loop-mux and psf-mux represent the two-stage multiplexer enable signal of the partial and feedback modules.

In Figure 3, target data is available in the second clock cycle. with Electronic equipment can be obtained according to the PSF module with As part and result data, and with The first preset enable signal corresponding to the four PE modules.

In addition, the second preset enable signal may be determined according to a code length of a data frame to be decoded and a preset period algorithm.

The preset period algorithm may be set by a technician according to experience. Specifically, the preset period algorithm may be represented by a logic tree.

In an embodiment of the invention, after acquiring the data frame to be decoded, the electronic device may determine the second preset enable signal according to the code length of the data frame to be decoded and the preset period algorithm.

Referring to FIG. 6, FIG. 6 is a logic tree corresponding to the prior art provided by the embodiment.

The data frame to be decoded corresponding to the logical tree contains 16 bit likelihood ratio data, that is, the code length of the data frame to be decoded is 16. Therefore, the entire decoding process can be divided into four stages. In the figure, for a data frame to be decoded with a code length of N, the number of layers of the logical tree is log ₂ N, that is, the number of stages of the decoding process. Hollow dots represent the f operation, and solid dots represent the g operation. The number under each compute node indicates the number of clock cycles required by the compute node to maintain the current operation. The number of clock cycles required by the compute node in the dashed line to maintain the current operation can be represented by N.2 ^1-r -1, where r is The stage at which the current compute node is located. The root node of the right subtree maintains the number of clock cycles required for the current operation as N-log ₂ N. The second preset enable signal can be determined based on the number of clock cycles required for the node to maintain the current operation.

It can be seen that among the two child nodes of a computing node, the right child node maintains the number of clock cycles required for the current operation, which is equal to the number of clock cycles required by the computing node to maintain the current operation minus the left child node needs to maintain the current operation. The number of clock cycles. That is, the number of clock cycles required for the current child node to maintain the current operation can be used. Said that Indicates the number of clock cycles required by the parent node of the child node to maintain the current operation, α(r, c-1) represents the number of clock cycles required for the left child node to maintain the current operation, and c represents the right child node at the current stage of the logic tree. The number from left to right, the number of nodes in the logical tree is the clock cycle required for the entire decoding.

Based on the method of the embodiment of the present invention, the logic trees in the prior art can be merged to obtain a logic tree as shown in FIG. 7.

The solid dot indicates the PE module, and the hollow dot indicates the accelerator module. It can be seen that for the data frame to be decoded with a code length of 16, the method of the embodiment only needs 7 clock cycles to complete the decoding.

Referring to FIG. 8, FIG. 8 is a schematic diagram of comparison of decoding delays according to the embodiment.

Figure 8 includes the decoding delay of a conventional tree SC decoder, the decoding delay of the SC decoder, the decoding delay of the 2b-SC decoder, and the decoder of the method according to the present invention. Decoding delay. It can be seen that the decoding delay can be reduced based on the method of the present invention.

According to the multi-bit parallel structure serial cancellation decoding method of the embodiment of the present invention, the data in the data frame to be decoded is subjected to f operation and g operation, respectively, to obtain corresponding operation result data, according to the first preset enable signal and the first The second preset enable signal determines the candidate result data from the operation result data, obtains the target data according to the preset acceleration calculation rule and the candidate result data, and uses the target data as the decoded data corresponding to the data frame to be decoded, and Determining whether the currently obtained decoded data reaches the code length of the data frame to be decoded, and if not, updating the first preset enable signal according to the target data, and continuing to perform according to the first preset enable signal and the second preset The energy signal determines the candidate result data from the operation result data. Based on the above processing, the merging of the computing nodes in the partial stages is realized by using the preset acceleration calculation rule, thereby reducing the delay of decoding.

Corresponding to the method embodiment of FIG. 2, referring to FIG. 9, FIG. 9 is a multi-bit parallel structure serial cancellation decoding apparatus according to an embodiment of the present invention, where the apparatus includes:

The calculation module 901 is configured to obtain a data frame to be decoded, perform f operation and g operation on the data in the data frame to be decoded, respectively, to obtain corresponding operation result data;

The determining module 902 is configured to determine candidate result data from the operation result data according to the first preset enable signal and the second preset enable signal;

The obtaining module 903 is configured to obtain the target data according to the preset acceleration calculation rule and the candidate result data, where the preset acceleration calculation rule is obtained by simplifying the operation manner of the preset number of calculation nodes;

The determining module 904 is configured to use the target data as the decoded data corresponding to the data frame to be decoded, and determine whether the currently obtained decoded data reaches the code length of the data frame to be decoded;

The processing module 905 is configured to: if not, update the first preset enable signal according to the target data, and perform the operation result data according to the first preset enable signal and the second preset enable signal. Determine the alternative result data steps.

Optionally, the determining module 902 is specifically configured to determine the operation result data corresponding to the f operation as the candidate result data if the second preset enable signal is currently at a low level;

If the second preset enable signal is currently at a high level, the candidate result data is determined from the operation result data corresponding to the g operation according to the first preset enable signal.

Optionally, the obtaining module 903 is specifically configured to calculate, according to a preset acceleration calculation rule, the candidate result data, to obtain accelerated calculation result data;

Performing an AND operation on the acceleration calculation result data and the preset correction data to obtain target data.

Optionally, the processing module 905 is specifically configured to obtain a partial sum of the target data, to obtain a partial part and result data;

And determining the partial and result data as the current signal value of the first preset enable signal.

Optionally, the second preset enable signal is determined according to a code length of the data frame to be decoded and a preset period algorithm.

The multi-bit parallel structure serial cancellation decoding apparatus according to the embodiment of the present invention performs f operation and g operation on the data in the data frame to be decoded, respectively, to obtain corresponding operation result data, according to the first preset enable signal and the first The second preset enable signal determines the candidate result data from the operation result data, obtains the target data according to the preset acceleration calculation rule and the candidate result data, and uses the target data as the decoded data corresponding to the data frame to be decoded, and Determining whether the currently obtained decoded data reaches the code length of the data frame to be decoded, and if not, updating the first preset enable signal according to the target data, and continuing to perform according to the first preset enable signal and the second preset The energy signal determines the candidate result data from the operation result data. Based on the above processing, the merging of the computing nodes in the partial stages is realized by using the preset acceleration calculation rule, thereby reducing the delay of decoding.

The embodiment of the present invention further provides an electronic device, as shown in FIG. 10, including a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 pass through the communication bus 1004. Complete communication with each other,

a memory 1003, configured to store a computer program;

The processor 1001 is configured to perform the following steps when executing the program stored on the memory 1003:

Obtaining a data frame to be decoded, performing f operation and g operation on the data in the data frame to be decoded, respectively, to obtain corresponding operation result data;

Determining candidate result data from the operation result data according to the first preset enable signal and the second preset enable signal;

And obtaining, according to the preset acceleration calculation rule and the candidate result data, the target acceleration data, wherein the preset acceleration calculation rule is obtained by simplifying operation manners of a preset number of calculation nodes;

Determining, by using the target data, the decoded data corresponding to the data frame to be decoded, and determining whether the currently obtained decoded data reaches the code length of the data frame to be decoded;

If not, updating the first preset enable signal according to the target data, and performing determining, according to the first preset enable signal and the second preset enable signal, the candidate result data from the operation result data step.

Optionally, the determining, according to the first preset enable signal and the second preset enable signal, the candidate result data from the operation result data, including:

If the second preset enable signal is currently low, determining the operation result data corresponding to the f operation as the candidate result data;

If the second preset enable signal is currently at a high level, the candidate result data is determined from the operation result data corresponding to the g operation according to the first preset enable signal.

Optionally, the obtaining the target data according to the preset acceleration calculation rule and the candidate result data, including:

Calculating the candidate result data according to a preset acceleration calculation rule to obtain accelerated calculation result data;

Performing an AND operation on the acceleration calculation result data and the preset correction data to obtain target data.

Optionally, the updating the first preset enable signal according to the target data includes:

Partially summing the target data to obtain a partial and result data;

And determining the partial and result data as the current signal value of the first preset enable signal.

Optionally, the second preset enable signal is determined according to a code length of the data frame to be decoded and a preset period algorithm.

The communication bus mentioned in the above electronic device may be a Peripheral Pomponent Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the above electronic device and other devices.

The memory may include a random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

The processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (Ne twork processor, NP for short), or a digital signal processor (DSP). ), Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component.

It should be noted that, in this context, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations. There is any such actual relationship or order between them. Furthermore, the term "comprises" or "comprises" or "comprises" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a plurality of elements includes not only those elements but also Other elements, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.

The various embodiments in the present specification are described in a related manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus, the electronic device, the computer readable storage medium, and the computer program product embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Any modifications, equivalents, improvements, etc. made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (10)

1. A serial cancellation decoding method for a multi-bit parallel structure is characterized by comprising the following steps:

acquiring a data frame to be decoded, and respectively performing f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data;

determining alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal;

obtaining target data according to a preset accelerated computing rule and the alternative result data, wherein the preset accelerated computing rule is obtained by simplifying the operation mode of a preset number of computing nodes;

the target data is used as decoding data corresponding to the data frame to be decoded, and whether the currently obtained decoding data reaches the code length of the data frame to be decoded is judged;

if not, updating the first preset enabling signal according to the target data, and executing a step of determining alternative result data from the operation result data according to the first preset enabling signal and the second preset enabling signal.

2. The method of claim 1, wherein determining alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal comprises:

if the second preset enabling signal is at a low level currently, determining operation result data corresponding to the f operation as alternative result data;

and if the second preset enabling signal is at a high level currently, determining alternative result data from the operation result data corresponding to the g operation according to the first preset enabling signal.

3. The method according to claim 1, wherein obtaining target data according to a preset accelerated computing rule and the candidate result data comprises:

calculating the alternative result data according to a preset accelerated calculation rule to obtain accelerated calculation result data;

and performing AND operation on the accelerated calculation result data and preset correction data to obtain target data.

4. The method of claim 1, wherein the updating the first preset enable signal according to the target data comprises:

partial summation is carried out on the target data to obtain partial summation result data;

and taking the summation result data as the current signal value of the first preset enabling signal.

5. The method of claim 1, wherein the second preset enable signal is determined according to a code length of the data frame to be decoded and a preset period algorithm.

6. An apparatus for serial cancellation decoding with a multi-bit parallel structure, the apparatus comprising:

the calculation module is used for acquiring a data frame to be decoded, and respectively performing f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data;

the determining module is used for determining alternative result data from the operation result data according to a first preset enabling signal and a second preset enabling signal;

the acquisition module is used for acquiring target data according to a preset accelerated computing rule and the alternative result data, wherein the preset accelerated computing rule is obtained by simplifying the operation mode of a preset number of computing nodes;

the judging module is used for taking the target data as decoding data corresponding to the data frame to be decoded and judging whether the currently obtained decoding data reaches the code length of the data frame to be decoded;

and the processing module is used for updating the first preset enabling signal according to the target data and executing the step of determining alternative result data from the operation result data according to the first preset enabling signal and the second preset enabling signal if the target data is not updated.

7. The apparatus according to claim 6, wherein the determining module is specifically configured to determine, if the second preset enable signal is currently at a low level, the operation result data corresponding to the f-operation as the candidate result data;

and if the second preset enabling signal is at a high level currently, determining alternative result data from the operation result data corresponding to the g operation according to the first preset enabling signal.

8. The apparatus according to claim 6, wherein the obtaining module is specifically configured to calculate the candidate result data according to a preset accelerated calculation rule to obtain accelerated calculation result data;

and performing AND operation on the accelerated calculation result data and preset correction data to obtain target data.

9. The apparatus according to claim 6, wherein the processing module is specifically configured to perform partial summation on the target data to obtain partial summation result data;

and taking the summation result data as the current signal value of the first preset enabling signal.

10. The apparatus of claim 6, wherein the second preset enable signal is determined according to a code length of the data frame to be decoded and a preset period algorithm.