CN116169029A - Packaging substrate and preparation method thereof - Google Patents
Packaging substrate and preparation method thereof Download PDFInfo
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- CN116169029A CN116169029A CN202310028959.5A CN202310028959A CN116169029A CN 116169029 A CN116169029 A CN 116169029A CN 202310028959 A CN202310028959 A CN 202310028959A CN 116169029 A CN116169029 A CN 116169029A
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- 239000000758 substrate Substances 0.000 title claims abstract description 166
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 50
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000008719 thickening Effects 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 168
- 238000000034 method Methods 0.000 claims description 24
- 238000003466 welding Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 4
- 238000004381 surface treatment Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 abstract description 9
- 239000005022 packaging material Substances 0.000 abstract description 8
- 230000005856 abnormality Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The application discloses a packaging substrate and a preparation method thereof, wherein the preparation method of the packaging substrate comprises the following steps: obtaining a strippable carrier plate which comprises a substrate and a first conductive layer which is attached to at least one side of the substrate and is strippable; thickening a first preset position and a second preset position of one side of each first conductive layer far away from the substrate, and correspondingly forming a target conductive circuit and a metal boss; preparing at least one layer of conductive circuit on one side of each target conductive circuit far away from the substrate, and stripping the substrate and each corresponding first conductive layer to obtain at least one processing plate; and etching the processing plate until the metal boss is removed to form a hollowed-out groove so as to prepare the packaging substrate. Through the mode, the gap between the follow-up component and the plate can be enlarged, so that the filling of plastic packaging materials is facilitated, the cavity abnormality is reduced, and the structural reliability of the packaging substrate is improved.
Description
Technical Field
The application is applied to the technical field of packaging substrates, in particular to a packaging substrate and a preparation method thereof.
Background
Along with the continuous development of science and technology, electronic products are continuously developed towards the directions of high density and high integration, and the packaging process of the packaging substrate also tends to be fine and light, so that the requirements of industry on the flatness of the packaging substrate are higher.
ETS (Embedded Trace Substrate) is a fine circuit fabrication process characterized by the circuit layer being embedded in a dielectric layer.
For ETS products, as the circuit is embedded in the dielectric layer, the horizontal plane of the circuit is lower than that of the dielectric layer through the biting of the rear section, and after components are attached through SMT (surface mounting technology), gaps between the components and the dielectric layer are small, so that plastic packaging materials cannot enter the gaps during plastic packaging, and cavity abnormality is generated.
Disclosure of Invention
The application provides a packaging substrate and a preparation method thereof, which are used for solving the problems that in the prior art, gaps between components and dielectric layers are small, and cavity abnormality is easy to generate.
In order to solve the above technical problems, the present application provides a method for manufacturing a package substrate, including: obtaining a strippable carrier plate which comprises a substrate and a first conductive layer which is attached to at least one side of the substrate and is strippable; thickening a first preset position and a second preset position of one side of each first conductive layer far away from the substrate, and correspondingly forming a target conductive circuit and a metal boss; preparing at least one layer of conductive circuit on one side of each target conductive circuit far away from the substrate, and stripping the substrate and each corresponding first conductive layer to obtain at least one processing plate; and etching the processing plate until the metal boss is removed to form a hollowed-out groove so as to prepare the packaging substrate.
The step of thickening a first preset position and a second preset position of one side of each first conductive layer far away from the substrate to correspondingly form a target conductive line and a metal boss comprises the following steps: attaching the protective layer to the side, far away from the substrate, of each first conductive layer except the first preset position and the second preset position; electroplating and thickening are carried out on one side, far away from the substrate, of each first conductive layer so as to form a target conductive circuit at a first preset position, and a metal boss is formed at a second preset position.
Wherein, preparing at least one layer of conductive circuit on one side of each target conductive circuit far away from the substrate, and stripping the substrate and each corresponding first conductive layer to obtain at least one processed plate, wherein the step of obtaining at least one processed plate comprises the following steps: laminating a dielectric layer on one side of each target conductive circuit far away from the substrate, and preparing a conductive circuit on one side of the dielectric layer far away from the substrate; repeatedly preparing the conductive circuits until the number of layers of the conductive circuits on one side of each target conductive circuit far away from the substrate meets the preset number of layers; and stripping the substrate and each corresponding first conductive layer, and removing the first conductive layers to obtain at least one processed plate.
Wherein, the step of preparing the conductive circuit on the side of the dielectric layer away from the substrate comprises: drilling the dielectric layer from one side of the dielectric layer far away from the substrate to form a plurality of through holes, wherein each through hole exposes a corresponding target conductive line; electroplating one side of the dielectric layer far away from the substrate until each through hole is filled to form a through hole, and forming a second conductive layer on one side of the dielectric layer far away from the substrate; etching the second conductive layer to obtain a conductive circuit.
Wherein, etch each processing plate, until remove the metal boss and form the hollow groove, in order to prepare the step of packaging the base plate includes: attaching photoetching layers on the whole plates on two opposite sides of the processed plate; exposing and developing the processed plate based on the position corresponding to the metal boss on the photoetching layer; and etching the processed plate until the metal boss is removed to form a hollowed-out groove so as to prepare the packaging substrate.
Wherein, etch the processing plate, until removing the metal boss and forming the hollow groove to the step of preparing the encapsulation base plate still includes: and welding the components on the bonding pads of the target conductive circuits, and performing plastic packaging on the components and the processed plate until the components are wrapped and the hollow grooves are filled, so as to prepare the packaging substrate.
The method comprises the steps of welding components on a bonding pad of a target conductive line, and performing plastic package on the components and a processing plate until the components are wrapped and the hollow groove is filled, so that the method comprises the following steps of: attaching a solder mask layer at a third preset position on two opposite sides of the processed plate; and carrying out surface treatment on the exposed conductive circuits on the two opposite sides of the processed plate.
Wherein the thickness of the metal boss ranges from 10 to 35 microns.
In order to solve the above technical problem, the present application further provides a package substrate, including: the packaging substrate is prepared by the preparation method of the packaging substrate. The packaging substrate comprises a packaging substrate and a packaging substrate, wherein a hollow groove is formed in a conductive circuit on one side of the packaging substrate, and the hollow groove penetrates through the corresponding conductive circuit.
The packaging substrate also comprises a plastic sealing layer and components; the conductive circuit on one side of the packaging substrate comprises a bonding pad; the components and the bonding pads are welded and fixed, and the plastic sealing layer wraps the components and fills the hollow grooves.
The beneficial effects of this application are: different from the condition of the prior art, the method and the device correspondingly form the target conductive circuit and the metal boss by thickening the first preset position and the second preset position of one side of each first conductive layer of the strippable carrier plate far away from the substrate; preparing at least one layer of conductive circuit on one side of each target conductive circuit far away from the substrate, and stripping the substrate and each corresponding first conductive layer to obtain at least one processing plate; and finally, etching each processing plate until the metal boss is removed to form a hollowed-out groove so as to prepare the packaging substrate. Therefore, before at least one layer of conductive circuit is prepared, the metal boss is prepared at the second preset position, so that the situation that the dielectric layer is filled in the second preset position in the process of the subsequent at least one layer of conductive circuit, so that the subsequent conductive circuit is difficult to remove and the gap generated by welding of subsequent components is reduced is prevented. And the metal boss is etched to form a hollow groove, so that the gap between the subsequent component and the plate is enlarged, the filling of plastic packaging materials is facilitated, the abnormal holes are reduced, and the structural reliability of the packaging substrate is improved.
Drawings
Fig. 1 is a schematic flow chart of an embodiment of a method for manufacturing a package substrate provided in the present application;
fig. 2 is a schematic flow chart of another embodiment of a method for manufacturing a package substrate provided in the present application;
FIG. 3 is a schematic flow diagram of one embodiment of a process for making a processed panel;
FIG. 4 is a schematic flow chart of an embodiment of preparing a package substrate based on a processed board;
FIG. 5 is a schematic diagram of an embodiment of a package substrate according to the present disclosure;
fig. 6 is a schematic structural diagram of another embodiment of a package substrate provided in the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, fig. 1 is a flow chart illustrating an embodiment of a method for manufacturing a package substrate according to the present application.
Step S11: and obtaining a strippable carrier plate, wherein the strippable carrier plate comprises a substrate and a first conductive layer which is attached to at least one side of the substrate and is in strippable arrangement.
In a specific application scenario, the peelable carrier plate includes a substrate and a first conductive layer attached to one side of the substrate, which may be used for preparing a package substrate on one side. In another specific application scenario, the strippable carrier plate comprises a substrate and two first conductive layers respectively attached to two opposite sides of the substrate, and the first conductive layers are used for preparing two packaging substrates on two sides.
The substrate is attached to the first conductive layer and can be peeled off. The substrate may include a double-sided copper-clad plate, a monolithic metal substrate, etc., without limitation.
Step S12: and thickening the first preset position and the second preset position of one side of each first conductive layer far away from the substrate, and correspondingly forming a target conductive circuit and a metal boss.
The first preset position corresponds to the target conductive line and is used for preparing the target conductive line; the second preset position corresponds to the metal boss, and the second preset position is the position of a gap generated by welding of subsequent components. When a plurality of components need to be mounted later, the second preset position can correspondingly comprise a plurality of components.
And thickening at a first preset position to form a target conductive circuit, and thickening at a second preset position to form a metal boss. The first preset position and the second preset position may be adjacent, that is, the target conductive line is connected to the metal boss, and may even be integrally formed.
The thickening may be performed by electroplating, metal block welding, or the like, and is not limited herein.
In the step, the metal boss is arranged at the second preset position, so that the situation that the dielectric layer is filled in the second preset position in the preparation process of at least one layer of subsequent conductive circuit, so that the subsequent conductive circuit is difficult to remove and the gap generated by welding the plate and the component is reduced is prevented.
Step S13: and preparing at least one layer of conductive circuit on one side of each target conductive circuit far away from the substrate, and stripping the substrate and each corresponding first conductive layer to obtain at least one processing plate.
The specific number of layers of the at least one layer of conductive traces may be set based on actual requirements. When at least one layer of conductive circuit is required to be prepared on both sides of the strippable carrier plate, the number of layers of the conductive circuit on both sides can be the same or different.
In a specific application scenario, a layer of conductive circuit and 3 layers of conductive circuit may be respectively prepared on the side, away from the substrate, of the first conductive layer on the opposite sides of the releasable carrier. In another specific application scenario, 2 layers of conductive traces may also be prepared on the side of the first conductive layer on the opposite side of the releasable carrier away from the substrate. And are not limited herein.
And after at least one layer of conductive circuit is prepared, stripping the substrate and each first conductive layer in the strippable carrier plate to obtain a processed plate formed by the first conductive layer and the corresponding at least one layer of conductive circuit.
Step S14: and etching the processing plate until the metal boss is removed to form a hollowed-out groove so as to prepare the packaging substrate.
The metal boss is etched and removed to form a hollow groove, namely, the hollow groove is formed at a second preset position, so that a gap generated by welding a subsequent plate and a component is enlarged, and the plastic packaging material is filled conveniently.
Through the steps, the preparation method of the packaging substrate of the embodiment thickens the first preset position and the second preset position of one side, far away from the substrate, of each first conductive layer of the strippable carrier plate, so that a target conductive circuit and a metal boss are correspondingly formed; preparing at least one layer of conductive circuit on one side of each target conductive circuit far away from the substrate, and stripping the substrate and each corresponding first conductive layer to obtain at least one processing plate; and finally, etching each processing plate until the metal boss is removed to form a hollowed-out groove so as to prepare the packaging substrate. Therefore, before at least one layer of conductive circuit is prepared, the metal boss is prepared at the second preset position, so that the situation that the dielectric layer is filled in the second preset position in the process of the subsequent at least one layer of conductive circuit, so that the subsequent conductive circuit is difficult to remove and gaps generated by welding with subsequent components are reduced is prevented. And the metal boss is etched to form a hollow groove, so that the gap between the subsequent component and the plate is enlarged, the filling of plastic packaging materials is facilitated, the abnormal holes are reduced, and the structural reliability of the packaging substrate is improved.
Referring to fig. 2-4, fig. 2 is a flow chart illustrating another embodiment of a method for manufacturing a package substrate according to the present application. Fig. 3 is a schematic flow chart of an embodiment of preparing a processed board, and fig. 4 is a schematic flow chart of an embodiment of preparing a package substrate based on the processed board. The schematic diagram of this embodiment only schematically illustrates the preparation flow, and does not limit the specific structure of the package substrate.
Step S21: and obtaining a strippable carrier plate, wherein the strippable carrier plate comprises a substrate and a first conductive layer which is attached to at least one side of the substrate and is in strippable arrangement.
The step is the same as the step S11 in the foregoing embodiment, please refer to the foregoing, and the description is omitted.
Referring to fig. 3a, the releasable carrier 100 of the present embodiment includes a substrate 110 and two first conductive layers 120. The two first conductive layers 120 are respectively adhered to opposite sides of the substrate 110.
The substrate 110 may include a double-sided copper-clad plate or a metal substrate, which is not limited herein.
Step S22: and attaching the protective layer to the position, except the first preset position and the second preset position, of one side, far away from the substrate, of each first conductive layer.
Referring to fig. 3b, the passivation layer 130 is attached to a side of each first conductive layer 120 away from the substrate 110 except for the first predetermined position 131 and the second predetermined position 132. The first preset position 131 and the second preset position 132 are exposed.
The protective layer 130 may include a protective material such as a plating resist, a dry film, etc. To prevent thickening of the first conductive layers 120 at positions other than the first preset position 131 and the second preset position 132 on the side away from the substrate 110.
The first preset position 131 and the second preset position 132 may be adjacent or independent, and may be specifically set based on actual requirements, which is not limited herein.
The first preset position 131 is a position for preparing a target conductive line, and the second preset position 132 is a position of a gap generated by welding with a component. When a plurality of components are required to be mounted subsequently, the second preset position 132 may correspondingly include a plurality of components.
Step S23: electroplating and thickening are carried out on one side, far away from the substrate, of each first conductive layer so as to form a target conductive circuit at a first preset position, and a metal boss is formed at a second preset position.
Referring to fig. 3c, the side of each first conductive layer 120 away from the substrate 110 is thickened by electroplating to form a target conductive trace 141 at a first predetermined position 131 and a metal bump 142 at a second predetermined position 132. The target conductive trace 141 and the metal boss 142 may be integrally formed, i.e., plated at the same time.
After the plating is completed, the protective layer 130 is removed.
The thickness of the metal boss 142 may be in the range of 10-35 microns, and may specifically be 10 microns, 15 microns, 16 microns, 18 microns, 20 microns, 23 microns, 25 microns, 30 microns, 32 microns, 35 microns, etc. The metal boss 142 in this range can reserve enough space for the void generated by the subsequent component soldering, prevent filling the void and prevent the metal boss 142 from being too thick to affect the signal transmission of the target conductive line 141 or the component mounting.
In one specific application scenario, the thickness of the protective layer 130 may be not less than the metal boss 142 to assist in forming the metal boss 142 during the electroplating thickening process.
Step S24: laminating a dielectric layer on one side of each target conductive circuit far away from the substrate, and preparing a conductive circuit on one side of the dielectric layer far away from the substrate; and repeatedly preparing the conductive circuits until the number of layers of the conductive circuits on one side of each target conductive circuit far away from the substrate meets the preset number of layers.
Referring to fig. 3d, a dielectric layer 150 is laminated on a side of each target conductive trace 141 away from the substrate 110, and the dielectric layer 150 covers the target conductive traces 141 and the metal bumps 142. And the dielectric layer 150 fills the gaps between the target conductive traces 141 to prevent the target conductive traces 141 from being undercut during the subsequent etching process, which affects the width of the target conductive traces 141. At this time, the dielectric layer 150 cannot fill the second preset position 132 because the metal bump 142 is formed on the second preset position 132.
A copper foil layer (not shown) may be formed on the side of the dielectric layer 150 away from the substrate 110, so as to facilitate adhesion during lamination and serve as a primer layer for subsequent electroplating.
Referring to fig. 3e, a plurality of through holes 151 are formed by drilling the dielectric layer 150 from a side of the dielectric layer 150 away from the substrate 110, and each through hole 151 exposes the corresponding target conductive line 141, so that the metal boss 142 needs to be removed later, and the preparation position of the through hole 151 needs to avoid the metal boss 142.
Drilling may be performed by laser ablation.
Referring to fig. 3f, the side of the dielectric layer 150 away from the substrate 110 is electroplated until each via is filled to form a via 152, and a second conductive layer 153 is formed on the side of the dielectric layer 150 away from the substrate.
At this time, the via 152 communicates with the target conductive line 141 and the second conductive layer 153.
Referring further to fig. 3g, the second conductive layer 153 is etched to obtain a conductive line 154.
Specifically, the etching step may be performed by film pasting, exposure, development, and etching.
In this embodiment, a layer of conductive traces 154 is prepared on the side of each target conductive trace 141 far from the substrate 110, and when other numbers of conductive traces 154 are needed to be prepared on the side of each target conductive trace 141 far from the substrate 110, the preparation of each layer of conductive traces 154 is still performed by laminating a dielectric layer, drilling holes, forming conductive holes and conductive layers by electroplating, and finally etching.
The conductive traces 154 are repeatedly prepared as described above until the number of layers of the conductive traces 154 on the side of each target conductive trace 141 remote from the substrate 110 meets a preset number of layers. The preset number of layers can be set based on actual requirements.
Step S25: and stripping the substrate and each corresponding first conductive layer, and removing the first conductive layers to obtain at least one processed plate.
The substrate 110 and the corresponding first conductive layers 120 are peeled off.
The plate at this time includes a first conductive layer 120, a target conductive line 141, a dielectric layer 150 and a conductive line 154 that are sequentially stacked and bonded, where the metal bump 142 and the target conductive line 141 are disposed on the same layer, and the target conductive line 141 and the conductive line 154 are communicated through a via 152.
And removing the first conductive layer 120 to obtain at least one processed plate 160. Specifically, the first conductive layer 120 may be removed by rapid etching to expose the target conductive line 141 and the conductive line 154.
Since the dielectric layer 150 is filled with the gap of the target conductive line 141 before the rapid etching, the dielectric layer 150 filled in the gap of the target conductive line 141 can prevent the target conductive line 141 from being etched by the etching solution during the rapid etching, thereby ensuring the line width of the target conductive line 141 and improving the reliability of the target conductive line 141.
Referring to fig. 3h, the processed board 160 includes a target conductive trace 141, a dielectric layer 150 and a conductive trace 154 sequentially stacked and bonded, wherein the metal bump 142 and the target conductive trace 141 are disposed on the same layer, and the target conductive trace 141 and the conductive trace 154 are communicated through a via 152.
Step S26: attaching photoetching layers on the whole plates on two opposite sides of the processed plate; exposing and developing the processed plate based on the position corresponding to the metal boss on the photoetching layer; and etching the processed plate until the metal boss is removed to form a hollowed-out groove.
Referring further to fig. 3i-3l, a photoresist layer 161 is applied to the opposite sides of the processed plate 160; the processed plate 160 is exposed and developed based on the position on the photo-etching layer 161 corresponding to the metal boss 142, specifically, the photo-etching layer 161 corresponding to the metal boss 142 can be avoided during exposure, so that chemical reaction is generated inside the photo-etching layer 161 except the photo-etching layer 161 corresponding to the metal boss 142 under the action of illumination, and molecular chains are crosslinked together to form a resist layer 162.
While the photolithographic layer 161 corresponding to the metal lands 142 is not irradiated with light, and the molecular chains thereof are not crosslinked together. The photo resist 161, which is not crosslinked in molecular chains, is dissolved by the developer solution to expose the metal bump 142.
The process plate 160 is etched until the metal boss 142 is removed to form the hollowed out groove 144.
Finally, all of the resist layer 162 is removed.
Step S27: attaching a solder mask layer at a third preset position on two opposite sides of the processed plate; and carrying out surface treatment on the exposed conductive circuits on the two opposite sides of the processed plate.
Referring further to fig. 3m, solder mask 166 is attached at a third predetermined position on opposite sides of the processed plate 160; and surface treating the exposed lines on opposite sides of the process plate 160.
The third preset position may be set based on an insulation requirement of the package substrate, which is not limited herein. The solder mask 166 has the effect of protecting and enhancing the aesthetics in addition to the ability to insulate the board.
The surface treatment is to form an organic protective film on the surface of the circuit by chemical action of liquid medicine so as to prevent the circuit from oxidizing and ensure the conductivity and signal transmission integrity of the circuit.
In a specific application scenario, the processed board 160 of the present step may be shipped as a finished package substrate, and the component soldering step may be performed by the user himself. The processing plate 160 in this step has prepared the hollow groove 144, and when the user welds the component by himself, the space of the hollow groove 144 can be used to realize full filling, so as to reduce the cavity abnormality.
Step S28: and welding the components on the bonding pads of the target conductive circuits, and performing plastic packaging on the components and the processed plate until the components are wrapped and the hollow grooves are filled, so as to prepare the packaging substrate.
Referring further to fig. 3n-3o, the component 170 is soldered to the pad 143 of the target conductive trace 141. The target conductive line 141 includes a line and a plurality of pads 143, and the pads 143 are soldered to the component 170. The plurality of pads 143 of the target conductive trace 141 may be soldered to the plurality of components 170, respectively, and may be specifically set based on actual requirements.
The present embodiment is directed to the case where the component 170 is soldered to the pad 143 by SMT mounting. SMT mounting is a circuit mounting technology for mounting a component 170 assembled on a surface of a pad 143 without a pin or a short lead, that is, the distance between the component 170 and the surface of the pad 143 in this mounting mode is short, so that the gap between the component 170 and the board is small, therefore, the gap between the component 170 and the board is enlarged by etching the metal boss 142, so that the plastic layer 180 can be smoothly filled into the gap between the component 170 and the board, and the cavity abnormality is reduced.
The component 170 and the processed board 160 are encapsulated until the component 170 is encapsulated and the hollow groove 144 is filled to obtain the molding layer 180, so as to prepare the package substrate 190.
The hollow groove 144 of the embodiment is prepared by etching the metal boss with the thickness ranging from 10 to 35 micrometers, so that the plastic layer 180 can be provided with enough filling space, so that the hollow groove 144 and the gap between the component 170 and the plate are filled, the abnormal cavity is reduced, and the structural reliability of the package substrate 190 is improved.
Through the steps, the preparation method of the packaging substrate of the embodiment prevents the situation that the dielectric layer is filled in the second preset position in the process of the subsequent at least one layer of conductive line, so that the subsequent dielectric layer is difficult to remove and the gap generated by welding the subsequent dielectric layer and the components is reduced by preparing the metal boss at the second preset position before preparing the at least one layer of conductive line. And the metal boss is etched to form a hollow groove, so that a gap generated by welding with a component is enlarged, filling of plastic packaging materials is facilitated, abnormal holes are reduced, and the structural reliability of the packaging substrate is improved.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of a package substrate provided in the present application.
The package substrate 500 of the present embodiment includes a target conductive trace 530, a dielectric layer 540, a conductive trace 560 and a solder mask layer 550 which are stacked and bonded in sequence, wherein a via 570 is formed in the dielectric layer 540, and the target conductive trace 530 and the conductive trace 560 are communicated through the via 570.
The hollow grooves 544 are formed on the target conductive traces 530 on one side of the package substrate 500, and the hollow grooves 544 penetrate through the corresponding target conductive traces 530 to expose the corresponding dielectric layer 540.
The package substrate of this embodiment is prepared by the method for preparing a package substrate of any one of the above embodiments.
The packaging substrate of the embodiment enlarges the gap generated by welding the follow-up components and parts to facilitate filling of plastic packaging materials, reduces the cavity abnormality and improves the structural reliability of the packaging substrate through the arrangement of the hollow groove.
Referring to fig. 6, fig. 6 is a schematic structural diagram of another embodiment of a package substrate provided in the present application.
The package substrate 600 of the present embodiment further includes a plastic layer 620 and a component 610 in addition to the package substrate 500 of the foregoing embodiment.
The conductive traces on one side of package substrate 600 include bond pads 630 and the traces themselves;
The component 610 and the bonding pad 630 may be soldered and fixed by a soldering layer 611.
The packaging substrate of the embodiment enlarges the gap generated by welding the components and the devices through the arrangement of the hollow groove, is convenient for filling the plastic packaging material, reduces the abnormal cavity and improves the structural reliability of the packaging substrate.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.
Claims (10)
1. The preparation method of the packaging substrate is characterized by comprising the following steps of:
obtaining a strippable carrier plate, wherein the strippable carrier plate comprises a substrate and a first conductive layer which is attached to at least one side of the substrate and is strippable;
thickening a first preset position and a second preset position of one side of each first conductive layer far away from the substrate, and correspondingly forming a target conductive circuit and a metal boss;
preparing at least one layer of conductive circuit on one side of each target conductive circuit far away from the substrate, and stripping the substrate and each corresponding first conductive layer to obtain at least one processing plate;
and etching each processing plate until the metal boss is removed to form a hollowed-out groove so as to prepare the packaging substrate.
2. The method for manufacturing a package substrate according to claim 1, wherein the step of thickening the first preset position and the second preset position of the side of each first conductive layer away from the substrate, and correspondingly forming the target conductive line and the metal boss, comprises:
attaching a protective layer to the first conductive layers at positions except for the first preset position and the second preset position on one side of the substrate far away from the first conductive layers;
electroplating and thickening one side of each first conductive layer far away from the substrate so as to form the target conductive circuit at the first preset position and form the metal boss at the second preset position.
3. The method of claim 1, wherein the step of preparing at least one layer of conductive traces on a side of each of the target conductive traces remote from the substrate, and stripping the substrate and the corresponding first conductive layers to obtain at least one processed board comprises:
laminating a dielectric layer on one side of each target conductive circuit far away from the substrate, and preparing the conductive circuit on one side of the dielectric layer far away from the substrate;
repeatedly preparing the conductive lines until the number of layers of the conductive lines on one side of each target conductive line far away from the substrate meets the preset number of layers;
and stripping the substrate and each corresponding first conductive layer, and removing the first conductive layers to obtain at least one processed plate.
4. A method of manufacturing a package substrate according to claim 3, wherein the step of manufacturing the conductive trace on a side of the dielectric layer remote from the substrate comprises:
drilling the dielectric layer from one side of the dielectric layer far away from the substrate to form a plurality of through holes, wherein each through hole exposes the corresponding target conductive circuit;
electroplating one side of the dielectric layer far away from the substrate until each through hole is filled to form a through hole, and forming a second conductive layer on one side of the dielectric layer far away from the substrate;
and etching the second conductive layer to obtain the conductive circuit.
5. The method of claim 1, wherein the step of etching each of the processed plate members until the metal boss is removed to form a hollowed-out groove, to prepare the package substrate comprises:
attaching photoetching layers on the whole plates on two opposite sides of the processed plate;
exposing and developing the processing plate based on the position, corresponding to the metal boss, on the photoetching layer;
and etching the processing plate until the metal boss is removed to form the hollow groove, so as to prepare the packaging substrate.
6. The method of manufacturing a package substrate according to claim 5, wherein the step of etching the processed plate until the metal boss is removed to form the hollowed-out groove, further comprises:
and welding the components on the bonding pads of the target conductive circuit, and performing plastic packaging on the components and the processing plate until the components are wrapped and the hollow grooves are filled, so as to prepare the packaging substrate.
7. The method of manufacturing a package substrate according to claim 6, wherein the step of soldering the component to the pad of the target conductive trace and plastic packaging the component and the processed board until the component is wrapped and the hollow groove is filled, further comprises, before the step of manufacturing the package substrate:
attaching a solder mask layer at a third preset position on two opposite sides of the processed plate; and
and carrying out surface treatment on the exposed conductive circuits on the two opposite sides of the processed plate.
8. The method of claim 1, wherein the metal bump has a thickness in the range of 10-35 microns.
9. A package substrate, characterized in that the package substrate is prepared by the method for preparing a package substrate according to any one of claims 1-8.
The packaging substrate comprises a packaging substrate and is characterized in that a hollowed-out groove is formed in a conductive circuit on one side of the packaging substrate, and the hollowed-out groove penetrates through the corresponding conductive circuit.
10. The package substrate of claim 9, further comprising a plastic layer and a component;
the conductive circuit on one side of the packaging substrate comprises a bonding pad;
the component is welded and fixed with the bonding pad, and the plastic sealing layer wraps the component and fills the hollow groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310028959.5A CN116169029A (en) | 2023-01-09 | 2023-01-09 | Packaging substrate and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310028959.5A CN116169029A (en) | 2023-01-09 | 2023-01-09 | Packaging substrate and preparation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN116169029A true CN116169029A (en) | 2023-05-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202310028959.5A Pending CN116169029A (en) | 2023-01-09 | 2023-01-09 | Packaging substrate and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116631883A (en) * | 2023-05-31 | 2023-08-22 | 苏州兴德森电子科技有限公司 | Packaging substrate and manufacturing method thereof, chip and manufacturing method thereof |
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2023
- 2023-01-09 CN CN202310028959.5A patent/CN116169029A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116631883A (en) * | 2023-05-31 | 2023-08-22 | 苏州兴德森电子科技有限公司 | Packaging substrate and manufacturing method thereof, chip and manufacturing method thereof |
| CN116631883B (en) * | 2023-05-31 | 2024-04-16 | 苏州兴德森电子科技有限公司 | Packaging substrate and manufacturing method thereof, chip and manufacturing method thereof |
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