CN116155090A

CN116155090A - Power supply circuit and power supply method

Info

Publication number: CN116155090A
Application number: CN202111390349.7A
Authority: CN
Inventors: 潘均宏; 陈力辅
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-11-23
Filing date: 2021-11-23
Publication date: 2023-05-23

Abstract

A power supply circuit comprises a first high-voltage switch, a first low-voltage switch, a second high-voltage switch, a second low-voltage switch and a control circuit. The first high-voltage switch is used for receiving a first input voltage and generating a first node voltage. The first low-voltage switch is coupled between the first high-voltage switch and the output end. The second high-voltage switch is used for receiving a second input voltage and generating a second node voltage. The second low-voltage switch is coupled between the second high-voltage switch and the output end. The control circuit is used for controlling the first high-voltage switch, the first low-voltage switch, the second high-voltage switch and the second low-voltage switch according to the first node voltage and the second node voltage so that the output end outputs output voltage.

Description

Power supply circuit and power supply method

Technical Field

The present disclosure relates to a power supply technology, and more particularly, to a power supply circuit and a power supply method capable of saving circuit area.

Background

With the development of technology, electronic devices have more and more functions and application scenarios. Based on this, many electronic devices are designed with multiple power ports to support various functions or to be suitable for various application scenarios. To control these power ports, a control chip can be disposed inside the electronic device. The control chip can conduct one of the power paths of the power ports to supply power to the rear circuit, and cut off the power paths of the other power ports to avoid current flowing backward.

Disclosure of Invention

Some embodiments of the present disclosure relate to a power supply circuit. The power supply circuit comprises a first high-voltage switch, a first low-voltage switch, a second high-voltage switch, a second low-voltage switch and a control circuit. The first high-voltage switch is used for receiving a first input voltage and generating a first node voltage. The first low-voltage switch is coupled between the first high-voltage switch and the output end. The second high-voltage switch is used for receiving a second input voltage and generating a second node voltage. The second low-voltage switch is coupled between the second high-voltage switch and the output end. The control circuit is used for controlling the first high-voltage switch, the first low-voltage switch, the second high-voltage switch and the second low-voltage switch according to the first node voltage and the second node voltage so that the output end outputs output voltage.

Some embodiments of the present disclosure relate to a power supply method. The power supply method comprises the following operations: receiving a first input voltage and generating a first node voltage by a first high voltage switch; receiving a second input voltage and generating a second node voltage by a second high voltage switch; and controlling the first high-voltage switch, the first low-voltage switch, the second high-voltage switch and the second low-voltage switch by the control circuit according to the first node voltage and the second node voltage so as to enable the output end to output the output voltage. The first low-voltage switch is coupled between the first high-voltage switch and the output end, and the second low-voltage switch is coupled between the second high-voltage switch and the output end.

In summary, in the power supply circuit and the power supply method of the present disclosure, some components may be implemented by low-voltage components. Therefore, the circuit area can be saved, and the chip cost can be further reduced.

Drawings

The foregoing and other objects, features, advantages and embodiments of the present disclosure will be apparent from the following description of the drawings in which:

FIG. 1 is a schematic diagram of a power supply circuit shown according to some embodiments of the present disclosure;

FIG. 2 is a waveform diagram of the power supply circuit of FIG. 1 shown in accordance with some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a power supply circuit shown according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of a power supply circuit shown according to some embodiments of the present disclosure; and

fig. 5 is a flow chart of a power supply method shown according to some embodiments of the present disclosure.

Detailed Description

The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected," may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.

Referring to fig. 1, fig. 1 is a schematic diagram of a power supply circuit 100 shown according to some embodiments of the present disclosure.

Taking fig. 1 as an example, the power supply circuit 100 can receive an input voltage VIN1 and an input voltage VIN2. The power supply circuit 100 may turn on one of the input voltage VIN1 and the input voltage VIN2 and turn off the other. For example, when the power supply circuit 100 turns on the power path corresponding to the input voltage VIN1, the power path corresponding to the input voltage VIN2 is cut off. Conversely, when the power supply circuit 100 turns on the power path corresponding to the input voltage VIN2, the power path corresponding to the input voltage VIN1 is cut off.

Then, the power supply circuit 100 can generate the output voltage VOUT at the output terminal OUT according to the input voltage (the input voltage VIN1 or the input voltage VIN 2) of the conductive power path. In some embodiments, the output voltage VOUT is less than the input voltage VIN1 (or input voltage VIN 2). That is, the power supply circuit 100 can not only conduct one of the power paths, but also perform voltage conversion (e.g. voltage reduction) on the corresponding input voltage to generate the output voltage VOUT.

In some embodiments, the voltage value of the input voltage VIN1 is different from the voltage value of the input voltage VIN2. Take the example that the power supply circuit 100 (e.g. power control chip) is disposed in a notebook computer. The input voltage VIN1 may come from a charger and be, for example, 20 volts. The input voltage VIN2 may come from a battery in a notebook computer and be, for example, 12 volts. The power supply circuit 100 may switch on one of the power paths and switch off the other power path, and convert 20 volts or 12 volts to 3.3 volts as the output voltage VOUT. The output voltage VOUT of 3.3 volts may then be used to power other chips or other circuitry in a notebook computer.

However, the present disclosure is not limited to the above examples, and various applicable cases are within the scope of the present disclosure.

Taking fig. 1 as an example, the power supply circuit 100 includes a high voltage switch HS1, a low voltage switch LS1, a high voltage switch HS2, a low voltage switch LS2, and a control circuit 110. The high voltage switch HS1 and the high voltage switch HS2 may be implemented with N-type transistors, and the low voltage switch LS1 and the low voltage switch LS2 may be implemented with P-type transistors.

The high voltage switch HS1 is configured to receive an input voltage VIN1. The low voltage switch LS1 is coupled between the high voltage switch HS1 and the output terminal OUT. The high voltage switch HS1 forms a first power supply path with the low voltage switch LS1. The high voltage switch HS1 generates a node voltage VL1 at a node N1 between the high voltage switch HS1 and the low voltage switch LS1 according to the input voltage VIN1 and a control signal VG1 from the control circuit 110.

The high voltage switch HS2 is used for receiving the input voltage VIN2. The low voltage switch LS2 is coupled between the high voltage switch HS2 and the output terminal OUT. The high voltage switch HS2 forms a second power supply path with the low voltage switch LS2. The high voltage switch HS2 generates a node voltage VL2 at a node N2 between the high voltage switch HS2 and the low voltage switch LS2 according to the input voltage VIN2 and the control signal VG2 from the control circuit 110.

In some related art, the switch for receiving the input voltage is implemented as a P-type transistor. In these related arts, a high-voltage to low-voltage circuit is additionally provided behind the switches.

In comparison with the above-described related arts, in the present disclosure, the high-voltage switches HS1 and HS2 for receiving the input voltages VIN1 and VIN2 are implemented with N-type transistors. The high voltage switches HS1 and HS2 implemented with N-type transistors have the effect of blocking high voltages. Taking the high voltage switch HS1 as an example, when the difference between the gate voltage of the high voltage switch HS1 and the source voltage of the high voltage switch HS1 is greater than the threshold voltage of the high voltage switch HS1, the high voltage switch HS1 is turned on and the source voltage (node voltage VL 1) of the high voltage switch HS1 is pulled up according to the drain voltage (input voltage VIN 1) of the high voltage switch HS1. However, when the difference between the gate voltage of the high voltage switch HS1 and the source voltage of the high voltage switch HS1 is equal to or less than the threshold voltage of the high voltage switch HS1, the high voltage switch HS1 is turned off. That is, the source voltage (node voltage VL 1) of the high voltage switch HS1 is limited by the gate voltage (voltage value of the control signal VG 1) of the high voltage switch HS1, so that the node voltages VL1 and VL2 are low voltage outputs. Accordingly, the present disclosure does not require an additional high-to-low voltage circuit disposed behind the high-voltage switches HS1 and HS2, thereby reducing the circuit area and the chip cost.

Then, the control circuit 110 can control the high voltage switch HS1, the low voltage switch LS1, the high voltage switch HS2 and the low voltage switch LS2 according to the node voltage VL1 and the node voltage VL2, so that the output voltage VOUT is generated at the output terminal OUT.

Taking fig. 1 as an example, the control circuit 110 includes a low voltage comparator 111, a low voltage controller 112, and an inverter 113. The low voltage comparator 111 includes a first input terminal, a second input terminal, and an output terminal. The low voltage controller 112 includes an input, a first output, a second output, and a third output. Inverter 113 includes an input and an output.

The first input terminal of the low voltage comparator 111 is coupled to the node N1 between the high voltage switch HS1 and the low voltage switch LS1 to receive the node voltage VL1. A second input terminal of the low voltage comparator 111 is coupled to a node N2 between the high voltage switch HS2 and the low voltage switch LS2 to receive the node voltage VL2. An output terminal of the low voltage comparator 111 is coupled to an input terminal of the low voltage controller 112. A first output terminal of the low voltage controller 112 is coupled to a gate terminal of the high voltage switch HS1. A second output terminal of the low voltage controller 112 is coupled to a gate terminal of the high voltage switch HS2. The third output terminal of the low voltage controller 112 is coupled to the gate terminal of the low voltage switch LS1 and the input terminal of the inverter 113. The output terminal of the inverter 113 is coupled to the gate terminal of the low voltage switch LS2.

Referring to fig. 1 and 2 simultaneously. Fig. 2 is a waveform diagram of the power supply circuit 100 of fig. 1, shown according to some embodiments of the present disclosure.

Taking fig. 2 as an example, in the first stage, if the input voltage VIN1 is greater than the input voltage VIN2, the voltage value of the control signal VG1 can be preset to be greater than the voltage value of the control signal VG2. In this case, as described above, since the node voltage VL1 (the source voltage of the high voltage switch HS 1) is limited by the voltage value of the control signal VG1 (the gate voltage of the high voltage switch HS 1) and the node voltage VL2 (the source voltage of the high voltage switch HS 2) is limited by the voltage value of the control signal VG2 (the gate voltage of the high voltage switch HS 2), the node voltage VL1 will be greater than the node voltage VL2. The low voltage comparator 111 may compare the node voltage VL1 and the node voltage VL2 to generate a comparison result signal cmp_out. When the node voltage VL1 is greater than the node voltage VL2, the low voltage comparator 111 may output a comparison result signal cmp_out having a first logic value (e.g., logic value 0).

The low voltage controller 112 may receive the comparison result signal cmp_out having a first logic value (e.g., logic value 0), and output the control signal CS to control the low voltage switches LS1 and LS2 according to the comparison result signal cmp_out having the first logic value (e.g., logic value 0). In detail, the low voltage controller 112 may output a control signal CS having a first logic value (e.g., logic value 0) to turn on the low voltage switch LS1 according to the comparison result signal cmp_out having the first logic value (e.g., logic value 0). Since the low voltage switch LS1 and the high voltage switch HS1 are both turned on, the first power path corresponding to the input voltage VIN1 is turned on. The turned-on high voltage switch HS1 may generate the node voltage VL1 and the node voltage VL1 may charge the output terminal OUT through the turned-on low voltage switch LS1 such that the output voltage VOUT in the first stage is close to the node voltage VL1. On the other hand, the inverter 113 may generate an inverted control signal CSB having a second logic value (e.g., logic value 1) according to a control signal CS having a first logic value (e.g., logic value 0) from the low voltage controller 112. The inverted control signal CSB turns off the low voltage switch LS2. Since the low voltage switch LS2 is off, the second power supply path corresponding to the input voltage VIN2 is cut off to avoid current backflow.

As the node voltage VL1 (the input voltage VIN 1) continuously charges the output terminal OUT, the node voltage VL1 (the input voltage VIN 1) decreases after entering the second stage. Taking fig. 2 as an example, after entering the second stage, the node voltage VL1 is turned to be smaller than the node voltage VL2.

The low voltage comparator 111 may compare the node voltage VL1 and the node voltage VL2 to generate a comparison result signal cmp_out. When the node voltage VL1 is smaller than the node voltage VL2, the low voltage comparator 111 may output a comparison result signal cmp_out having a second logic value (e.g., logic value 1). In some embodiments, the low voltage comparator 111 has a delay time DT. That is, the time point when the comparison result signal CMP_OUT transitions to have the second logic value (e.g., logic value 1) (end time point T2 of the second stage in FIG. 2) is later than the time point when the node voltage VL1 transitions to be smaller than the node voltage VL2 (start time point T1 of the second stage in FIG. 2) by the delay time DT. Within the delay time DT (i.e., in the second phase), the high voltage switch HS1 and the low voltage switch LS1 (i.e., the first power path) are still on. However, since the input voltage VIN1 (node voltage VL 1) of the first power path is smaller and the second power path is not turned on, the output voltage VOUT is slightly decreased in the second stage.

After the delay time DT has elapsed (i.e., the third stage is entered), the comparison result signal cmp_out transitions to have a second logic value (e.g., logic value 1). The low voltage controller 112 may receive the comparison result signal cmp_out having the second logic value (e.g., logic value 1), and output the control signal CS to control the low voltage switch LS1 and the low voltage switch LS2 according to the comparison result signal cmp_out having the second logic value (e.g., logic value 1). In detail, the low voltage controller 112 may output the control signal CS having a second logic value (e.g., logic value 1) to turn off the low voltage switch LS1 according to the comparison result signal cmp_out having the second logic value (e.g., logic value 1). Since the low-voltage switch LS1 is turned off, the first power supply path corresponding to the input voltage VIN1 is cut off, and current flowing backward can be avoided. On the other hand, the inverter 113 may generate the inverted control signal CSB having the first logic value (e.g., logic value 0) according to the control signal CS having the second logic value (e.g., logic value 1) from the low voltage controller 112. The inverted control signal CSB turns on the low voltage switch LS2. Since the high voltage switch HS2 and the low voltage switch LS2 are both turned on, the second power path corresponding to the input voltage VIN2 is turned on. In this case, the turned-on high voltage switch HS2 may generate the node voltage VL2 and the node voltage VL2 may charge the output terminal OUT through the turned-on low voltage switch LS2 so that the output voltage VOUT may rise again and approach the node voltage VL2 in the third stage. On the other hand, the low voltage controller 112 may decrease the voltage value of the control signal VG1 and increase the voltage value of the control signal VG2 (increase the upper limit of the node voltage VL 2) according to the comparison result signal cmp_out having the second logic value (e.g., logic value 1).

It should be noted that the "high voltage" switch and the "low voltage" switch refer to a switch having a relatively high voltage resistance and a switch having a relatively low voltage resistance, respectively. That is, the withstand voltage of the high voltage switch HS1 (or the high voltage switch HS 2) is greater than the withstand voltage of the low voltage switch LS1 (or the low voltage switch LS 2). In some embodiments, the withstand voltage of the high voltage switch HS1 (or the high voltage switch HS 2) is equal to or greater than 20 volts, and the withstand voltage of the low voltage switch LS1 (or the low voltage switch LS 2) is equal to or less than 5 volts, but not limited thereto. For example, in other embodiments, the withstand voltage of the high voltage switch HS1 (or the high voltage switch HS 2) is equal to or greater than 14 volts, and the withstand voltage of the low voltage switch LS1 (or the low voltage switch LS 2) is equal to or less than 6 volts.

In addition, the aforementioned "low voltage" comparator and "low voltage" controller means that they are implemented by "low voltage" transistors. And a "low voltage" transistor refers to a transistor of low withstand voltage. In some embodiments, the withstand voltage of the low voltage transistor is equal to or less than 5 volts, but not limited thereto.

In some related art, the control circuit is implemented by a high voltage element (e.g., a high withstand voltage transistor). In these related arts, since the high-voltage element is large in size, the circuit area of the control circuit realized by the high-voltage element is large. In addition, the reaction rate of the high-voltage element is also slower than that of the low-voltage element.

In comparison with the above-mentioned related arts, in the present disclosure, as described above, the source voltage (node voltage VL 1) of the high voltage switch HS1 is limited by the gate voltage (voltage value of the control signal VG 1) of the high voltage switch HS1 and the source voltage (node voltage VL 2) of the high voltage switch HS2 is limited by the gate voltage (voltage value of the control signal VG 2) of the high voltage switch HS2, so the node voltages VL1 and VL2 are low voltage outputs. Accordingly, the rear control circuit 110 can be realized by a low voltage element (e.g., a low withstand voltage transistor). The low voltage device is smaller in size and faster in response than the high voltage device. Therefore, the circuit area can be reduced, the chip cost can be reduced, and the circuit performance can be improved.

In some embodiments, the low voltage comparator 111 has a voltage hysteresis mechanism to avoid circuit malfunction. Taking the above embodiment as an example, when the low voltage comparator 111 detects that the node voltage VL1 is greater than the node voltage VL2, the comparison result signal cmp_out is not changed immediately. The low voltage comparator 111 does not transition to output the comparison result signal cmp_out having the first logic value (e.g., logic value 0) until the low voltage comparator 111 detects that the difference between the node voltage VL1 and the node voltage VL2 is greater than a threshold value (e.g., without limitation, 100 millivolts). In contrast, when the low voltage comparator 111 detects that the node voltage VL2 is greater than the node voltage VL1, the comparison result signal cmp_out is not changed immediately. The low voltage comparator 111 does not transition to output the comparison result signal cmp_out having the second logic value (e.g., logic value 1) until the low voltage comparator 111 detects that the difference between the node voltage VL2 and the node voltage VL1 is greater than the threshold value.

Although the above embodiment takes the control signal VG1 preset to be greater than the voltage value of the control signal VG2 as an example, the disclosure is not limited thereto. In some other embodiments, the voltage value of the control signal VG1 can be preset to be equal to the voltage value of the control signal VG2.

For example, if the input voltage VIN1 is different from the input voltage VIN2, the voltage value of the control signal VG1 is greater than the voltage value of the input voltage VIN1 and the difference between the two is greater than the threshold voltage of the high voltage switch HS1, and the voltage value of the control signal VG2 is greater than the input voltage VIN2 and the difference between the two is greater than the threshold voltage of the high voltage switch HS2. Although the voltage value of the control signal VG1 is equal to the voltage value of the control signal VG2, the voltage value of the node voltage VL1 may rise to be equal to the voltage value of the input voltage VIN1 and the voltage value of the node voltage VL2 may rise to be equal to the voltage value of the input voltage VIN2. Since the input voltage VIN1 is different from the input voltage VIN2 (the node voltage VL1 is different from the node voltage VL 2), the low voltage comparator 111 can still compare the node voltage VL1 with the node voltage VL2 to generate the comparison result signal cmp_out, and the low voltage controller 112 can perform the subsequent operations according to the comparison result signal cmp_out.

For another example, if the voltage value of the control signal VG1 is smaller than the voltage value of the input voltage VIN1 and the voltage value of the control signal VG2 is smaller than the voltage value of the input voltage VIN2. In this case, the node voltage VL1 may be limited by the voltage value of the control signal VG1 and the node voltage VL2 may be limited by the voltage value of the control signal VG2. Although the voltage value of the control signal VG1 is equal to the voltage value of the control signal VG2, the node voltage corresponding to the larger input voltage will rise earlier to the voltage value of the control signal VG1 or VG2. At this time, the voltage of the other node has not risen to the voltage value of the control signal VG1 or VG2. Accordingly, the low voltage comparator 111 can still compare the node voltage VL1 (e.g., the voltage value of the control signal VG1 has been increased) with the node voltage VL2 (e.g., the voltage value of the control signal VG2 has not been increased) to generate the comparison result signal CMP_OUT, and the low voltage controller 112 can perform the subsequent operations according to the comparison result signal CMP_OUT. For example, the low voltage controller 112 may decrease the voltage value of the control signal (e.g., control signal VG 2) corresponding to the smaller input voltage to decrease the upper limit of the node voltage (e.g., node voltage VL 2) of the power supply path.

In addition, although the above embodiment takes the example that the voltage value of the input voltage VIN1 is different from the voltage value of the input voltage VIN2, the disclosure is not limited thereto. In some other embodiments, the voltage value of the input voltage VIN1 may be the same as the voltage value of the input voltage VIN2. In these other embodiments, the node voltage VL1 and the node voltage VL2 may be controlled by designing the voltage value of the control signal VG1 and the voltage value of the control signal VG2. Accordingly, the low voltage comparator 111 can still compare the node voltage VL1 with the node voltage VL2 to generate the comparison result signal cmp_out, and the low voltage controller 112 can perform the subsequent operations according to the comparison result signal cmp_out.

Referring to fig. 3, fig. 3 is a schematic diagram of a power supply circuit 300 shown according to some embodiments of the present disclosure. The circuit architecture and operation of the power supply circuit 300 in fig. 3 is similar to that of the power supply circuit 100 in fig. 1.

One of the main differences between the power supply circuit 300 and the power supply circuit 100 is that the low voltage controller 312 of the control circuit 310 further includes a gate voltage adjusting circuit 3121, and the low voltage controller 312 is further configured to receive the enable signal EN1 and the enable signal EN2. The enable signal EN1 and the enable signal EN2 may come from a digital circuit.

In some cases, similar to the low voltage controller 112 in fig. 1, the low voltage controller 312 may control the high voltage switch HS1, the low voltage switch LS1, the high voltage switch HS2, and the low voltage switch LS2 according to the comparison result signal cmp_out from the low voltage comparator 111.

In some cases, the low voltage controller 312 can also control the high voltage switch HS1, the low voltage switch LS1, the high voltage switch HS2 and the low voltage switch LS2 according to the enable signal EN1 and the enable signal EN2.

For example, when the enable signal EN1 has an enable level, the enable signal EN2 may have a disable level. The low voltage controller 312 may control the voltage adjusting circuit 3121 to output the control signal VG1 according to the enable signal EN1 having the enable level, and control the voltage adjusting circuit 3121 to output the control signal VG2 according to the enable signal EN2 having the disable level. For example, the gate voltage adjusting circuit 3121 can output a control signal VG1 with a larger voltage value and a control signal VG2 with a smaller voltage value to control the high voltage switch HS1 and the high voltage switch HS2, respectively. On the other hand, the low voltage controller 312 may output a control signal CS having a first logic value (e.g., logic value 0) to turn on the low voltage switch LS1 according to the enable signal EN1 having the enable level and the enable signal EN2 having the disable level, and the inverter 113 may generate an inverted control signal CSB having a second logic value (e.g., logic value 1) to turn off the low voltage switch LS2 according to the control signal CS having the first logic value (e.g., logic value 0). That is, the low voltage controller 312 may turn on the first power path corresponding to the input voltage VIN1 and turn off the second power path corresponding to the input voltage VIN2 according to the enable signal EN1 having the enable level and the enable signal EN2 having the disable level.

Conversely, when the enable signal EN2 has an enable level, the enable signal EN1 may have a disable level. The low voltage controller 312 may control the gate voltage adjusting circuit 3121 to output the control signal VG2 according to the enable signal EN2 having the enable level, and control the voltage adjusting circuit 3121 to output the control signal VG1 according to the enable signal EN1 having the disable level. For example, the gate voltage adjusting circuit 3121 can output the control signal VG2 with a larger voltage value and the control signal VG1 with a smaller voltage value to control the high voltage switch HS2 and the high voltage switch HS1, respectively. On the other hand, the low voltage controller 312 may output the control signal CS having a second logic value (e.g., logic value 1) to turn off the low voltage switch LS1 according to the enable signal EN2 having the enable level and the enable signal EN1 having the disable level, and the inverter 113 may generate the inverted control signal CSB having the first logic value (e.g., logic value 0) to turn on the low voltage switch LS2 according to the control signal CS having the second logic value (e.g., logic value 1). That is, the low voltage controller 312 may turn on the second power path corresponding to the input voltage VIN2 and turn off the first power path corresponding to the input voltage VIN1 according to the enable signal EN2 having the enable level and the enable signal EN1 having the disable level.

Referring to fig. 4, fig. 4 is a schematic diagram of a power supply circuit 400 shown according to some embodiments of the present disclosure. The circuit architecture and operation of the power supply circuit 400 in fig. 4 is similar to that of the power supply circuit 300 in fig. 3.

The following description is mainly directed to main differences between the power supply circuit 400 and the power supply circuit 300.

The power supply circuit 400 further includes a high voltage switch HS3 and a low voltage switch LS3. In some embodiments, the high voltage switch HS3 may be implemented with an N-type transistor and the low voltage switch LS3 may be implemented with a P-type transistor.

The high voltage switch HS3 is used for receiving the input voltage VIN3. The low voltage switch LS3 is coupled between the high voltage switch HS3 and the output terminal OUT. The high voltage switch HS3 forms a third power supply path with the low voltage switch LS3. The high voltage switch HS3 generates a node voltage VL3 at a node N3 between the high voltage switch HS3 and the low voltage switch LS3 according to the input voltage VIN3 and the control signal VG3 from the control circuit 410.

In some embodiments, the voltage value of the input voltage VIN1, the voltage value of the input voltage VIN2, and the voltage value of the input voltage VIN3 are the same as each other. In some embodiments, the voltage value of the input voltage VIN1, the voltage value of the input voltage VIN2, and the voltage value of the input voltage VIN3 are not identical to each other.

The control circuit 410 may control the high voltage switch HS1, the low voltage switch LS1, the high voltage switch HS2, the low voltage switch LS2, the high voltage switch HS3 and the low voltage switch LS3 according to the node voltage VL1, the node voltage VL2 and the node voltage VL3 to control whether the first power path, the second power path and the third power path are turned on or not, so as to generate the output voltage VOUT at the output terminal OUT.

Taking fig. 4 as an example, the control circuit 410 includes a low voltage comparator 411 and a low voltage controller 412. The low voltage controller 412 includes a gate voltage regulator circuit 4121.

The low voltage comparator 411 may compare the node voltage VL1, the node voltage VL2, and the node voltage VL3 to generate a comparison result signal cmp_out1 and a comparison result signal cmp_out2. The low voltage controller 412 can generate the control signal VG1, the control signal VG2, the control signal VG3, the control signal CS1, the control signal CS2 and the control signal CS3 according to the comparison result signal cmp_out1 and the comparison result signal cmp_out2 to control the high voltage switch HS1, the high voltage switch HS2, the high voltage switch HS3, the low voltage switch LS1, the low voltage switch LS2 and the low voltage switch LS3, respectively. The detailed control manner is similar to the previous embodiment, and thus will not be repeated here. In short, the low voltage controller 412 may turn on the power supply path corresponding to the maximum node voltage (the maximum one of the node voltages VL1, VL2, and VL 3) and cut off other power supply paths.

Similar to the previous embodiments, in some cases, the low voltage controller 412 may control the high voltage switch HS1, the low voltage switch LS1, the high voltage switch HS2, the low voltage switch LS2, the high voltage switch HS3, and the low voltage switch LS3 directly according to the enable signal EN1, the enable signal EN2, and the enable signal EN 3. For example, when the enable signal EN1 has an enable level, the low voltage controller 412 may turn on the first power path (the high voltage switch HS1 and the low voltage switch LS 1) corresponding to the input voltage VIN1. When the enable signal EN2 has an enable level, the low voltage controller 412 may turn on the second power path (the high voltage switch HS2 and the low voltage switch LS 2) corresponding to the input voltage VIN2. When the enable signal EN3 has an enable level, the low voltage controller 412 may turn on the third power path (the high voltage switch HS3 and the low voltage switch LS 3) corresponding to the input voltage VIN3.

The "high voltage" switch and the "low voltage" switch refer to a switch having a relatively high voltage resistance and a switch having a relatively low voltage resistance, respectively. That is, the withstand voltage of the high voltage switch HS3 is greater than that of the low voltage switch LS3. For example, the withstand voltage of the high voltage switch HS3 is equal to or greater than 20 volts, and the withstand voltage of the low voltage switch LS3 is equal to or less than 5 volts, but not limited thereto.

In some other embodiments, the power supply circuit may also include more than three power paths. That is, these power supply circuits may include more than three high voltage switches and more than three low voltage switches. The circuit architecture and operation of these power supply circuits are similar to those of the power supply circuit 400, and thus will not be described here again.

Referring to fig. 5, fig. 5 is a flow chart of a power supply method 500 shown according to some embodiments of the present disclosure. In some embodiments, the power supply method 500 may be applied to the power supply circuit 100 of fig. 1, the power supply circuit 300 of fig. 3, and the power supply circuit 400 of fig. 4. For ease of understanding, the power supply method 500 will be described in connection with the power supply circuit 100 of fig. 1.

Taking fig. 5 as an example, the power supply method 500 includes operation S510, operation S520, and operation S530.

In operation S510, an input voltage VIN1 is received by the high-voltage switch HS1 and a node voltage VL1 is generated. In some embodiments, the high voltage switch HS1 is implemented with an N-type transistor. The low voltage switch LS1 is coupled between the high voltage switch HS1 and the output terminal OUT.

In operation S520, the input voltage VIN2 is received by the high-voltage switch HS2 and the node voltage VL2 is generated. In some embodiments, the high voltage switch HS2 is implemented with an N-type transistor. And the low voltage switch LS2 is coupled between the high voltage switch HS2 and the output terminal OUT.

In operation S530, the control circuit 110 controls the high voltage switch HS1, the low voltage switch LS1, the high voltage switch HS2 and the low voltage switch LS2 according to the node voltage VL1 and the node voltage VL2, so that the output voltage VOUT is generated at the output terminal OUT. In some embodiments, the low voltage comparator 111 compares the node voltage VL1 and the node voltage VL2 to generate a comparison result signal cmp_out, and the low voltage controller 112 outputs the control signal VG1, the control signal VG2 and the control signal CS to control the high voltage switch HS1, the low voltage switch LS1, the high voltage switch HS2 and the low voltage switch LS2 according to the comparison result signal cmp_out.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that the present disclosure is not limited thereto, and that various changes and modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the present disclosure, and therefore, the scope of the present disclosure should be limited only by the scope of the appended claims.

Reference numerals

100,300,400 power supply circuit

110,310,410 control circuit

111,411 low voltage comparator

112,312,412 Low pressure controller

113 inverter

3121,4121 Gate Voltage regulator Circuit

500 power supply method

VIN1, VIN2, VIN3 input Voltage

VOUT: output voltage

OUT: output terminal

HS1, HS2, HS3 high-voltage switch

LS1, LS2, LS3 low voltage switch

VL1, VL2, VL3 node voltage

CMP_OUT, CMP_OUT1, CMP_OUT2 comparison result Signal

VG1, VG2, VG3, CS, CS1, CS2, CS3: control signal

CSB inverse control signal

DT delay time

T1, T2 time Point

N1, N2, N3: nodes

EN1, EN2, EN3 enable signal

S510, S520, S530 operation

Claims

1. A power supply circuit, comprising:

the first high-voltage switch is used for receiving a first input voltage and generating a first node voltage;

the first low-voltage switch is coupled between the first high-voltage switch and the output end;

the second high-voltage switch is used for receiving a second input voltage and generating a second node voltage;

a second low voltage switch coupled between the second high voltage switch and the output terminal; and

the control circuit is used for controlling the first high-voltage switch, the first low-voltage switch, the second high-voltage switch and the second low-voltage switch according to the first node voltage and the second node voltage so that the output end outputs output voltage.

2. The power supply circuit according to claim 1, wherein a withstand voltage of the first high-voltage switch is greater than a withstand voltage of the first low-voltage switch, and a withstand voltage of the second high-voltage switch is greater than a withstand voltage of the second low-voltage switch.

3. The power supply circuit according to claim 2, wherein a withstand voltage of the first high-voltage switch or a withstand voltage of the second high-voltage switch is equal to or greater than 20 volts, wherein a withstand voltage of the first low-voltage switch or a withstand voltage of the second low-voltage switch is equal to or less than 5 volts.

4. The power supply circuit of claim 1, wherein the first high voltage switch and the second high voltage switch are implemented with N-type transistors, wherein the first low voltage switch and the second low voltage switch are implemented with P-type transistors.

5. The power supply circuit of claim 1, wherein the control circuit comprises:

a low voltage comparator for comparing the first node voltage and the second node voltage to generate a comparison result signal;

the low-voltage controller is used for controlling the first high-voltage switch, the first low-voltage switch, the second high-voltage switch and the second low-voltage switch according to the comparison result signal or at least one enabling signal; and

and the inverter is used for receiving the control signal and generating an inverted control signal according to the control signal, wherein the control signal is used for controlling the first low-voltage switch, and the inverted control signal is used for controlling the second low-voltage switch.

6. The power supply circuit of claim 5, wherein the low voltage comparator has a voltage hysteresis mechanism.

7. The power supply circuit of claim 6, wherein the low voltage comparator outputs the comparison result signal having a first logic value when the first node voltage is greater than the second node voltage and a difference between the first node voltage and the second node voltage is greater than a threshold value, wherein the low voltage comparator outputs the comparison result signal having a second logic value when the second node voltage is greater than the first node voltage and the difference between the second node voltage and the first node voltage is greater than the threshold value.

8. The power supply circuit of claim 5, wherein the low voltage controller comprises a gate voltage regulation circuit, and the gate voltage regulation circuit is configured to control the first high voltage switch and the second high voltage switch.

9. The power supply circuit of claim 1, further comprising:

the third high-voltage switch is used for receiving a third input voltage and generating a third node voltage; and

a third low voltage switch coupled between the third high voltage switch and the output terminal,

wherein the control circuit further comprises:

a low voltage comparator for comparing the first node voltage, the second node voltage, and the third node voltage to generate a first comparison result signal and a second comparison result signal; and

the low voltage controller is configured to control the first high voltage switch, the first low voltage switch, the second high voltage switch, the second low voltage switch, the third high voltage switch and the third low voltage switch according to the first comparison result signal and the second comparison result signal or at least one enable signal.

10. A power supply method, comprising:

receiving a first input voltage and generating a first node voltage by a first high voltage switch;

receiving a second input voltage and generating a second node voltage by a second high voltage switch; and

the control circuit controls the first high voltage switch, the first low voltage switch, the second high voltage switch and the second low voltage switch according to the first node voltage and the second node voltage so that the output end outputs an output voltage,

the first low-voltage switch is coupled between the first high-voltage switch and the output end, and the second low-voltage switch is coupled between the second high-voltage switch and the output end.