CN116153867A - Chip package structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a chip packaging structure and its manufacturing method, wherein the chip packaging structure includes a substrate, at least one first chip, an adhesive material, a redistribution circuit structure and a plurality of second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one groove. At least one first chip is disposed in the groove. The adhesive material is disposed in at least one groove and located between the substrate and at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate and is electrically connected to at least one first chip. A plurality of second chips are disposed on the redistribution circuit structure and electrically connected to the redistribution circuit structure. The chip packaging structure and the manufacturing method of the present invention have the technical effect of reducing the overall thickness or effectively improving the yield of products.

Description

Chip package structure and manufacturing method thereof

technical field

The invention relates to a packaging structure, in particular to a chip packaging structure and a manufacturing method thereof.

Background technique

Currently, in submillimeter light-emitting diode (mini LED) panels or micro light-emitting diode (micro LED) panels, sub-millimeter light-emitting diodes or micro light-emitting diodes are usually arranged on the front surface of a printed circuit board (or IC substrate), and The packaged driver IC (driver IC) is disposed on the back surface or side of the printed circuit board (or IC carrier). In this way, the overall thickness of the panel will be increased.

In addition, since printed circuit boards (or IC substrates) often have problems of warpage and poor copper surface flatness, it is not conducive to the mass transfer of micro-LEDs, and increases the possibility of assembly failure, thereby affecting the quality of the finished product. yield.

Contents of the invention

The invention is aimed at a circuit substrate structure and a manufacturing method thereof, which has the technical effect of reducing the overall thickness or effectively improving the yield of products.

The chip packaging structure of the present invention includes a substrate, at least one first chip, adhesive material, redistribution circuit structure and a plurality of second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one groove. At least one first chip is disposed in the groove. The adhesive material is disposed in at least one groove and located between the substrate and at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate and is electrically connected to at least one first chip. A plurality of second chips are disposed on the redistribution circuit structure and electrically connected to the redistribution circuit structure.

In an embodiment of the present invention, the aforementioned substrate is a glass substrate or a silicon substrate.

In an embodiment of the present invention, the above-mentioned at least one first chip is a bare die.

In an embodiment of the present invention, the above-mentioned plurality of second chips include bare die and/or packaged chips.

In an embodiment of the present invention, the above-mentioned redistribution wiring structure includes a first dielectric layer, a first patterned wiring layer, a first via hole, a second dielectric layer, a second patterned wiring layer, and a second Via hole. The first dielectric layer is disposed on the first surface of the substrate. The first patterned circuit layer is disposed on the first dielectric layer. The first via hole penetrates the first dielectric layer, and the first via hole electrically connects the first patterned circuit layer and at least one first chip. The second dielectric layer is disposed on the first patterned circuit layer. The second patterned circuit layer is disposed on the second dielectric layer. The second via hole penetrates the second dielectric layer, and the second via hole electrically connects the second patterned circuit layer and the first patterned circuit layer.

In an embodiment of the present invention, the active surface of the at least one first chip is flush with the first surface of the substrate.

In an embodiment of the present invention, the above-mentioned chip packaging structure further includes a connector. The connector is disposed on the redistribution wiring structure, wherein the plurality of second chips are electrically connected to the redistribution wiring structure through the connector.

In an embodiment of the present invention, the above-mentioned connection element includes a contact pad and a welding point. The contact pads can be connected to the rerouting structure. The soldering point is disposed on the contact pad, and the soldering point can be electrically connected to the contact pad.

The manufacturing method of the chip packaging structure of the present invention includes the following steps: firstly, a substrate is provided, wherein the substrate has a first surface, a second surface opposite to the first surface, and at least one groove. Next, disposing at least one first chip and adhesive material in at least one groove, so that the adhesive material is located between the substrate and the at least one first chip. Next, a redistribution circuit structure is formed on the first surface of the substrate to be electrically connected to at least one first chip. Then, a plurality of second chips are arranged on the redistribution circuit structure to be electrically connected to the redistribution circuit structure.

In an embodiment of the present invention, the above-mentioned method for forming a redistribution wiring structure on the first surface of the substrate includes the following steps: firstly, a first dielectric layer is formed on the first surface of the substrate by a planarization process. Next, form a first patterned circuit layer on the first dielectric layer and form a first via hole in the first dielectric layer, wherein the first via hole penetrates the first dielectric layer, and the first via hole The first patterned circuit layer is electrically connected to at least one first chip. Next, a second dielectric layer is formed on the first patterned circuit layer. Then, a second patterned circuit layer is formed on the second dielectric layer and a second via hole is formed in the second dielectric layer, wherein the second via hole penetrates the second dielectric layer and is electrically connected to the second dielectric layer. The patterned circuit layer and the first patterned circuit layer.

In an embodiment of the present invention, the manufacturing method of the above-mentioned chip package structure further includes the following step: forming a connecting piece on the redistribution wiring structure, so that the plurality of second chips are electrically connected to the redistribution wiring structure through the connecting piece.

Based on the above, in the chip packaging structure according to an embodiment of the present invention, the overall thickness is reduced by embedding the first chip in the substrate. Furthermore, since the first chip of this embodiment can be embedded in the substrate and is a bare crystal, it can avoid the problem of warping of the substrate due to the use of packaged chips, and can also maintain the rigidity and flatness of the substrate, thereby improving Product yield.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the present invention;

2A to 2D are schematic cross-sectional views of a manufacturing method of a chip packaging structure according to an embodiment of the present invention.

Explanation of reference signs

10: Chip packaging structure;

100: Substrate;

102: first surface;

104: second surface;

106a, 106b: grooves;

110a, 110b: the first chip;

112, 162: active surface;

114: back surface;

116: surrounding surface;

118, 130: pad;

120: adhesive material;

140: Redistribute the line structure;

141: the first dielectric layer;

142: the first patterned circuit layer;

143: a first via hole;

144: second dielectric layer;

145: the second patterned circuit layer;

146: a second via hole;

150: connector;

152: contact pad;

154: welding point;

160a, 160b, 160c, 160d: second chips;

S1, S2, S3, S4: steps.

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and description to refer to the same or like parts.

FIG. 1 is a flowchart of a manufacturing method of a chip packaging structure according to an embodiment of the present invention. 2A to 2D are schematic cross-sectional views of a manufacturing method of a chip packaging structure according to an embodiment of the present invention.

The manufacturing method of the chip packaging structure 10 of this embodiment may include the following steps:

First, please refer to FIG. 1 and FIG. 2A at the same time, and perform step S1: providing the substrate 100 . The substrate 100 has a first surface 102, a second surface 104 opposite to the first surface 102, and at least one groove 106a, 106b (two grooves are exemplarily shown in FIG. That is to say, the number of grooves can be adjusted according to requirements). In this embodiment, since the substrate 100 can be a rigid substrate, and the first surface 102 of the substrate 100 can have excellent flatness, it is helpful to fabricate fine lines in subsequent processes. Here, the substrate 100 may be, for example, a glass substrate, a ceramic substrate, a silicon substrate or other suitable substrates, but is not limited thereto.

In this embodiment, the grooves 106 a , 106 b are recessed from the first surface 102 of the substrate 100 toward the second surface 104 , and the grooves 106 a , 106 b do not penetrate through the substrate 100 . Viewed from the cross-sectional view, the grooves 106a, 106b may be ㄩ-shaped openings, but not limited thereto. In this embodiment, the grooves 106a, 106b may be formed by, for example, wet etching or other suitable processes.

Next, please refer to FIG. 1 and FIG. 2B at the same time, perform step S2: dispose at least one first chip 110a, 110b and the adhesive material 120 in at least one groove 106a, 106b, so that the adhesive material 120 is located between the substrate 100 and the at least one first chip Between a chip 110a, 110b. In this embodiment, each first chip 110a, 110b can be correspondingly disposed in each groove 106a, 106b. For example, as shown in FIG. 2B , the first chip 110a may be disposed in the groove 106a, and the first chip 110b may be disposed in the groove 106b. The first chip 110 a , 110 b has an active surface 112 , a back surface 114 opposite to the active surface 112 , and a surrounding surface 116 connecting the active surface 112 and the back surface 114 . The active surface 112 faces and is adjacent to the first surface 102 . In this embodiment, the active surface 112 of the first chip 110a, 110b may be flush with the first surface 102 of the substrate 100, but not limited thereto. The first chips 110a and 110b may be bare dies, and the functions of the first chip 110a and the first chip 110b may be the same or different. For example, in this embodiment, the first chip 110 a and the first chip 110 b may be, for example, a source driver IC (Source Drive IC), a gate driver IC (Gate Driver IC) or chips with other functions. In other embodiments, the first chip 110a may be, for example, a passive device, and the first chip 110b may be, for example, a surface mount device (SMD), which is not limited in the present invention.

The adhesive material 120 may be disposed in the gap between the substrate 100 and the bottom surface 114 of the first chip 110a, 110b, and may be disposed in the gap between the substrate 100 and the surrounding surface 116 of the first chip 110a, 110b, that is, The adhesive material 120 can cover the bottom surface 112 and the surrounding surface 116 of the first chips 110a, 110b, thereby helping to fix the first chips 110a, 110b in the grooves 106a, 106b. In this embodiment, the method of placing the first chips 110a, 110b in the grooves 106a, 106b may be, for example, first filling the adhesive material 120 into the grooves 106a, 106b, and then placing the first chips 110a, 110b . The adhesive material 120 can be, for example, resin, epoxy or other suitable materials, but is not limited thereto.

In this embodiment, by embedding the first chips 110 a and 110 b in the substrate 100 , the overall thickness of the chip packaging structure 10 (as shown in FIG. 2D ) in this embodiment is reduced. Furthermore, compared to the general chip packaging structure, the packaging chip with heterogeneous materials (ie, the encapsulation compound of the non-embedded chip packaging structure) is placed on the substrate to cause warpage of the substrate, due to the present embodiment The first chips 110a, 110b in the chip packaging structure 10 can be embedded in the substrate 100 and are bare crystals (that is, not packaged chips), so that the problem of warpage of the substrate 100 caused by the use of heterogeneous materials can be avoided, and the substrate 100 can also be warped. The rigidity and flatness of the substrate 100 are maintained, thereby improving the yield of products. In addition, since the substrate 100 has rigidity and excellent flatness, the problem of warpage of the substrate 100 can also be effectively reduced.

Next, referring to FIG. 1 and FIG. 2C , step S3 is performed: forming a redistribution wiring structure 140 on the first surface 102 of the substrate 100 to be electrically connected to at least one first chip 110a, 110b. In this embodiment, the step of forming the redistribution wiring structure 140 on the first surface 102 of the substrate 100 may include but not limited to the following steps:

Firstly, the pads 118 are formed on the active surface 112 of the first chip 110a, 110b, and the pads 130 are formed on the first surface 102 of the substrate 100 at the same time, wherein the connection pads 118 and the pads 130 can be regarded as patterned lines layer. Next, a first dielectric layer 141 is formed on the first surface 102 of the substrate 100 by a planarization process (such as a bonding process) to cover the first surface 102 of the substrate 100 and the active surfaces 112 of the first chips 110a, 110b . In this embodiment, the first dielectric layer 141 can be regarded as a planar layer. For example, in some embodiments, when the adhesive material 120 does not fill the gap between the substrate 100 and the first chips 110a, 110b, the first dielectric layer 141 can be used to fill the gap and provide A planarized surface facilitates subsequent formation of the patterned circuit layer 142 . The material of the first dielectric layer 141 can be, for example, a dielectric material with a leveling effect, such as Ajinomoto Build-up Film (ABF), polyimide (Polyimide) or other suitable materials, but not This is the limit. The thickness of the first dielectric layer 141 in this embodiment may be, for example, between 10 microns and 40 microns, but is not limited thereto. Specifically, the thickness of the first dielectric layer 141 needs to match the thickness of the patterned circuit layer (ie, the pads 118 , 130 ). Here, the thickness of the pads 118, 130 in this embodiment can be, for example, between 4 microns and 8 microns. Therefore, when the thickness of the first dielectric layer 141 is less than 10 microns, the manufacturing difficulty is high and the high-frequency impedance matching design less elastic. Furthermore, since the coefficient of thermal expansion (CTE) of the first dielectric material is large, when the thickness of the first dielectric layer 141 is greater than 40 microns, the warpage of the entire structure is likely to increase.

Next, a first patterned circuit layer 142 is formed on the first dielectric layer 141 and a first via hole 143 is formed in the first dielectric layer 141 . Specifically, the first via hole 143 can penetrate through the first dielectric layer 141 to electrically connect the first patterned circuit layer 142 and the pads 118 of the first chip 110a, 110b. Here, the material of the first patterned circuit layer 142 and the first via hole 143 can be, for example, copper or other conductive materials.

Next, a second dielectric layer 144 is formed on the first patterned circuit layer 142 . Wherein, the second dielectric layer 144 can be formed on the first patterned circuit layer 142 by, for example, a lamination process, a liquid coating process or other suitable processes, so as to cover the first dielectric layer 141, the first patterned circuit layer 142 and the first via hole 143. In this embodiment, the material of the second dielectric layer 144 can be, for example, a photosensitive dielectric material, a non-photosensitive dielectric material, or other suitable materials. In addition, the material of the second dielectric layer 144 can also be the same as or different from that of the first dielectric layer 141 , which is not limited in the present invention. The thickness of the first wiring layer in this embodiment may be, for example, between 2 microns and 6 microns, and the thickness of the second dielectric layer 144 may be, for example, less than 10 microns, but not limited thereto. When the thickness of the second dielectric layer 144 is less than 10 micrometers, the overall thickness can be made thinner and have lower residual stress, thereby reducing warpage.

Next, a second patterned circuit layer 145 is formed on the second dielectric layer 144 and a second via hole 146 is formed in the second dielectric layer 144 . Wherein, the second via hole 146 penetrates through the second dielectric layer 144 and electrically connects the second patterned circuit layer 145 and the first patterned circuit layer 142 . So far, the redistribution circuit structure 140 of this embodiment has been fabricated.

In this embodiment, the redistributed circuit structure 140 is exemplarily shown as a two-layer dielectric layer (first dielectric layer 141, second dielectric layer 144) and a three-layer patterned circuit layer (patterned circuit layer , the first patterned circuit layer 142, and the second patterned circuit layer 145), but the present invention is not limited thereto. In some embodiments, those skilled in the art can increase the number of stacked layers of the redistribution wiring structure 140 according to actual needs.

In addition, in this embodiment, since the substrate 100 has rigidity and excellent flatness, each circuit in the redistributed circuit structure 140 disposed on the substrate 100 (that is, the first patterned circuit layer 142, the second patterned circuit layer 142 The circuit layer 145 , the first via hole 143 , and the second via hole 146 ) can be fine lines.

Next, please refer to FIG. 1 and FIG. 2D at the same time, and perform step S4: disposing a plurality of second chips 160a, 160b, 160c, 160d on the redistribution circuit structure 140 to be electrically connected to the redistribution circuit structure 140 . In this embodiment, the step of configuring the second chip 160a, 160b, 160c, 160d on the redistribution circuit structure 140 may include but not limited to the following steps:

Firstly, the connecting element 150 is formed on the redistribution wiring structure 140 . In this embodiment, the connector 150 may include a contact pad 152 and a solder joint 154 , but it is not limited thereto. In other embodiments, the connector 150 may be, for example, a conductive post (not shown) or other suitable conductive connectors (not shown). Specifically, as shown in FIG. 2D, the contact pad 152 of this embodiment can be connected to the second patterned circuit layer 145 in the redistribution circuit structure 140, the soldering point 154 can be arranged on the contact pad 152, and the soldering point 154 It can be electrically connected to the contact pad 152 . Here, the material of the contact pad 152 can be, for example, copper or other suitable metal conductive materials, and the material of the solder joint 154 can be, for example, tin, silver, copper, gold or their alloys or other suitable metal conductive materials, but not This is the limit.

Next, a plurality of second chips 160 a , 160 b , 160 c , 160 d are disposed on the connector 150 , so that the plurality of second chips 160 a , 160 b , 160 c , 160 d can be electrically connected to the redistribution wiring structure 140 through the connector 150 . So far, the chip packaging structure 10 of this embodiment has been fabricated.

In this embodiment, the active surfaces 162 of the second chips 160 a , 160 b , 160 c , 160 d face the connectors 150 and are electrically connected to the corresponding connectors 150 . The second chip 160a, 160b, 160c, 160d may be a bare die and/or a packaged chip, and the present invention is not limited thereto. In addition, the functions of the second chip 160a, the second chip 160b, the second chip 160c, and the second chip 160d may be the same or different. For example, in this embodiment, the second chips 160a, 160b, 160c, and 160d may be, for example, miniature light-emitting diodes, or may be, for example, surface mount devices (Surface Mount Device, SMD), memory components, or chips with other functions. This is not limited.

In short, the chip packaging structure 10 of the present embodiment includes a substrate 100 , at least one first chip 110a, 110b, an adhesive material 120, a redistribution wiring structure 140, and a plurality of second chips 160a, 160b, 160c, 160d. The substrate 100 has a first surface 102, a second surface 104 opposite to the first surface 102, and at least one groove 106a, 106b. At least one first chip 110a, 110b is disposed in the groove 106a, 106b. The adhesive material 120 is disposed in at least one groove 106a, 106b, and is located between the substrate 100 and at least one first chip 110a, 110b. The redistribution wiring structure 140 is disposed on the first surface 102 of the substrate 100 and is electrically connected to at least one first chip 110a, 110b. A plurality of second chips 160 a , 160 b , 160 c , 160 d are disposed on the redistribution wiring structure 140 and are electrically connected to the redistribution wiring structure 140 .

To sum up, in the chip packaging structure of an embodiment of the present invention, the overall thickness of the chip packaging structure of this embodiment is reduced by embedding the first chip in the substrate. Furthermore, compared to the general chip packaging structure where the packaged chip with heterogeneous materials is placed on the substrate and causes the substrate to warp, since the first chip of this embodiment can be embedded in the substrate and is a bare crystal, therefore, It can avoid the problem of substrate warpage caused by the use of heterogeneous materials, and can also maintain the rigidity and flatness of the substrate, thus effectively reducing the possibility of assembly failure caused by substrate warpage, thereby improving product quality. Rate.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (12)

1. A chip package structure, comprising:

a substrate having a first surface, a second surface opposite to the first surface, and at least one groove;

at least one first chip arranged in the at least one groove;

the adhesive material is arranged in the at least one groove and is positioned between the substrate and the at least one first chip;

the redistribution circuit structure is arranged on the first surface of the substrate and is electrically connected to the at least one first chip; and

the second chips are arranged on the rerouting circuit structure and are electrically connected to the rerouting circuit structure.

2. The chip package structure according to claim 1, wherein the substrate is a glass substrate or a silicon substrate.

3. The chip package structure of claim 1, wherein the at least one first chip is a die.

4. The chip packaging structure according to claim 1, wherein the plurality of second chips comprises bare dies and/or packaged chips.

5. The chip package structure of claim 1, wherein the rerouting circuit structure comprises:

a first dielectric layer disposed on the first surface of the substrate;

the first patterning circuit layer is arranged on the first dielectric layer;

the first via hole penetrates through the first dielectric layer and is electrically connected with the first patterned circuit layer and the at least one first chip;

the second dielectric layer is arranged on the first patterned circuit layer;

the second patterning circuit layer is arranged on the second dielectric layer; and

the second via hole penetrates through the second dielectric layer and is electrically connected with the second patterned circuit layer and the first patterned circuit layer.

6. The chip package structure of claim 1, wherein the at least one first chip has an active surface, a back surface opposite to the active surface, and a pad disposed on the active surface, and the at least one first chip is electrically connected to the redistribution circuit structure through the pad.

7. The chip package structure of claim 6, wherein the active surface of the at least one first chip is flush with the first surface of the substrate.

8. The chip package structure according to claim 1, further comprising:

the connecting piece is arranged on the rerouting circuit structure, and the plurality of second chips are electrically connected to the rerouting circuit structure through the connecting piece.

9. The chip package structure of claim 8, wherein the connection member comprises:

a contact pad connecting the rerouting circuit structure; and

and the welding point is arranged on the contact pad and is electrically connected to the contact pad.

10. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:

providing a substrate, wherein the substrate is provided with a first surface, a second surface opposite to the first surface and at least one groove;

disposing at least one first chip and an adhesive material in the at least one recess such that the adhesive material is located between the substrate and the at least one first chip;

forming a redistribution circuit structure on the first surface of the substrate to be electrically connected to the at least one first chip; and

and configuring a plurality of second chips on the rerouting circuit structure to be electrically connected to the rerouting circuit structure.

11. The method of claim 10, wherein forming the redistribution structure on the first surface of the substrate comprises:

forming a first dielectric layer on the first surface of the substrate by a planarization process;

forming a first patterned circuit layer on the first dielectric layer and forming a first via hole in the first dielectric layer, wherein the first via hole penetrates through the first dielectric layer and is electrically connected with the first patterned circuit layer and the at least one first chip;

forming a second dielectric layer on the first patterned circuit layer; and

forming a second patterned circuit layer on the second dielectric layer and forming a second via hole in the second dielectric layer, wherein the second via hole penetrates through the second dielectric layer and is electrically connected with the second patterned circuit layer and the first patterned circuit layer.

12. The method of manufacturing a chip package structure according to claim 10, further comprising:

and forming a connecting piece on the rerouting circuit structure so that the plurality of second chips are electrically connected to the rerouting circuit structure through the connecting piece.

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