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CN116130355A - 干法刻蚀制作正梯形胶形的工艺 - Google Patents

干法刻蚀制作正梯形胶形的工艺 Download PDF

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CN116130355A
CN116130355A CN202310056716.2A CN202310056716A CN116130355A CN 116130355 A CN116130355 A CN 116130355A CN 202310056716 A CN202310056716 A CN 202310056716A CN 116130355 A CN116130355 A CN 116130355A
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dry etching
glue
trapezoid
photoresist
photosensitive
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陈银培
刘耀菊
宁珈祺
吴超
杨巨椽
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Hangzhou Meidikai Microelectronics Co ltd
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Hangzhou Meidikai Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

本发明公开了一种干法刻蚀制作正梯形胶形的工艺，其工艺步骤为：S1、取出基板，在基板上涂覆一层非光敏底层胶达到设定的目标厚度；S2、在非光敏底层胶上层再涂覆一层光刻胶，光刻胶的厚度大于非光敏底层胶；S3、两层胶涂覆完毕后采用曝光显影坚膜的方式把上层的光刻胶做成具有正梯形或者倒梯形槽口的胶形，并裸露出需要去除的非光敏底层胶；S4、采用干法刻蚀的工艺对上层的光刻胶胶和裸露出来的非光敏底层胶一起进行干刻；S5、干刻后，通过去胶液将非光敏底层胶上层残留的光刻胶去除，最终得到正梯形或者倒梯形胶形的产品，完成干法刻蚀制作正梯形胶形的工艺。本发明实现了胶形为正梯形或者倒梯形且斜面角度小于等于45°的图形化加工。

Description

干法刻蚀制作正梯形胶形的工艺
技术领域
本发明涉及半导体干法刻蚀工艺领域，尤其涉及一种干法刻蚀制作正梯形胶形的工艺。
背景技术
目前半导体行业在快速发展，市场对于半导体器件的需求也越来越大，半导体的形式也越来越多样化。其中一部分部件就涉及到在硅基板上涂覆非光敏胶的半导体器件。其要求在半导体器件上涂覆非光敏胶的胶形为正梯形且斜面角度要求为45°，而一般的黄光工艺无法加工非光敏胶的胶形，而单独使用干法刻蚀的工艺虽然能够进行图形化加工但是干刻后的胶形一般为长方形或者斜面角度接近90°。为了解决该问题本申请发明了一种干法刻蚀结合黄光工艺的方法在进行非光敏胶图形化加工的同时还能使胶的胶形为正梯形。
发明内容
为解决上述技术问题，本发明设计了一种干法刻蚀制作正梯形胶形的工艺，使最终形成的胶形为正梯形或者倒梯形且斜面角度实现小于等于45°。
本发明采用如下技术方案：
一种干法刻蚀制作正梯形胶形的工艺，其工艺步骤为：
S1、取出基板，在基板上涂覆一层非光敏底层胶达到设定的目标厚度；
S2、在非光敏底层胶上层再涂覆一层光刻胶，光刻胶的厚度大于非光敏底层胶；
S3、两层胶涂覆完毕后采用曝光显影坚膜的方式把上层的光刻胶做成具有正梯形或者倒梯形槽口的胶形，并裸露出需要去除的非光敏底层胶；
S4、采用干法刻蚀的工艺对上层的光刻胶胶和裸露出来的非光敏底层胶一起进行干刻；
S5、干刻后，通过去胶液将非光敏底层胶上层残留的光刻胶去除，最终得到正梯形或者倒梯形胶形的产品，完成干法刻蚀制作正梯形胶形的工艺。
作为优选，步骤S4中，调整干法刻蚀的参数，使上层干刻胶的干刻速率与非光敏底层胶的干刻速率一致。
作为优选，所述正梯形或者倒梯形槽口的斜面角度小于等于45°。
作为优选，所述非光敏底层胶通过旋涂的方式均匀涂覆在基板上。
作为优选，所述光刻胶通过旋涂的方式均匀涂覆在非光敏底层胶上。
本发明的有益效果是：本发明结合了干法刻蚀及涂胶曝光显影工艺，使得胶形加工更加多样化，拓展了干刻机的使用领域，实现了胶形为正梯形或者倒梯形且斜面角度小于等于45°的图形化加工。
附图说明
图1是本发明中基板的一种结构示意图；
图2是本发明基板上涂上一层非光敏底层胶的一种结构示意图；
图3是图2上的非光敏底层胶涂上一层光刻胶并曝光显影坚膜后的一种结构示意图；
图4是图3中对上层光刻胶和裸露出来的非光敏底层胶一起干法蚀刻后的一种结构示意图；
图5是图4中干法蚀刻后将上层光刻胶去除的一种结构示意图；
图中：1、基板，2、非光敏底层胶，3、光刻胶。
实施方式
下面通过具体实施例，并结合附图，对本发明的技术方案作进一步的具体描述：
实施例：一种干法刻蚀制作正梯形胶形的工艺，其工艺步骤为：
S1、如图1所示，取出基板1，在基板上涂覆一层非光敏底层胶2达到设定的目标厚度，如图2所示；
S2、在非光敏底层胶上层再涂覆一层光刻胶3，光刻胶的厚度大于非光敏底层胶；
S3、两层胶涂覆完毕后采用曝光显影坚膜的方式把上层的光刻胶做成具有正梯形槽口的胶形，并裸露出需要去除的非光敏底层胶，如图3所示；
S4、采用干法刻蚀的工艺对上层的光刻胶胶和裸露出来的非光敏底层胶一起进行干刻，如图4所示；
S5、干刻后，通过去胶液将非光敏底层胶上层残留的光刻胶去除，最终得到正梯形胶形的产品，如图5所示，完成干法刻蚀制作正梯形胶形的工艺,。
步骤S4中，调整干法刻蚀的参数，使上层干刻胶的干刻速率与非光敏底层胶的干刻速率一致。
正梯形槽口的斜面角度小于等于45°。非光敏底层胶通过旋涂的方式均匀涂覆在基板上。光刻胶通过旋涂的方式均匀涂覆在非光敏底层胶上。
本发明结合了干法刻蚀及涂胶曝光显影工艺，使得胶形加工更加多样化，拓展了干刻机的使用领域，实现了胶形为正梯形或者倒梯形且斜面角度小于等于45°的图形化加工。
以上所述的实施例只是本发明的一种较佳的方案，并非对本发明作任何形式上的限制，在不超出权利要求所记载的技术方案的前提下还有其它的变体及改型。

Claims (5)

1.一种干法刻蚀制作正梯形胶形的工艺，其特征是，其工艺步骤为：
S1、取出基板，在基板上涂覆一层非光敏底层胶达到设定的目标厚度；
S2、在非光敏底层胶上层再涂覆一层光刻胶，光刻胶的厚度大于非光敏底层胶；
S3、两层胶涂覆完毕后采用曝光显影坚膜的方式把上层的光刻胶做成具有正梯形或者倒梯形槽口的胶形，并裸露出需要去除的非光敏底层胶；
S4、采用干法刻蚀的工艺对上层的光刻胶胶和裸露出来的非光敏底层胶一起进行干刻；
S5、干刻后，通过去胶液将非光敏底层胶上层残留的光刻胶去除，最终得到正梯形或者倒梯形胶形的产品，完成干法刻蚀制作正梯形胶形的工艺。
2.根据权利要求1所述的一种干法刻蚀制作正梯形胶形的工艺，其特征是，步骤S4中，调整干法刻蚀的参数，使上层干刻胶的干刻速率与非光敏底层胶的干刻速率一致。
3.根据权利要求1所述的一种干法刻蚀制作正梯形胶形的工艺，其特征是，所述正梯形或者倒梯形槽口的斜面角度小于等于45°。
4.根据权利要求1所述的一种干法刻蚀制作正梯形胶形的工艺，其特征是，所述非光敏底层胶通过旋涂的方式均匀涂覆在基板上。
5.根据权利要求1所述的一种干法刻蚀制作正梯形胶形的工艺，其特征是，所述光刻胶通过旋涂的方式均匀涂覆在非光敏底层胶上。
CN202310056716.2A 2023-01-16 2023-01-16 干法刻蚀制作正梯形胶形的工艺 Pending CN116130355A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118983274A (zh) * 2024-10-17 2024-11-19 杭州合盛微电子有限公司 半导体器件接触孔的制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118983274A (zh) * 2024-10-17 2024-11-19 杭州合盛微电子有限公司 半导体器件接触孔的制备方法

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