CN116110945A - A kind of TSS semiconductor discharge tube and preparation method thereof - Google Patents

Abstract

The invention discloses a TSS semiconductor discharge tube and a preparation method thereof, and relates to the technical field of semiconductor electronic devices. The TSS semiconductor discharge tube includes an N-type silicon chip, and two sides of the N-type silicon chip are respectively provided with P ⁺ regions. And P ^# area and P ^‑ area, the P ^# area is set between the P ⁺ area and the P ^‑ area, the depth of the P ⁺ area is greater than the depth of the P ^# area, and the P ^# The depth of the region is greater than the depth of the P ^- region; the P ^# region is photoetched with some N ⁺ regions on the side far away from the N-type silicon wafer, and the P ^# region is located on the side far away from the N-type silicon wafer. A metal layer is provided on one side, and protective layers are respectively provided on both sides of the metal layer. The invention can effectively improve the surge capacity of the TSS semiconductor discharge tube and reduce residual voltage and capacitance.

Description

A kind of TSS semiconductor discharge tube and preparation method thereof

technical field

The invention relates to the technical field of semiconductor electronic devices, in particular to a TSS semiconductor discharge tube and a preparation method thereof.

Background technique

The semiconductor discharge tube is an overvoltage protection component used at the input end of the equipment. It is made based on the principle of the thyristor. The breakdown current of the PN junction triggers the device to conduct and discharge, so that a large surge current or pulse current can pass through it. . The range of the breakdown voltage of the semiconductor discharge tube forms the range of overvoltage protection. It is widely used in information transmission equipment or systems such as communication terminals, modems, and distribution frames.

When the TSS semiconductor discharge tube is turned on, a large residual voltage (overshoot voltage) will be generated. The higher the residual voltage, the easier it is for the device to burn out and fail, that is, the anti-surge capability of the device will decrease. On the contrary, the higher the residual voltage The lower the surge resistance of the device, the stronger the anti-surge capability of the device; another important parameter of the protective device is capacitance, which is an important parameter that determines the signal transmission frequency. Lower capacitance is more suitable for high-frequency applications, so how to reduce residual Voltage and capacitance reduction are also the focus of various studies. The conventional method is to reduce the residual voltage by directly reducing the resistivity of the substrate material, but at the cost of increasing the capacitance. Similarly, the way to reduce capacitance is to increase the resistivity of the substrate. , but will increase the residual voltage, none of these methods can meet the needs of customers. How to ensure high surge capacity, low residual voltage, and low capacitance has always been the research direction of technicians.

Contents of the invention

Aiming at the deficiencies of the prior art, the object of the present invention is to provide a TSS semiconductor discharge tube and a preparation method thereof, aiming at improving the surge capability of the TSS semiconductor discharge tube and reducing residual voltage and capacitance.

One aspect of the present invention is to provide a TSS semiconductor discharge tube, including an N-type silicon chip, the two sides of the N-type silicon chip are respectively provided with a P ⁺ region, a P# region and ^{a P- region} , and the P ^# region Located between the P ⁺ area and the P ^- area, the depth of the P ⁺ area is greater than the depth of the P ^# area, and the depth of the P ^# area is greater than the depth of the P ^- area;

The P ^# area is photoetched with several N ⁺ areas on the side far away from the N-type silicon chip, and the P ^# area is provided with a metal layer on the side far away from the N-type silicon chip, and the metal layer Protective layers are provided on both sides.

Compared with the prior art, the beneficial effect of the present invention is that: the TSS semiconductor discharge tube provided by the present invention can effectively reduce the capacitance and increase the surge capacity, specifically, the TSS semiconductor discharge tube includes an N-type silicon chip , the two sides of the N-type silicon wafer are respectively provided with a P ⁺ area, a P ^# area and a P ^- area, and the P ^# area is arranged between the P ⁺ area and the P ^- area, and the P ⁺ area The depth of the P ^# area is greater than the depth of the P # area, and the depth of the P ^# area is greater than the depth of the P ^- area; the P ^# area is photoetched with several N ⁺ areas on the side away from the N-type silicon wafer , the P ^# area is provided with a metal layer on the side away from the N-type silicon chip, and the two sides of the metal layer are respectively provided with protective layers, and the P ⁺ area, the P ^# area and the N ⁺ area and the N-type The silicon wafer forms a PN junction, with a concave-convex-convex-convex-convex-convex-convex-convex-convex-convex structure. By optimizing the structure, a breakdown is formed locally, so that the TSS semiconductor discharge tube has extremely low capacitance, good reliability, and stronger surge capability. The setting of the P ^- region It will reduce the generation of leakage current, improve the IPP flow capacity of the semiconductor discharge tube, thereby improving the surge capacity of the TSS semiconductor discharge tube, and reducing the residual voltage and capacitance.

According to one aspect of the above technical solution, the N-type silicon chip includes a first N-type portion and a second N-type portion connected to the first N-type portion, and the two sides of the first N-type portion are arranged side by side. There are the P ⁺ area, the P ^# area and the P ^- area, and the second N-type part is provided on the side of the P ⁺ area away from the P ^# area.

According to one aspect of the above technical solution, the protection layer includes a first protection sublayer and a second protection sublayer, the first protection sublayer is disposed on the P ^- region, and the second protection sublayer is disposed on on the second N-type portion.

According to one aspect of the above technical solution, the junction depth of the P ⁺ region is 50-70 μm, the junction depth of the P ^# region is 15-40 μm, the diameter of the N ⁺ region is 8-12 μm, and the P ^- The junction depth of the region is 20-30 μm.

Another aspect of the present invention is to provide a kind of preparation method of TSS semiconductor discharge tube, described preparation method is used for preparing the TSS semiconductor discharge tube described in any one of above-mentioned, and described preparation method comprises:

Select N-type silicon wafer;

growing oxide layers on both sides of the N-type silicon wafer;

On both sides of the N-type silicon chip, photoetching the P ⁺ well area, performing boron pre-diffusion and boron re-diffusion distribution on the P ⁺ well area, forming a P ^# area and a P ⁺ area;

On both sides of the N-type silicon chip, photoetching the P ^- well region, performing boron pre-diffusion and boron re-diffusion distribution on the P ^- well region to form a P ^- region;

Photoetching an N ⁺ well region on the side of the P ⁺ region away from the N-type silicon wafer, performing phosphorus pre-diffusion and phosphorus re-diffusion distribution on the N ⁺ well region, to form an N ⁺ region;

Depositing protective layers on both sides of the N-type silicon wafer;

Metal deposition, photolithography, etching, electrodes are formed in the protective layer gap, and metal layers are formed on both sides of the N-type silicon wafer;

alloy.

According to one aspect of the above-mentioned technical solution, the step of performing boron pre-diffusion and boron re-diffusion distribution on the P ^- well region to form a P ^- region specifically includes:

The surface of the P ^- well area is evenly coated with a boron source and nitrogen and oxygen are introduced, the pre-diffusion temperature is 1000-1250°C, and the time is 2-30h; the re-diffusion temperature is 1100-1275°C, and the time is 5-10h, Form a P ^- region with a junction depth of 20-30 µm.

According to one aspect of the above-mentioned technical solution, the step of performing boron pre-diffusion and boron re-diffusion distribution on the P ⁺ well region to form a P ^# region and a P ⁺ region specifically includes:

Uniformly coat the boron source on the surface of the P ⁺ well region and pass nitrogen and oxygen gas, the pre-diffusion temperature is 1000-1250°C, the time is 2-30h; the re-diffusion temperature is 1200-1275°C, the time is 9-120h, Form a P ⁺ region with a junction depth of 50-70 μm.

According to one aspect of the above technical solution, the surface of P ^# area is evenly coated with boron source and nitrogen and oxygen are introduced, the boron pre-diffusion temperature is 1000-1250°C, time 2-30h; re-diffusion temperature is 1200-1275°C, time For 9-120h, a P ^# area with a junction depth of 15-40μm is formed.

According to one aspect of the above technical solution, POCl ₃ is introduced into the N ⁺ well region, the pre-diffusion temperature is 1000-1100°C, and the time is 1-2h; the re-diffusion temperature is 1100-1250°C, and the time is 1-6h, N ⁺ region is formed.

According to one aspect of the above technical solution, the synthesis temperature of the alloy is 400-530° C., the synthesis time is 10-30 min, and the vacuum degree is 5×10 ^-4 -5×10 ^-3 Pa.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, wherein:

Fig. 1 is the structural representation of the TSS semiconductor discharge tube in the first embodiment of the present invention;

Fig. 2 is the flow chart of the preparation method of the TSS semiconductor discharge tube in the second embodiment of the present invention;

Explanation of symbols of attached parts and components:

N-type silicon wafer 100, first N-type portion 101, second N-type portion 102, P ⁺ region 200, P ^# region 300, P ^- region 400, N ⁺ region 500, protective layer 600, first protective sublayer 601 , the second protective sublayer 602 , and the metal layer 700 .

Detailed ways

In order to make the purpose, features and advantages of the present invention more obvious and understandable, the specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings. Several embodiments of the invention are shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

It should be noted that when an element is referred to as being “fixed on” another element, it may be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical", "horizontal", "left", "right", "upper", "lower" and similar expressions are for the purpose of description only and do not indicate or imply the device or Elements must have certain orientations, be constructed and operate in certain orientations, and therefore should not be construed as limitations on the invention.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Please refer to Fig. 1, it is shown that a kind of TSS semiconductor discharge tube provided by the present invention, this TSS semiconductor discharge tube comprises N-type silicon chip 100; Wherein, the material of making N-type silicon chip 100 can be semiconductor material SOI, silicon carbide, Materials such as gallium nitride, gallium arsenide, indium phosphide, and silicon germanium, the thickness of the N-type silicon wafer 100 is 150-300 μm, and the resistivity is 0.009-0.012 Ω·cm. The N-type silicon wafer 100 has high minority carrier lifetime, good low-light performance, high tolerance to metal impurities, and the formed PN junction structure has excellent performance.

The two sides of the N-type silicon wafer 100 are respectively provided with P ⁺ district 200, P ^# district 300 and P ^- district 400, and the P ^# district 300 is arranged between the P ⁺ district 200 and the P ^- district 400, and the P ⁺ district 200 The depth is greater than the depth of the P ^# region 300, and the depth of the P ^# region 300 is greater than the depth of the P ^- region 400.

Further, the N-type silicon wafer 100 includes a first N-type portion 101 and a second N-type portion 102 connected to the first N-type portion 101, and the two sides of the first N-type portion 101 are respectively provided with a P ⁺ region 200 and a In the P ^# region 300 and the P ⁻ region 400 , the second N-type portion 102 is located on the side of the P ⁺ region 200 away from the P ^# region 300 .

Among them, the P ⁺ region 200, the P ^# region 300 and the P ^- region 400 are all doped with a certain amount of impurities into the N-type silicon wafer 100 through boron pre-expansion and boron re-expansion to form the P ⁺ region 200 and the P ^# region 300 and P ^- zone 400. It should be noted that the current relatively common impurity doping method is ion implantation, that is, the impurity is ionized into ions and focused into an ion beam, which is accelerated in an electric field to obtain extremely high kinetic energy and implanted into the silicon wafer for doping. Usually, ion implantation The required energy E>50KeV, but ion implantation will cause a large number of defects such as vacancies and interstitial atoms, as well as composite defects formed by the combination of vacancies and other impurities; and this embodiment adopts the diffusion method for impurity doping, which can effectively reduce vacancies and defects, and the diffusion process can obtain a deep junction depth, stronger surge withstand capability, and the formed chip has a fast response speed, strong surge capability, and high reliability. In addition, the diffusion process has a short cycle, is easy to package, and can effectively Minimize the impact of packaging on chip output stress.

Further, the P ⁺ region 200 is a deep boron region, and the junction depth of the P ⁺ region 200 is 50-70 μm. The deeper the junction depth, the stronger the resistance to packaging stress.

Further, the P ^# region 300 is a light boron region, which is used to adjust the voltage of the semiconductor discharge tube, and the junction depth of the P ^# region 300 is 15-40 μm.

Further, the P ^- region 400 is a barrier layer, preventing current from leaking from the P ^- region 400, reducing leakage current generation, and improving the IPP flow capacity of the semiconductor discharge tube. The junction depth of the P ^- region 400 is 20-30 μm.

In addition, the P ^# region 300 is photoetched with a number of N ⁺ regions 500 on the side far away from the N-type silicon wafer 100, and the P ^# region 300 is provided with a metal layer 700 on the side far away from the N-type silicon wafer 100, and the metal layer 700 Protective layers 600 are provided on both sides respectively. The protective layer 600 includes a first protective sublayer 601 and a second protective sublayer 602 , the first protective sublayer 601 is disposed on the P ⁻ region 400 , and the second protective sublayer 602 is disposed on the second N-type portion 102 .

Wherein, the N ⁺ region 500 is a breakdown region, and the N ⁺ region 500 is formed by phosphorus pre-expansion and phosphorus re-expansion, and is used to adjust the current effect of the semiconductor discharge tube. The diameter of the N ⁺ region 500 is 8-12 μm.

Both sides of the N-type silicon wafer 100 are provided with an N ⁺ region 500, a P ⁺ region 200, and a P ^# region 300, and the P ⁺ region 200, the P ^# region 300, and the N ⁺ region 500 form a PN junction with the N-type silicon wafer 100. Concave-convex structure. In addition, a flat interface is formed above the N ⁺ region 500, the P ⁺ region 200, the P ^# region 300, the P ⁻ region 400 and the second N-type portion 102, so as to facilitate the attachment and deposition of the subsequent protective layer 600 and metal layer 700 , improve the density and flatness of the follow-up protective layer 600 and the metal layer 700, prevent the generation of defects, and the flat interface can effectively prevent the metal powder from falling off under vibration, improve the stability and reliability of the device, and avoid P ^-The region forms a groove shape, and the protective layer 600 or metal layer 700 deposited in the groove has poor stability and flatness, resulting in the peeling off of the protective layer 600 or metal layer 700 and poor device stability.

Further, the protective layer 600 is silicon dioxide with a thickness of 20000-25000Å, and the protective layer 600 is used to protect the PN junction, because the N ⁺ region 500, the P ⁺ region 200, the P ^# region 300, the P ^- region 400 and the second N A flat interface is formed above the molding portion 102 , and the interface is easily covered with a protective layer 600 by thermal oxidation to protect the PN junction and improve the stability and reliability of the device.

Further, the metal layer 700 is a titanium-nickel-silver alloy with a thickness of 8000-15000 Å, and the metal layer 700 is used to improve reliability and surge capability as well as welding between the chip and the package.

In addition, please refer to Fig. 2, which shows a preparation method of a TSS semiconductor discharge tube provided by the present invention, the preparation method includes steps S10-S17:

Step S10, selecting an N-type silicon wafer;

Among them, the material for making the N-type silicon wafer can be semiconductor materials such as SOI, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, and silicon germanium. The thickness of the N-type silicon wafer is 150-300 μm, and the resistivity is 0.009 -0.012Ω·cm. N-type silicon wafers have high minority carrier lifetime, good low-light performance, high tolerance to metal impurities, and excellent performance of the formed PN junction structure.

The N-type silicon chip includes a first N-type portion and a second N-type portion connected to the first N-type portion, and the two sides of the first N-type portion are respectively provided with the P ⁺ region and the The P ^# area and the P ^- area, the second N-type part is provided on the side of the P ⁺ area away from the P ^# area.

Step S11, growing oxide layers on both sides of the N-type silicon wafer;

Step S12, photoetching the P ⁺ well area on both sides of the N-type silicon wafer, performing boron pre-diffusion and boron re-diffusion distribution on the P ⁺ well area to form a P ^# area and a P ⁺ area;

Wherein, the step of performing boron pre-diffusion and boron re-diffusion distribution on the P ⁺ well region to form a P ^# region and a P ⁺ region specifically includes:

Uniformly coat the boron source on the surface of the P ⁺ well region and pass nitrogen and oxygen gas, the pre-diffusion temperature is 1000-1250°C, the time is 2-30h; the re-diffusion temperature is 1200-1275°C, the time is 9-120h, Form a P ⁺ region with a junction depth of 50-70 μm.

Coat the boron source uniformly on the surface of P ^# area and pass nitrogen and oxygen gas, boron pre-diffusion temperature is 1000-1250℃, time is 2-30h; re-diffusion temperature is 1200-1275℃, time is 9-120h, forming deep junction P ^# area for 15-40μm.

Further, the P ⁺ region is a deep boron region, and the junction depth of the P ⁺ region is 50-70 μm, and the deeper the junction depth, the stronger the resistance to packaging stress.

Further, the P ^# area is a light boron area, which is used to adjust the voltage of the semiconductor discharge tube, and the junction depth of the P ^# area is 15-40 μm.

Step S13, photoetching P ^- well regions on both sides of the N-type silicon wafer, performing boron pre-diffusion and boron re-diffusion distribution on the P ^- well regions to form P ^- regions;

Specifically, a boron source is evenly coated on the surface of the P ^- well region and nitrogen and oxygen are introduced, the pre-diffusion temperature is 1000-1250°C, and the time is 2-30h; the re-diffusion temperature is 1100-1275°C, and the time is 5 hours. -10h, forming a P ^- region with a junction depth of 20-30μm.

The P ^- region is a barrier layer, which prevents current from leaking from the P ^- region, reduces leakage current generation, and improves the IPP flow capacity of the semiconductor discharge tube. The junction depth of the P ^- region is 20-30 μm.

In addition, the P ⁺ area, P ^# area and P ^- area are all doped with a certain amount of impurities into the N-type silicon wafer through boron pre-expansion and boron re-expansion to form the P ⁺ area, P ^# area and P ^- area. It should be noted that the current relatively common impurity doping method is ion implantation, that is, the impurity is ionized into ions and focused into an ion beam, which is accelerated in an electric field to obtain extremely high kinetic energy and implanted into the silicon wafer for doping. Usually, ion implantation The required energy E>50KeV, but ion implantation will cause a large number of defects such as vacancies and interstitial atoms, as well as composite defects formed by the combination of vacancies and other impurities; and the present invention adopts a diffusion method for impurity doping, which can effectively reduce vacancies and interstitial atoms. Defects, and the diffusion process can obtain a deep junction depth, stronger surge withstand capability, the formed chip has a fast response speed, strong surge capability, and high reliability. In addition, the diffusion process has a short cycle and is easy to package, which can effectively Reduce the impact of packaging on chip output stress.

At the same time, the temperature of pre ^- diffusion and re-diffusion in P-area is less than or equal to the temperature of pre-diffusion and re-diffusion in P ^# area, and the temperature of pre-diffusion and re-diffusion in P ^# area is less than or equal to the pre-diffusion and re-diffusion in P ⁺ area. The temperature of diffusion will improve the surge capability of the device, avoiding that the temperature of pre-diffusion and re-diffusion in the latter step is higher than the temperature of pre-diffusion and re-diffusion in the previous step, causing the boron doping concentration in the previous step to change again through high temperature. As a result, the distribution of boron doping concentration is uneven, resulting in a decrease in the surge capability of the device.

Step S14, photoetching an N ⁺ well region on the side of the P ⁺ region far away from the N-type silicon wafer, and performing phosphorus pre-diffusion and phosphorus re-diffusion distribution on the N ⁺ well region to form an N ⁺ region;

Specifically, POCl ₃ is introduced into the N ⁺ well region, the pre-diffusion temperature is 1000-1100°C, and the time is 1-2h; the re-diffusion temperature is 1100-1250°C, and the time is 1-6h, to form the N ⁺ region.

The N ⁺ region is the breakdown region. The N ⁺ region is formed by phosphorus pre-expansion and phosphorus re-expansion, and is used to adjust the current action of the semiconductor discharge tube. The diameter of the N ⁺ region is 8-12 μm.

Step S15, depositing protective layers on both sides of the N-type silicon wafer;

Wherein, the protective layer is silicon dioxide with a thickness of 20000-25000Å, and the protective layer is used to protect the PN junction.

Step S16, metal deposition, photolithography, etching, electrodes are formed in the protective layer gap, and metal layers are formed on both sides of the N-type silicon wafer;

Step S17, alloy.

The synthesis temperature of the alloy is 400-530°C, the synthesis time is 10-30min, the degree of vacuum is 5×10 ^-4 -5×10 ^-3 Pa, the metal layer is a titanium-nickel-silver alloy, and the thickness is 8000-15000Å , the metal layer is used to improve reliability and surge capability, as well as soldering between the chip and the package.

Further illustrate the present invention with specific embodiment below:

Example 1

The first embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube includes an N-type silicon chip; the N-type silicon chip has a thickness of 200 μm and a resistivity of 0.009-0.012 Ω·cm.

The two sides of the N-type silicon wafer are respectively provided with a P ⁺ area, a P ^# area and a P ^- area, and the P ^# area is arranged between the P ⁺ area and the P ^- area, and the depth of the P ⁺ area is greater than the depth of the P ^# area. The depth of the P ^# area is greater than the depth of the ^P- area.

Further, the N-type silicon wafer includes a first N-type portion and a second N-type portion connected to the first N-type portion, and the two sides of the first N-type portion are respectively provided with a P ⁺ region, a P ^# region and a P ⁻ region, the second N-type portion is located on the side of the P ⁺ region away from the P ^# region.

In this embodiment, the junction depth of the P ⁺ region is 60 μm, the junction depth of the P ^# region is 30 μm, and the junction depth of the P ⁻ region is 25 μm.

In addition, the P ^# area is photoetched with several N ⁺ areas on the side away from the N-type silicon wafer, and the P ^# area is provided with a metal layer on the side away from the N-type silicon wafer, and the two sides of the metal layer are respectively provided with protective layers. . The protective layer includes a first protective sublayer and a second protective sublayer, the first protective sublayer is arranged on the P ^- region, and the second protective sublayer is arranged on the second N-type portion.

In this embodiment, the N ⁺ region has a diameter of 10 μm, the protective layer is silicon dioxide with a thickness of 22000 Å, and the metal layer is a titanium-nickel-silver alloy with a thickness of 11000 Å.

The preparation method of TSS semiconductor discharge tube comprises the following steps in the present embodiment:

Step S10, selecting an N-type silicon wafer;

Step S11, growing oxide layers on both sides of the N-type silicon wafer;

Step S12, photoetching the P ⁺ well area on both sides of the N-type silicon wafer, performing boron pre-diffusion and boron re-diffusion distribution on the P ⁺ well area to form a P ^# area and a P ⁺ area;

Wherein, a boron source is evenly coated on the surface of the P ⁺ well area and nitrogen and oxygen are passed through, the pre-diffusion temperature is 1150°C, and the time is 4h; the re-diffusion temperature is 1260°C, and the time is 10h, forming a P ⁺ area.

Coat the boron source evenly on the surface of the P ^# area and pass nitrogen and oxygen. The boron pre-diffusion temperature is 1100°C for 3h; the re-diffusion temperature is 1230°C for 20h to form the P ^# area.

Step S13, photoetching P ^- well regions on both sides of the N-type silicon wafer, performing boron pre-diffusion and boron re-diffusion distribution on the P ^- well regions to form P ^- regions;

Specifically, a boron source is uniformly coated on the surface of the P ^- well region and nitrogen and oxygen are introduced, the pre-diffusion temperature is 1040°C, and the time is 2h; the re-diffusion temperature is 1230°C, and the time is 5h, to form a P ^- region.

Step S14, photoetching an N ⁺ well region on the side of the P ⁺ region far away from the N-type silicon wafer, and performing phosphorus pre-diffusion and phosphorus re-diffusion distribution on the N ⁺ well region to form an N ⁺ region;

Specifically, POCl ₃ is introduced into the N ⁺ well region, the pre-diffusion temperature is 1045°C, and the time is 1.5h; the re-diffusion temperature is 1150°C, and the time is 2.5h, to form the N ⁺ region.

Step S15, depositing protective layers on both sides of the N-type silicon wafer;

Step S16, metal deposition, photolithography, etching, electrodes are formed in the protective layer gap, and metal layers are formed on both sides of the N-type silicon wafer;

Step S17, alloy.

The synthesis temperature of the alloy is 510° C., the synthesis time is 30 min, and the vacuum degree is 10 ⁻³ Pa.

Example 2

A TSS semiconductor discharge tube provided in the second embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The junction depth of the P ⁺ region is 50 μm.

Example 3

A TSS semiconductor discharge tube provided in the third embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The junction depth of the P ⁺ region is 70 μm.

Example 4

A TSS semiconductor discharge tube provided by the fourth embodiment of the present invention, the difference between the TSS semiconductor discharge tube in this embodiment and the TSS semiconductor discharge tube in the first embodiment is:

The junction depth of the P ^- region is 20µm.

Example 5

A TSS semiconductor discharge tube provided in the fifth embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The junction depth of the P ^- region is 30µm.

Example 6

A TSS semiconductor discharge tube provided in the sixth embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The junction depth of the P ^# region is 15 μm.

Example 7

The seventh embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The junction depth of the P ^# region is 25μm.

Example 8

The eighth embodiment of the present invention provides a TSS semiconductor discharge tube. The difference between the TSS semiconductor discharge tube in this embodiment and the TSS semiconductor discharge tube in the first embodiment is:

The junction depth of the P ^# region is 40μm.

Example 9

A TSS semiconductor discharge tube provided by the ninth embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The diameter of the N ⁺ region is 8 μm.

Example 10

The tenth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The diameter of the N ⁺ region is 12 μm.

Example 11

The eleventh embodiment of the present invention provides a TSS semiconductor discharge tube. The differences between the TSS semiconductor discharge tube in this embodiment and the TSS semiconductor discharge tube in the first embodiment are:

The thickness of the protective layer is 20000Å.

Example 12

A TSS semiconductor discharge tube provided by the twelfth embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The thickness of the protective layer is 25000Å.

Example 13

A TSS semiconductor discharge tube provided by the thirteenth embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The thickness of the metal layer is 8000Å.

Example 14

The fourteenth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The thickness of the metal layer is 15000Å.

Example 15

The fifteenth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron pre-expansion temperature in the P ⁺ region is 1000°C.

Example 16

The sixteenth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron pre-expansion temperature in the P ⁺ region is 1250°C.

Example 17

The seventeenth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron re-expansion temperature in the P ⁺ region is 1200°C.

Example 18

The eighteenth embodiment of the present invention provides a TSS semiconductor discharge tube. The differences between the TSS semiconductor discharge tube in this embodiment and the TSS semiconductor discharge tube in the first embodiment are:

The boron re-expansion temperature in the P ⁺ region is 1275°C.

Example 19

A TSS semiconductor discharge tube provided by the nineteenth embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron pre-expansion temperature in P ^# area is 1000℃.

Example 20

A TSS semiconductor discharge tube provided by the twentieth embodiment of the present invention, the TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron pre-expansion temperature in P ^# area is 1250℃.

Example 21

The twenty-first embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron re-expansion temperature in P ^# area is 1200℃.

Example 22

The twenty-second embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron re-expansion temperature in P ^# area is 1275℃.

Example 23

The twenty-third embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron pre-diffusion temperature in the P ^- region is 1000°C.

Example 24

The twenty-fourth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron pre-diffusion temperature of the P ^- region is 1275°C.

Example 25

The twenty-fifth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron rediffusion temperature of the P ^- region is 1100°C.

Example 26

The twenty-sixth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The boron rediffusion temperature of the P ^- region is 1275°C.

Example 27

The twenty-seventh embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The phosphorus pre-diffusion temperature in the N ⁺ region is 1000°C.

Example 28

The twenty-eighth embodiment of the present invention provides a TSS semiconductor discharge tube. The difference between the TSS semiconductor discharge tube in this embodiment and the TSS semiconductor discharge tube in the first embodiment is:

The phosphorus pre-diffusion temperature in the N ⁺ region is 1100°C.

Example 29

The twenty-ninth embodiment of the present invention provides a TSS semiconductor discharge tube. The TSS semiconductor discharge tube in this embodiment is different from the TSS semiconductor discharge tube in the first embodiment in that:

The phosphorus rediffusion temperature in the N ⁺ region is 1100°C.

Example 30

The thirtieth embodiment of the present invention provides a TSS semiconductor discharge tube. The difference between the TSS semiconductor discharge tube in this embodiment and the TSS semiconductor discharge tube in the first embodiment is:

The phosphorus rediffusion temperature in the N ⁺ region is 1250°C.

Comparative example 1

A TSS semiconductor discharge tube provided in the first comparative example of the present invention, the difference between the TSS semiconductor discharge tube in this comparative example and the TSS semiconductor discharge tube in the first embodiment is:

The whole is doped with boron by ion implantation.

Please refer to Table 1 below, which shows the performance test results of the TSS semiconductor discharge tubes prepared in different embodiments and comparative examples.

Table 1

Combining the data of Example 1 to Example 30 and Comparative Example 1, it can be seen that the surge capability of the TSS semiconductor discharge tube can be effectively improved, and the residual voltage and capacitance can be reduced by optimizing the structure.

Combining the data of Examples 1 to 3, it can be seen that when the junction depth of the P ⁺ region is too shallow, the surge capability is weaker and cannot reach the surge capability required by the device. When the junction depth of the P ⁺ region reaches 60 μm, it has reached Surge peak, when the junction depth of the P ⁺ region is too deep, the N-type silicon chip will break down, resulting in a decrease in device performance.

Combining the data of Example 1, Example 4, and Example 5, it can be seen that when the junction depth of the P ^- region is too shallow, the surge capability is weaker, and when the junction depth of the P ^- region is too deep, it will affect the P ⁺ region and P ^# The flow capacity of the area, resulting in a drop in peak pulse current.

Combining the data of Example 1, Example 6 to Example 8, it can be seen that when the junction depth of the P ^# area is too shallow, the surge capability will be weaker, and when the junction depth of the P ^# area is too deep, it will affect the flow capacity of the P ⁺ area , resulting in a drop in peak pulse current.

Combining the data of Example 1, Example 9, and Example 10, it can be known that the diameter of the N ⁺ region will affect the flow capacity of the product. When the diameter of the N ⁺ area is too large, the flow capacity will become weaker, and the sustaining current will become larger, resulting in The decrease of the peak pulse current; the diameter of the N ⁺ region is too small, the maintenance current cannot be formed, and the flow capacity becomes weak, resulting in a decrease of the peak pulse current.

Combining the data of Example 1, Example 11, and Example 12, it can be seen that when the thickness of the protective layer is too thin, there will be carrier drift at the edge of the PN junction, which will generate dark current and affect the surge capability of the device. When the thickness is too thick, it will not affect the parameters of the device, but will increase the time cost and material cost.

Combining the data of Example 1, Example 13, and Example 14, it can be seen that when the thickness of the metal layer is too thin, the package is easy to desolder, resulting in weaker surge capability, lower flow capacity, and larger capacitance; when the thickness of the metal layer When the thickness is too thick, the performance of the device will not be affected, but the time cost and material cost will be increased.

Combining the data of Example 1, Example 15, and Example 16, it can be seen that when the pre-spreading temperature of the P ⁺ region is too low, the boron doping diffusion is uneven, and the surge capability decreases; when the pre-spreading temperature of the P ⁺ region is too high , Boron diffusion is too fast, more surface defects, poorer uniformity, and lower surge capability.

Combining the data of Example 1, Example 17, and Example 18, it can be seen that when the respreading temperature of the P ⁺ region is too low, the boron doping diffusion is uneven and the surge capability decreases; when the respreading temperature of the P ⁺ region is too high , Boron diffusion is too fast, more surface defects, poorer uniformity, and lower surge capability.

In conjunction with the data of Example 1, Example 19, and Example 20, it can be seen that when the pre-spreading temperature of the P ^# district was too low, the dopant diffusion was uneven, and the surge capability decreased; when the pre-spreading temperature of the P ^# district was too high, Exceeding the pre-diffusion temperature of the P ⁺ region will affect the concentration distribution of boron in the P ⁺ region, causing the uniformity of boron in the P ⁺ region to deteriorate and the surge capability to decrease.

In conjunction with the data of Example 1, Example 21, and Example 22, it can be seen that when the re-expansion temperature of the P ^# district is too low, the dopant diffusion is uneven, and the surge capacity declines; when the re-expansion temperature of the P ^# district is too high, Exceeding the re-diffusion temperature of the P ⁺ region will affect the concentration distribution of boron in the P ⁺ region, causing the uniformity of boron in the P ⁺ region to deteriorate and the surge capability to decrease.

Combined with the data of Example 1, Example 23, and Example 24, it can be seen that when the pre-spreading temperature of the P ^- region is too low, the dopant diffusion is uneven, and the surge capability decreases; when the pre-spreading temperature of the P ^- region is too high, Exceeding the pre-diffusion temperature of the P ^# area will affect the concentration distribution of boron in the P ^# area, resulting in poor uniformity of boron in the P ⁺ area and a decrease in surge capability.

In conjunction with the data of Example 1, Example 25, and Example 26, it can be seen that when the re-expansion temperature of the P ^- region is too low, the dopant diffusion is uneven, and the surge capability decreases; when the re-expansion temperature of the P ^- region is too high, Exceeding the re-diffusion temperature of the P ^# area will affect the concentration distribution of boron in the P ^# area, causing the uniformity of boron in the P ⁺ area to deteriorate and the surge capability to decrease.

Combining the data of Example 1, Example 27, and Example 28, it can be seen that the pre-spreading temperature of the N ⁺ region is too low or too high, which will affect the flow capacity and cause a decrease in the peak pulse current.

Combining the data of Example 1, Example 29, and Example 30, it can be seen that the re-expansion temperature of the N ⁺ region is too low or too high, which will affect the surge capability and cause a decrease in the surge capability.

To sum up, through the optimization of the structure, the surge capability of the TSS semiconductor discharge tube can be effectively improved, and the residual voltage and capacitance can be reduced.

In the description of this specification, reference to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" means that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present invention. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. a kind of TSS semiconductor discharge tube, comprises N-type silicon slice, it is characterized in that, the two sides of described N-type silicon slice are respectively provided with P ⁺ district and P ^# district and P ^- district, and described P ^# district is set Between the P ⁺ area and the P ^- area, the depth of the P ⁺ area is greater than the depth of the P ^# area, and the depth of the P ^# area is greater than the depth of the P ^- area; The P ^# area is photoetched with several N ⁺ areas on the side far away from the N-type silicon chip, and the P ^# area is provided with a metal layer on the side far away from the N-type silicon chip, and the metal layer Protective layers are provided on both sides. 2. The TSS semiconductor discharge tube according to claim 1, wherein the N-type silicon chip comprises a first N-type portion and a second N-type portion connected to the first N-type portion, and the first N-type portion is connected to the first N-type portion. The two sides of an N-type part are respectively provided with the P ⁺ region, the P ^# region and the P ^- region side by side, and the second N-type part is arranged on the side of the P ⁺ region away from the P ^# region side. 3. The TSS semiconductor discharge tube according to claim 2, wherein the protection layer comprises a first protection sublayer and a second protection sublayer, and the first protection sublayer is arranged on the P ^- region , the second protective sublayer is disposed on the second N-type portion. 4. The TSS semiconductor discharge tube according to claim 3, characterized in that, the junction depth of the P ⁺ region is 50-70 μm, the junction depth of the P ^# region is 15-40 μm, and the junction depth of the N ⁺ region The diameter is 8-12μm, and the junction depth of the P ^- region is 20-30μm. 5. a preparation method of TSS semiconductor discharge tube, it is characterized in that, described preparation method is used for preparing the TSS semiconductor discharge tube described in any one of claim 1-4, and described preparation method comprises: Select N-type silicon wafer; growing oxide layers on both sides of the N-type silicon wafer; On both sides of the N-type silicon chip, photoetching the P ⁺ well area, performing boron pre-diffusion and boron re-diffusion distribution on the P ⁺ well area, forming a P ^# area and a P ⁺ area; On both sides of the N-type silicon chip, photoetching the P ^- well region, performing boron pre-diffusion and boron re-diffusion distribution on the P ^- well region to form a P ^- region; Photoetching an N ⁺ well region on the side of the P ⁺ region away from the N-type silicon wafer, performing phosphorus pre-diffusion and phosphorus re-diffusion distribution on the N ⁺ well region, to form an N ⁺ region; Depositing protective layers on both sides of the N-type silicon wafer; Metal deposition, photolithography, etching, electrodes are formed in the protective layer gap, and metal layers are formed on both sides of the N-type silicon wafer; alloy. 6. The preparation method of TSS semiconductor discharge tube according to claim 5, is characterized in that, carries out boron pre-diffusion and boron re-diffusion distribution to described P ^- well region, forms the step of P ^- region, specifically comprises: The surface of the P ^- well area is evenly coated with a boron source and nitrogen and oxygen are introduced, the pre-diffusion temperature is 1000-1250°C, and the time is 2-30h; the re-diffusion temperature is 1100-1275°C, and the time is 5-10h, Form a P ^- region with a junction depth of 20-30 µm. 7. the preparation method of TSS semiconductor discharge tube according to claim 5 is characterized in that, carries out boron pre-diffusion and boron re-diffusion distribution to described P ⁺ well region, forms the step of P ^# district and P ⁺ district, specifically include: Uniformly coat the boron source on the surface of the P ⁺ well region and pass nitrogen and oxygen gas, the pre-diffusion temperature is 1000-1250°C, the time is 2-30h; the re-diffusion temperature is 1200-1275°C, the time is 9-120h, Form a P ⁺ region with a junction depth of 50-70 μm. 8. The preparation method of the TSS semiconductor discharge tube according to claim 5 is characterized in that, the boron source is evenly coated on the surface of the P ^# area and feeds nitrogen and oxygen, the boron pre-expansion temperature is 1000-1250 ℃, and the time is 2 -30h; the re-diffusion temperature is 1200-1275°C, and the time is 9-120h, forming a P ^# region with a junction depth of 15-40μm. 9. The preparation method of the TSS semiconductor discharge tube according to claim 5, characterized in that, the step of performing phosphorus pre-diffusion and phosphorus re-diffusion distribution on the N ⁺ well region to form an N ⁺ region specifically includes: PoCl ₃ is introduced into the N ⁺ well area, the pre-diffusion temperature is 1000-1100°C, and the time is 1-2h; the re-diffusion temperature is 1100-1250°C, and the time is 1-6h, forming an N ⁺ area. 10. The preparation method of TSS semiconductor discharge tube according to claim 5, characterized in that, the synthesis temperature of the alloy is 400-530°C, the synthesis time is 10-30min, and the vacuum degree is 5×10 ^-4 -5 ×10 ^-3 Pa.

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