CN111276547A - High-surge-capability low-residual-voltage TVS anti-surge device and manufacturing method thereof - Google Patents

Abstract

The invention relates to a high surge capacity and low residual voltage TVS anti-surge device and a manufacturing method thereof, belonging to the technical field of microelectronics. Bottom silicon wafer, wherein a vertical TVS anti-surge device is formed on both sides of a P-type or N-type substrate through a PN junction main junction preparation post-thinning process and a secondary homotype doping diffusion junction, and the PN junction junction The depth is 15-35 μm, and there is a contact metal layer on the surface of the doped surface, and a passivation layer is covered on the side of the substrate. The present invention also provides a preparation method of the above device. The invention has obvious improvement effect on devices that have requirements for long-wavelength surge capability, such as: IEC61000 10/1000μs surge waveform and ISO7637‑2 5A/5B waveform.

Description

A kind of TVS anti-surge device with high surge capability and low residual voltage and its manufacturing method

technical field

The invention relates to the technical field of microelectronics, in particular to a TVS anti-surge device with low residual voltage and high surge and a manufacturing method thereof.

Background technique

A surge (electrical surge) is an instantaneous peak that exceeds a stable value, including surge voltage and surge current. Essentially, a surge is a violent pulse that occurs in just a few millionths of a second. Possible causes of surges include: lightning strikes, overlapping power lines, vehicle load dumps, etc.

When a lightning surge occurs, dangerous overvoltage may be generated within a range of 1.5~2KM with the lightning strike as the center. Lightning-induced (external) surges are characterized by single-phase pulses with enormous energy. The voltage of an external surge can rapidly rise from a few hundred volts to 20,000V in a few microseconds and can be transmitted over considerable distances. , the instantaneous surge can be as high as 20000V, and the instantaneous current can reach 10000A. It will cause great damage to electronic equipment.

Transient Voltage Suppressor (TVS) is a high-efficiency electrostatic surge protection device, which plays an important protective role in the circuit. With the continuous application of handheld devices, electrostatic protection devices are widely used. Strong surge capability and low residual voltage are the direction of device optimization.

Improving the surge capability and reducing the residual voltage is the goal that TVS devices have been pursuing. Improving the surge capability can effectively protect the device from being damaged when it is subjected to more severe surge interference. The low residual voltage can better eliminate the influence of the surge on the back-end circuit, and prevent the back-end circuit from being damaged after being affected by the residual voltage. At present, process technologies such as negative resistance process, resistivity adjustment process, and thin film process are used to improve the surge capability per unit area. But it still failed to meet our requirements.

SUMMARY OF THE INVENTION

In order to solve the problem that the residual voltage of the traditional semiconductor anti-surge device is weak, especially the long-wavelength surge capability is weak. The purpose of the invention is to provide a TVS anti-surge device with high surge capability and low residual voltage.

Another object of the present invention is to provide a preparation method of the above TVS anti-surge device.

The object of the present invention is achieved through the following scheme: a high surge capability and low residual voltage TVS anti-surge device, comprising a P-type or N-type substrate silicon wafer, wherein, on the double-sided or single-sided of the P-type or N-type substrate The vertical TVS anti-surge device is formed by the thinning process after the preparation of the main junction of the PN junction and the secondary homotype doping diffusion junction. The junction depth of the PN junction is 15-35 μm, and there is a contact metal layer on the surface of the doped surface. , the side of the substrate is covered with a passivation layer.

On the basis of the above scheme, the substrate silicon wafer is a P-type substrate silicon wafer. After the first main junction doping and diffusion on both sides of the silicon wafer, the thinning process after the main junction preparation is carried out. The junction depth is between 10-35μm, and the sheet thickness is between 150μm and 400μm; after that, a second homotype doping diffusion junction is performed to form a vertical NPN structure, wherein the second diffusion junction depth is less than or equal to the first doping After the impurity diffusion is thinned, the junction depth is half, and finally, a vertical NPN structure TVS anti-surge device with a breakdown voltage between 8V and 150V is formed.

On the basis of the above solution, the substrate silicon wafer is an N-type substrate silicon wafer. After the first main junction doping and diffusion on both sides of the silicon wafer, the thinning process after the main junction preparation is performed to reduce the thickness. The depth of the back junction is between 10-35 μm, and the thickness of the sheet is between 150 μm and 400 μm; after that, a second homotype doping diffusion junction is performed to form a vertical PNP structure, wherein the depth of the second diffusion junction is less than or equal to the first time. Half of the junction depth after the doping diffusion is thinned, and finally, a vertical PNP structure TVS anti-surge device with a breakdown voltage between 8V and 150V is formed.

In particular, the present invention has a more obvious lifting effect on long-wavelength surges.

The present invention also provides a preparation method of the above-mentioned TVS anti-surge device, comprising the following main steps:

(1) Take the P-type boron-doped silicon substrate sheet and adopt double-sided junction: take the P-type boron-doped 4-inch sheet substrate, adopt the method of paper source diffusion to initially diffuse the double-sided phosphorus, and perform the slicing after the initial expansion and doping. Carry out the main junction push junction diffusion, the diffusion temperature is 1200-1260 ℃, the time is 16 hours, and the NPN structure is formed. At this time, the breakdown voltage is 26V, and the junction depth is 40μm;

(2) Thinning process after main junction preparation: using double-sided CMP process, the thinning depth is 20 μm, and the remaining junction depth is 30 μm;

(3) Second diffusion: use a phosphorus source for initial diffusion, the diffusion temperature is 800 °C for 20 minutes, and then re-diffusion is performed at 900 °C for 10 minutes to form a concentrated phosphorus layer N+ heavy doping, the second The secondary diffusion junction depth is less than or equal to half of the remaining junction depth after the first doping diffusion thinning;

(4) Double-sided metal preparation: AL metal is evaporated as the contact metal, and independent AL metal solder joints are obtained by photolithography etching, and the NPN structure TVS anti-surge device is made.

The present invention also provides another preparation method of the above-mentioned TVS anti-surge device, comprising the following main steps:

(1) Take an N-type silicon substrate sheet, and adopt double-sided junction: take an N-type phosphorus-doped 6-inch wafer substrate, and use the boron pre-deposition method to make a junction. After the initial expansion and doping is completed, the main junction is pushed out. Diffusion, the diffusion temperature is 1160°C for 24 hours, and a PNP structure is formed. At this time, the breakdown voltage of the device is determined to be 64V, and the junction depth is 50μm;

(2) Thinning process after main junction preparation: using double-sided CMP process, the thinning depth is 35 μm, and the remaining junction depth is 15 μm;

(3) Second diffusion: pre-deposit and diffuse boron again, use 900°C for 10 minutes to re-diffusion to form a concentrated phosphorus layer, and the junction depth of the second diffusion is less than or equal to the remaining junction after the first doping diffusion thinning. half the depth;

(4) Double-sided metal preparation: AL metal is evaporated on the front and back as the contact metal, and independent AL metal solder joints are obtained by photolithography etching, and the PNP structure TVS anti-surge device is made.

In the preparation steps of the present invention, the required breakdown voltage is obtained by pushing the junction by diffusion; the depth of the junction is reduced by thinning after the junction is formed; and the surface is heavily doped by secondary doping to form a better ohmic region contact, reducing ohmic contact resistance.

Positive effects of the present invention: The present invention has obvious improvement effects for devices that require long-wavelength surge capability, such as: IEC6100010/1000μs surge waveform and ISO7637-2 5A/5B waveform.

Description of drawings

Fig. 1 embodiment 1 cross-sectional schematic diagram of a mesa NPN structure TVS anti-surge device;

2 to 6 are schematic cross-sectional views of the silicon wafer structure formed in each step of Embodiment 1;

Fig. 7 embodiment 2 cross-sectional schematic diagram of mesa PNP structure TVS anti-surge device;

8 to 12 are schematic cross-sectional views of the silicon wafer structure formed in each step of Embodiment 2;

Figure 13 is a schematic cross-sectional view of a planar NPN structure TVS unidirectional surge protection device;

Description of the labels in the figure:

Example 1

100——P-type substrate;

101, 102 - N-type doping on the front and back

103, 104—the second front and back N+ doping;

105, 106 - left and right mesa grooves;

107 - passivation layer;

108, 109 - front and back metal contact layers;

In Example 2

200——N-type substrate;

201, 202 - P-type doping on the front and back;

203, 204 - P+ type doping on the front and back;

205, 206 - left and right mesa grooves;

207 - passivation layer;

208, 209 - front and back metal contact layers;

In Example 3:

300——P-type substrate;

301, 302 - front and back N-type doping;

303, 304 - positive and back N+ type doping;

305 - passivation layer;

306, 307 - front and back metal contact layers.

Detailed ways

Example 1

A mesa NPN structure TVS anti-surge device, as shown in Figure 1, the substrate silicon wafer is a P-type substrate 111 silicon wafer, the resistivity is 0.046Ωcm, and the two sides of the silicon wafer are formed by secondary N-type doping. Vertical NPN structure, in which the concentration of the first front and back N-type doping 101, 102 is lower than that of the second front and back N+ doping 103, 104, and there are left and right mesa trenches 105, 106 on both sides of the silicon wafer , is covered by a glass passivation layer 107, the two sides of the vertical NPN structure have front and back metal contact layers 108, 109, forming a mesa NPN structure TVS anti-surge device, the device operating voltage is 20V.

The countertop NPN structure TVS anti-surge device of the present embodiment is prepared according to the following steps:

(1) The P-type substrate 111 is fed with a P-type boron-doped 4-inch substrate. First, phosphorus is used for preliminary diffusion, and then push-junction diffusion is performed. The NPN structure of hetero 101 and 102 has a junction depth of about 40 μm, and the obtained silicon wafer is shown in Figure 2;

(2) The above-mentioned silicon wafer is thinned by double-sided CMP process, the thinning depth is 10 μm, and the remaining junction depth is about 30 μm, as shown in Figure 3;

(3) Use a phosphorus source for initial diffusion, the diffusion temperature is 800 °C for 20 minutes, and then the concentrated phosphorus layer obtained by re-diffusion at 900 °C for 10 minutes is positive and back N+ doping 103, 104, as shown in Figure 4 ;

(4) Photolithography, etching to form left and right mesa trenches 105, 106, as shown in FIG. 5;

(5) Carry out passivation treatment, cover the glass passivation layer 107 on the side, and then open metal connection holes by photolithography, as shown in FIG. 6 ;

(6) Evaporating AL metal as the front and back metal contact layers 108, 109, and lithography etching to obtain independent AL metal solder joints to obtain a mesa NPN structure TVS surge protection device as shown in FIG. 1 .

The device of this embodiment is tested, the breakdown voltage of the device is 26V, the leakage current at 20V is less than 0.1μA, the surge intensity of 10-100 waveforms using the traditional process device package is 800V, and the surge after the new process device package is greater than 1000V. Surge capacity increased by 25%.

Example 2

A mesa PNP structure TVS anti-surge device, as shown in Figure 7, the substrate silicon wafer is an N-type substrate 200 silicon wafer, and a vertical PNP structure is formed on both sides of the silicon wafer by secondary P-type doping, Among them, the concentration of the first front and back P-type doping 201, 202 is lower than that of the second positive and back P+ type doping 203, 204, and there are left and right mesa trenches 205, 206 on both sides, which are passivated by glass The layer 207 is covered, and the vertical PNP structure has front and back metal contact layers 208 and 209 to form a mesa PNP structure TVS anti-surge device. The breakdown voltage of the device is 68V.

The countertop PNP structure TVS anti-surge device of the present embodiment is prepared according to the following steps:

(1) The N-type substrate 200 selects the N-type phosphorus-doped 6-inch wafer substrate for feeding, and the boron pre-deposition method is used to make the junction. After the initial doping is completed, push-junction diffusion is performed. For hours, there are front and back P-type doping 201, 202 on the silicon wafer to form a vertical PNP structure with a junction depth of about 50 μm, as shown in Figure 8;

(2) Thinning by double-sided CMP process, the thinning depth is 35 μm, and the remaining junction depth is about 15 μm, as shown in Figure 9;

(3) Pre-deposition and diffusion of boron is performed again, and the concentrated phosphorus layer formed by re-diffusion under the conditions of 900 ° C and 10 minutes is the front and back P+ type doping 203 and 204, as shown in Figure 10;

(4) Photolithography, etching to form left and right mesa trenches 205, 206, as shown in FIG. 11;

(5) Carry out passivation treatment, cover the glass passivation layer 207 on the side, and then open metal connection holes by photolithography, as shown in Figure 12;

(6) Evaporating the AL metal as the contact metal to form the front and back metal contact layers 208 and 209, and lithography etching to obtain independent AL metal solder joints, the prepared mesa PNP structure TVS surge protection device is shown in Figure 7.

For the device test of this embodiment, the breakdown voltage of the device is 68V, and the leakage current is less than 0.05μA under the working voltage of 58V. The surge capability of the device in this embodiment is improved by more than 10% compared with the traditional process.

Example 3

A planar NPN structure TVS unidirectional surge protection device is only a vertical NPN structure. As shown in Figure 13, the substrate silicon wafer is a P-type substrate 300 silicon wafer, and there are passes on both sides of the silicon wafer. The secondary N-type doping forms a vertical NPN structure, wherein the first N-type doping forms the front and back N-type doping 301, 302 with a concentration lower than the second positive and back N+-type doping 303, 304. Covered by a silicon dioxide passivation layer 305, and a metal contact hole is opened, and there are front and back metal contact layers 306 and 307 in the metal contact hole, forming a flat NPN structure TVS unidirectional surge device.

Claims (6)

1. a high surge capacity low residual voltage TVS anti-surge device, comprising P-type or N-type substrate silicon wafer, it is characterized in that, after the double-sided preparation of P-type or N-type substrate by PN junction main junction The thinning process and the secondary homotype doping diffusion junction form a vertical TVS anti-surge device. The junction depth of the PN junction is 15-35 μm, the surface of the doped surface has a contact metal layer, and the side of the substrate is covered with a passivation chemical layer. 2. The high surge capability and low residual voltage TVS anti-surge device according to claim 1, wherein the substrate silicon wafer is a P-type substrate silicon wafer, and the two sides of the silicon wafer pass through the No. After the primary junction doping diffusion, the main junction preparation and post-thinning process are carried out. After thinning, the junction depth is between 10-35 μm, and the thickness is between 150 μm and 400 μm; after that, the second homotype doping diffusion junction is performed. A vertical NPN structure is formed, wherein the junction depth of the second diffusion is less than or equal to half of the junction depth after the first doping diffusion thinning, and finally, a vertical NPN structure TVS with a breakdown voltage between 8V and 150V is formed to prevent surge device. 3. The high surge capability and low residual voltage TVS anti-surge device according to claim 1, wherein the substrate silicon wafer is an N-type substrate silicon wafer, and the two sides of the silicon wafer pass through the No. After the primary junction doping diffusion, the thinning process after the main junction preparation is carried out. After thinning, the junction depth is between 10-35 μm, and the sheet thickness is between 150 μm and 400 μm; after that, the second homotype doping diffusion is performed. The junction forms a vertical PNP structure, wherein the junction depth of the second diffusion is less than or equal to half of the junction depth after the first doping diffusion thinning, and finally, a vertical PNP structure TVS with a breakdown voltage between 8V and 150V is formed to prevent surge device. 4. a preparation method of TVS anti-surge device according to claim 1 and 2, is characterized in that, comprises the following steps: (1) Take the P-type boron-doped silicon substrate sheet and adopt double-sided junction: take the P-type boron-doped 4-inch sheet substrate, adopt the method of paper source diffusion to initially diffuse the double-sided phosphorus, and perform the slicing after the initial expansion and doping. Carry out the main junction push junction diffusion, the diffusion temperature is 1200-1260 ℃, the time is 16 hours, and the NPN structure is formed. At this time, the breakdown voltage is 26V, and the junction depth is 40μm; (2) Thinning process after main junction preparation: using double-sided CMP process, the thinning depth is 20 μm, and the remaining junction depth is 30 μm; (3) Second diffusion: use a phosphorus source for initial diffusion, the diffusion temperature is 800 °C for 20 minutes, and then re-diffusion is performed at 900 °C for 10 minutes to form a concentrated phosphorus layer N+ heavy doping, the second The secondary diffusion junction depth is less than or equal to half of the remaining junction depth after the first doping diffusion thinning; (4) Double-sided metal preparation: AL metal is evaporated as the contact metal, and independent AL metal solder joints are obtained by photolithography etching, and the NPN structure TVS anti-surge device is made. 5. a preparation method of TVS anti-surge device according to claim 1 and 3, is characterized in that, comprises the following steps: (1) Take an N-type silicon substrate sheet, and adopt double-sided junction: take an N-type phosphorus-doped 6-inch wafer substrate, and use the boron pre-deposition method to make a junction. After the initial expansion and doping is completed, the main junction is pushed out. Diffusion, the diffusion temperature is 1160°C for 24 hours, and a PNP structure is formed. At this time, the breakdown voltage of the device is determined to be 64V, and the junction depth is 50μm; (2) Thinning process after main junction preparation: using double-sided CMP process, the thinning depth is 35 μm, and the remaining junction depth is 15 μm; (3) Second diffusion: pre-deposit and diffuse boron again, use 900°C for 10 minutes to re-diffusion to form a concentrated phosphorus layer, and the junction depth of the second diffusion is less than or equal to the remaining junction after the first doping diffusion thinning. half the depth; (4) Double-sided metal preparation: AL metal is evaporated on the front and back as the contact metal, and independent AL metal solder joints are obtained by photolithography etching, and the PNP structure TVS anti-surge device is made. 6. the preparation method of TVS anti-surge device according to claim 4 or 5, is characterized in that, thinning after main junction preparation is not limited to chemical mechanical polishing (CMP), also comprise chemical corrosion, the method for mechanical polishing to reduce Thin, the thinning thickness is not greater than the junction depth.

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