CN116088623A - NMOS low dropout linear voltage regulator, chip and electronic equipment - Google Patents

Abstract

The embodiment of the disclosure provides an NMOS low dropout linear voltage regulator, a chip and electronic equipment, and belongs to the technical field of LDO. The NMOS LDO includes: the soft start circuit, the error amplifier and the buffer stage are sequentially coupled; the output end of the buffer stage is coupled with the first electrode of the first transistor and the first node; the control electrode of the first transistor is coupled with the second electrode and the second node of the first transistor; the switch control circuit is coupled between the first node and the second node; the output end of the charge pump circuit is coupled with the control electrode of the NMOS power tube and the second node; the second pole of the NMOS power tube is coupled with the first voltage end, and the first pole of the NMOS power tube is sequentially coupled with the output end of the NMOS LDO, the first feedback resistor, the second feedback resistor and the second voltage end. The soft start circuit controls the starting signal to rise along with the rising of the power supply voltage after being electrified until reaching a preset voltage value, and provides the starting signal to the switch control circuit; the switch control circuit controls the on-off of the first transistor by utilizing a starting signal so as to control the on-off of the NMOS power tube.

Description

NMOS low dropout linear regulator, chip and electronic equipment

technical field

Embodiments of the present disclosure relate to the technical field of low dropout regulator (Low Dropout Regulaor, LDO), in particular to an NMOS LDO, a chip and an electronic device.

Background technique

A low dropout linear regulator is a linear voltage regulator. LDO can be divided into PMOS LDO and NMOS LDO according to whether the power tube used is NMOS power tube or PMOS power tube. In the traditional NMOS LDO, after the power supply voltage is powered on, before the soft-start circuit is turned on, the NMOS power transistor is turned on due to the high gate voltage of the NMOS power transistor, which causes a "step"-shaped fluctuation in the output voltage of the NMOS LDO, which affects subsequent loads. normal operation of the circuit.

Contents of the invention

The purpose of the embodiments of the present disclosure is to provide an NMOS low dropout linear voltage regulator, chip and electronic equipment, using the startup signal generated by the soft-start circuit after power-on to control the on-off of the NMOS power tube, when the soft-start circuit does not When working, the NMOS power tube is controlled to be turned off, which eliminates the "step" fluctuation in the output voltage of the NMOS low-dropout linear regulator.

In order to achieve the above object, according to the first aspect of the present disclosure, an NMOS low dropout linear regulator is provided, including: a soft start circuit, a switch control circuit, a charge pump circuit, an NMOS power transistor, an error amplifier, a buffer stage, a first A transistor, a first feedback resistor and a second feedback resistor, wherein the output terminal of the soft start circuit is coupled to the non-inverting input terminal of the error amplifier, and the output terminal of the error amplifier is coupled to the input terminal of the buffer stage , the output terminal of the buffer stage is coupled to the first pole of the first transistor and the first node, the control pole of the first transistor is coupled to the second pole of the first transistor and the second node, the The switch control circuit is coupled between the first node and the second node, the output terminal of the charge pump circuit is coupled to the control electrode of the NMOS power transistor and the second node, and the NMOS power transistor The first pole of the NMOS low-dropout linear regulator is coupled to the first end of the first feedback resistor, the second pole of the NMOS power transistor is coupled to the first voltage terminal, and the first The second terminal of the feedback resistor is coupled to the first terminal of the second feedback resistor and the inverting input terminal of the error amplifier, and the second terminal of the second feedback resistor is coupled to the second voltage terminal. Wherein, the charge pump circuit is used to generate a bias voltage, and provide the bias voltage to the control electrode of the NMOS power transistor through the second node; the soft start circuit is used to control The start signal rises with the rise of the power supply voltage until it reaches a preset voltage value, and the start signal is provided to the switch control circuit; the switch control circuit is used to control the first transistor by using the start signal on and off to control the on and off of the NMOS power transistor.

In some embodiments of the present disclosure, the soft start circuit includes: a first current source and a first capacitor, wherein the first terminal of the first current source is coupled to the first voltage terminal, and the first The second terminal of the current source is coupled to the first terminal of the first capacitor and the output terminal of the soft start circuit, and the second terminal of the first capacitor is coupled to the second voltage terminal.

In some embodiments of the present disclosure, the charge pump circuit includes: a charge pump and an internal resistance of the charge pump, the output terminal of the charge pump is coupled to the first end of the internal resistance of the charge pump, and the internal resistance of the charge pump The second terminal of is coupled to the output terminal of the charge pump circuit.

In some embodiments of the present disclosure, the switch control circuit includes: a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a second capacitor, and a Schmitt trigger, wherein, The control pole of the second transistor is coupled to the first output terminal of the Schmitt trigger, the first pole of the second transistor is coupled to the third voltage terminal, and the second pole of the second transistor is coupled to The first terminal of the third resistor; the control pole of the third transistor is coupled to the second output terminal of the Schmitt trigger, and the first pole of the third transistor is coupled to the third resistor The first terminal of the resistor, the second pole of the third transistor is coupled to the second voltage terminal; the second terminal of the third resistor is coupled to the first terminal of the second capacitor; the fourth The control pole of the transistor is coupled to the first terminal of the second capacitor, the first pole of the fourth transistor is coupled to the first terminal of the fourth resistor, and the second pole of the fourth transistor is coupled to the the second node; the second end of the fourth resistor is coupled to the first node; the second capacitor is coupled to the second voltage end; the input of the Schmitt trigger The terminal is coupled to the output terminal of the soft start circuit.

In some embodiments of the present disclosure, the Schmitt trigger includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor transistor, a fifth resistor, and a sixth resistor, wherein the control pole of the fifth transistor is coupled to the input terminal of the Schmitt trigger, and the first pole of the fifth transistor is coupled to the first voltage terminal, the second pole of the fifth transistor is coupled to the first pole of the sixth transistor and the first pole of the ninth transistor; the control pole of the sixth transistor is coupled to the Schmitt trigger The input terminal of the device, the second pole of the sixth transistor is coupled to the first pole of the seventh transistor and the second output terminal of the Schmitt trigger; the control pole of the seventh transistor is coupled to the The input terminal of the Schmitt trigger, the second pole of the seventh transistor is coupled to the first pole of the eighth transistor and the first pole of the tenth transistor; the control pole of the eighth transistor is coupled connected to the input terminal of the Schmitt trigger, the second pole of the eighth transistor is coupled to the second voltage terminal; the control pole of the ninth transistor is coupled to the second terminal of the Schmitt trigger output terminal, the second pole of the ninth transistor is coupled to the first terminal of the sixth resistor; the control pole of the tenth transistor is coupled to the second output terminal of the Schmitt trigger, the The second pole of the tenth transistor is coupled to the first terminal of the fifth resistor; the second terminal of the fifth resistor is coupled to the first voltage terminal; the second terminal of the sixth resistor is coupled to connected to the second voltage terminal; the control pole of the eleventh transistor is coupled to the second output terminal of the Schmitt trigger, and the first pole of the eleventh transistor is coupled to the first voltage terminal , the second pole of the eleventh transistor is coupled to the first output terminal of the Schmitt trigger; the control pole of the twelfth transistor is coupled to the second output terminal of the Schmitt trigger, A first pole of the twelfth transistor is coupled to the first output terminal of the Schmitt trigger, and a second pole of the twelfth transistor is coupled to the second voltage terminal.

In some embodiments of the present disclosure, when the startup signal output by the output terminal of the soft-start circuit does not reach the preset voltage value, the output of the first output terminal of the Schmitt trigger is a low voltage level, the output of the second output terminal of the Schmitt trigger is a high level; when the start signal output by the output terminal of the soft start circuit reaches the preset voltage value, the Schmitt trigger The output of the first output terminal of the trigger is high level, and the output of the second output terminal of the Schmitt trigger is low level.

In some embodiments of the present disclosure, when the first output terminal of the Schmitt trigger outputs a low level and the second output terminal of the Schmitt trigger outputs a high level, the fourth The transistor is turned on, the first transistor is short-circuited, and the NMOS power transistor is turned off.

In some embodiments of the present disclosure, when the first output terminal of the Schmitt trigger outputs a high level and the second output terminal of the Schmitt trigger outputs a low level, the fourth The transistor is turned off, the first transistor is connected to the circuit, and the NMOS power transistor is turned on.

According to a second aspect of the present disclosure, a chip is provided. The chip includes the NMOS low dropout linear voltage regulator according to the first aspect of the present disclosure.

According to a third aspect of the present disclosure, an electronic device is provided. The electronic device includes the chip according to the second aspect of the present disclosure.

Other features and advantages of the embodiments of the present disclosure will be described in detail in the detailed description that follows.

Description of drawings

The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the description, together with the following specific embodiments, are used to explain the embodiments of the present disclosure, but are not intended to limit the embodiments of the present disclosure. In the attached picture:

Fig. 1 is an exemplary circuit diagram of an NMOS LDO;

Figure 2 is a schematic diagram of a simulation waveform of an NMOS LDO;

3 is a schematic block diagram of an NMOS low dropout linear regulator according to an embodiment of the present disclosure;

4 is another schematic block diagram of an NMOS low dropout linear regulator according to an embodiment of the present disclosure;

5 is a schematic block diagram of a switch control circuit in an NMOS low dropout linear regulator according to an embodiment of the present disclosure;

6 is an exemplary circuit diagram of a Schmitt trigger according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of simulation waveforms of an NMOS low dropout linear regulator according to an embodiment of the present disclosure.

Elements in the drawings are schematic and not drawn to scale.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts also fall within the protection scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the specification and related technologies, and will not be interpreted in an idealized or overly formal manner, Unless otherwise expressly defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

In all the embodiments of the present disclosure, since the source and the drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current direction between the source and the drain of the N-type transistor and the P-type transistor is opposite , therefore, in the embodiments of the present disclosure, the controlled intermediate terminal of the MOS transistor is called the control pole, and the remaining two ends of the MOS transistor are respectively called the first pole and the second pole. In addition, terms such as "first" and "second" are only used to distinguish one element (or a part of a element) from another element (or another part of a element).

FIG. 1 shows an exemplary circuit diagram of an NMOS LDO 100. In the example of FIG. 1 , the soft-start circuit SoftStart is composed of a capacitor and a current source charging the capacitor, so that the input signal SS rises slowly, so that the output voltage VOUT rises slowly. Among them, the function of the transistor M0 is to prevent the source voltage of the source follower transistor Follower from being too high under heavy load (very large load current), thereby causing the output voltage of the error amplifier EA to be too high, resulting in abnormal operation of the error amplifier EA. In the example in Figure 1, when the power supply voltage VDD is powered on and the soft start circuit Soft Start is not turned on, the output voltage of the error amplifier EA is 0, and a gate-source voltage Vgs is generated through the source follower transistor Follower, and then passed through the transistor Diode, and generate a gate-source voltage Vgs, that is, the voltage at point Y is two gate-source voltages 2Vgs, the NMOS power tube is turned on, and a certain output current flows through the feedback resistors R1 and R2, resulting in a certain voltage at the output terminal VOUT , thus causing the output voltage to fluctuate in a "step" shape, as shown in the marked part of the output voltage VOUT waveform shown in FIG. 2 .

Embodiments of the present disclosure propose an NMOS low dropout linear regulator. The NMOS low-dropout linear regulator eliminates the NMOS low-dropout voltage drop by eliminating the gate-source voltage Vgs voltage drop caused by the source-following transistor Follower shown in Figure 1, and the gate-source voltage Vgs voltage drop caused by the transistor diode. A "step" shaped fluctuation in the output voltage of a linear regulator. FIG. 3 shows a schematic block diagram of an NMOS low dropout linear regulator 300 according to an embodiment of the present disclosure. As shown in FIG. 3, the NMOS low dropout linear regulator 300 may include: a soft start circuit 310, a switch control circuit 320, a charge pump circuit 330, an NMOS power transistor Mn0, an error amplifier EA, a buffer stage BUFFER, a first transistor M1, The first feedback resistor R1 and the second feedback resistor R2. Wherein, the output terminal of the soft start circuit 310 is coupled to the non-inverting input terminal of the error amplifier EA, the output terminal of the error amplifier EA is coupled to the input terminal of the buffer stage BUFFER, and the output terminal of the buffer stage BUFFER The first pole of the first transistor M1 is coupled to the first node N1, the control pole of the first transistor M1 is coupled to the second pole of the first transistor M1 and the second node N2, and the switch control circuit 320 is coupled between the first node N1 and the second node N2, the output terminal of the charge pump circuit 330 is coupled to the control electrode of the NMOS power transistor Mn0 and the second node N2, the The first pole of the NMOS power transistor Mn0 is coupled to the output terminal VOUT of the NMOS low dropout linear regulator 300 and the first end of the first feedback resistor R1, and the second pole of the NMOS power transistor Mn0 is coupled to the first terminal of the first feedback resistor R1. A voltage terminal V1, the second terminal of the first feedback resistor R1 is coupled to the first terminal of the second feedback resistor R2 and the inverting input terminal of the error amplifier EA, the second terminal of the second feedback resistor R2 The two terminals are coupled to the second voltage terminal V2.

Wherein, the charge pump circuit 330 is used to generate a bias voltage, and provide the bias voltage to the control electrode of the NMOS power transistor through the second node N2. The soft-start circuit 310 can also be coupled to the first voltage terminal V1 and the second voltage terminal V2, and is used to control the start-up signal SS to rise slowly with the rise of the power supply voltage until reaching a preset voltage value after power-on, and The start signal SS is provided to the switch control circuit 320 . The switch control circuit can be coupled to the soft start circuit 310, the first voltage terminal V1, the second voltage terminal V2, and the third voltage terminal V3, and is used to control the on-off of the first transistor M1 by using the start signal SS. to control the on-off of the NMOS power transistor Mn0.

According to the NMOS low dropout linear voltage regulator of the embodiment of the present disclosure, the startup signal generated after the soft-start circuit is powered on is used to control the on-off of the NMOS power tube. When the soft-start circuit is not working, the NMOS power tube is controlled to be turned off. The "step" shaped fluctuation in the output voltage of the NMOS low dropout linear regulator is eliminated.

FIG. 4 shows another schematic block diagram of an NMOS low dropout linear regulator 300 according to an embodiment of the present disclosure. As shown in FIG. 4, the soft start circuit 310 may include: a first current source _IA and a first capacitor C1. Wherein, the first terminal of the first current source I _A is coupled to the first voltage terminal V1, and the second terminal of the first current source I _A is coupled to the first terminal of the first capacitor C1 and the soft The output terminal of the start-up circuit 310, the second terminal of the first capacitor C1 is coupled to the second voltage terminal V2. The charge pump circuit 330 may include: a charge pump Charg pump and an internal resistance R0 of the charge pump. The output end of the charge pump Charg pump is coupled to the first end of the charge pump internal resistance R0 , and the second end of the charge pump internal resistance R0 is coupled to the output end of the charge pump circuit 330 .

FIG. 5 shows a schematic block diagram of the switch control circuit 320 in the NMOS low dropout linear regulator 300 according to an embodiment of the present disclosure. As shown in FIG. 5, the switch control circuit 320 may include: a second transistor M2, a third transistor M3, a fourth transistor M4, a third resistor R3, a fourth resistor R4, a second capacitor C2 and a Schmitt trigger 210. Wherein, the control electrode of the second transistor M2 is coupled to the first output terminal of the Schmitt trigger 210, the first electrode of the second transistor M2 is coupled to the third voltage terminal V3, and the second transistor M2 The second pole of M2 is coupled to the first end of the third resistor R3. The control electrode of the third transistor M3 is coupled to the second output end of the Schmitt trigger 210, and the first electrode of the third transistor M3 is coupled to the first end of the third resistor R3, so The second pole of the third transistor M3 is coupled to the second voltage terminal V2. The second end of the third resistor R3 is coupled to the first end of the second capacitor C2. The control electrode of the fourth transistor M4 is coupled to the first end of the second capacitor C2, the first electrode of the fourth transistor M4 is coupled to the first end of the fourth resistor R4, and the fourth The second pole of the transistor M4 is coupled to the second node N2. A second end of the fourth resistor R4 is coupled to the first node N1. A second terminal of the second capacitor C2 is coupled to the second voltage terminal V2. The input end of the Schmitt trigger 210 is coupled to the output end of the soft start circuit 310 .

In addition, FIG. 6 shows an exemplary circuit diagram of a Schmitt trigger 210 according to an embodiment of the present disclosure. As shown in FIG. 6, the Schmitt trigger 210 may include: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11 , the twelfth transistor M12, the fifth resistor R5 and the sixth resistor R6. Wherein, the control electrode of the fifth transistor M5 is coupled to the input terminal of the Schmitt trigger 210, the first electrode of the fifth transistor M5 is coupled to the first voltage terminal V1, and the fifth transistor M5 The second pole of M5 is coupled to the first pole of the sixth transistor M6 and the first pole of the ninth transistor M9. The control electrode of the sixth transistor M6 is coupled to the input terminal of the Schmitt trigger 210, and the second electrode of the sixth transistor M6 is coupled to the first electrode of the seventh transistor M7 and the Schmitt trigger. The second output terminal VOP of the special flip-flop 210 . The control electrode of the seventh transistor M7 is coupled to the input terminal of the Schmitt trigger 210, and the second electrode of the seventh transistor M7 is coupled to the first electrode of the eighth transistor M8 and the tenth transistor M8. The first pole of the transistor M10. A control electrode of the eighth transistor M8 is coupled to the input terminal of the Schmitt trigger 210 , and a second electrode of the eighth transistor M8 is coupled to the second voltage terminal V2. A control electrode of the ninth transistor M9 is coupled to the second output terminal VOP of the Schmitt trigger 210 , and a second electrode of the ninth transistor M9 is coupled to the first end of the sixth resistor R6 . A control electrode of the tenth transistor M10 is coupled to the second output terminal VOP of the Schmitt trigger 210 , and a second electrode of the tenth transistor M10 is coupled to the first end of the fifth resistor R5 . A second end of the fifth resistor R5 is coupled to the first voltage end V1. A second terminal of the sixth resistor R6 is coupled to the second voltage terminal V2. The control electrode of the eleventh transistor M11 is coupled to the second output terminal VOP of the Schmitt trigger 210, the first electrode of the eleventh transistor M11 is coupled to the first voltage terminal V1, the The second pole of the eleventh transistor M11 is coupled to the first output terminal VON of the Schmitt trigger 210 . The control electrode of the twelfth transistor M12 is coupled to the second output terminal VOP of the Schmitt trigger 210 , and the first electrode of the twelfth transistor M12 is coupled to the first output terminal of the Schmitt trigger 210 . An output terminal VON, the second pole of the twelfth transistor M12 is coupled to the second voltage terminal V2.

In the examples shown in FIG. 3 to FIG. 6 , the power supply voltage signal VDD is input from the first voltage terminal V1 , the second voltage terminal V2 is grounded, and the bias voltage VBIAS is input from the third voltage terminal V3 . The first transistor M1 , the fourth transistor M4 , the seventh transistor M7 , the eighth transistor M8 , the tenth transistor M10 and the twelfth transistor M12 are all NMOS transistors. The second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9 and the eleventh transistor M11 are all PMOS transistors. Those skilled in the art should understand that modifications to the circuits shown in FIGS. 3 to 6 based on the above inventive concepts should also fall within the protection scope of the present disclosure. In this variant, the aforementioned transistors and voltage terminals may also have a different arrangement than the examples shown in FIGS. 3 to 6 .

The working process of the NMOS low dropout linear regulator 300 according to the embodiment of the present disclosure will be described below with reference to the examples of FIGS. 3 to 6 .

FIG. 7 shows a schematic diagram of simulation waveforms of soft-start simulation performed by the NMOS low dropout linear regulator 300 according to an embodiment of the present disclosure. At time t1, when the power supply voltage is powered on and the start signal SS output by the output terminal of the soft start circuit 310 does not reach the preset voltage value, the first output terminal VON of the Schmitt trigger 210 outputs a low level , the second output terminal VOP of the Schmitt trigger 210 outputs a high level, the second transistor M2 is turned on, the third transistor M3 is turned off, and the gate terminal voltage V _{G_M4} of the fourth transistor M4 is a high level, Then the fourth transistor M4 is turned on, the first transistor M1 is short-circuited, the NMOS power transistor is turned off, and the output voltage VOUT is close to 0, as shown in the part marked by the dotted line in the waveform of the output voltage VOUT in FIG. 7 , That is, the "step" waveform of the output voltage VOUT is eliminated. At time t2, the soft start circuit 310 starts to work, the start signal SS output by its output end reaches the preset voltage value shown, the first output end VON of the Schmitt trigger 210 outputs a high level, and the Schmitt trigger 210 outputs a high level. The second output terminal VOP of the flip-flop 210 outputs a low level. Due to the presence of the second capacitor C2 and the fourth resistor R4, the gate terminal voltage V _{G_M4} and current I _M4 of the fourth transistor M4 drop slowly, and the fourth transistor M4 Gradually turn off, the first transistor M1 is connected to the circuit to start working, and the NMOS power transistor is slowly turned on, so that the output voltage VOUT of the NMOS low dropout linear regulator rises slowly to realize the function of soft start.

In summary, according to the NMOS low dropout linear voltage regulator of the embodiment of the present disclosure, the startup signal output by the soft-start circuit is used to control the on-off of the first transistor, thereby controlling the on-off of the NMOS power transistor, eliminating the need for soft-start Before the circuit is turned on, the output voltage of the NMOS low-dropout linear regulator fluctuates in a "step" shape to avoid affecting the normal operation of subsequent circuits.

The embodiment of the present disclosure also provides a chip. The chip includes an NMOS low dropout linear regulator according to an embodiment of the present disclosure. This chip is used, for example, in a power management chip.

The embodiment of the present disclosure also provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, a smart watch, an experimental device, a smart screen, and the like.

The flowcharts and block diagrams in the figures show the architecture, functions and operations of possible implementations of devices and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

Unless the context clearly dictates otherwise, as used herein and in the appended claims, the singular includes the plural and vice versa. Thus, when referring to the singular, the plural of the corresponding term will generally be included. Similarly, the words "comprise" and "include" are to be interpreted as being inclusive and not exclusive. Likewise, the terms "include" and "or" should be construed as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, said "example" is exemplary and explanatory only, and should not be considered to be exclusive or inclusive .

Further aspects and ranges of adaptations will become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A kind of NMOS low-dropout linear regulator, it is characterized in that, comprises: soft start circuit, switch control circuit, charge pump circuit, NMOS power tube, error amplifier, buffer stage, the first transistor, the first feedback resistance and the first Two feedback resistors, wherein the output end of the soft start circuit is coupled to the non-inverting input end of the error amplifier, the output end of the error amplifier is coupled to the input end of the buffer stage, and the output end of the buffer stage is coupled to connected to the first pole of the first transistor and the first node, the control pole of the first transistor is coupled to the second pole of the first transistor and the second node, and the switch control circuit is coupled to the first Between a node and the second node, the output terminal of the charge pump circuit is coupled to the control electrode of the NMOS power transistor and the second node, and the first pole of the NMOS power transistor is coupled to the NMOS The output terminal of the low dropout linear voltage regulator is connected to the first terminal of the first feedback resistor, the second pole of the NMOS power transistor is coupled to the first voltage terminal, and the second terminal of the first feedback resistor is coupled to the The first terminal of the second feedback resistor and the inverting input terminal of the error amplifier, the second terminal of the second feedback resistor is coupled to the second voltage terminal, Wherein, the charge pump circuit is used to generate a bias voltage, and provide the bias voltage to the control electrode of the NMOS power transistor through the second node; The soft start circuit is used to control the start signal to rise with the rise of the power supply voltage until reaching a preset voltage value after power-on, and provide the start signal to the switch control circuit; The switch control circuit is used to control the on-off of the first transistor by using the start-up signal, so as to control the on-off of the NMOS power transistor. 2. The NMOS low dropout linear voltage regulator according to claim 1, wherein the soft start circuit comprises: a first current source and a first capacitor, Wherein, the first terminal of the first current source is coupled to the first voltage terminal, and the second terminal of the first current source is coupled to the first terminal of the first capacitor and the output of the soft start circuit terminal, and the second terminal of the first capacitor is coupled to the second voltage terminal. 3. The NMOS low dropout linear voltage regulator according to claim 1, wherein the charge pump circuit comprises: a charge pump and a charge pump internal resistance, The output end of the charge pump is coupled to the first end of the internal resistance of the charge pump, and the second end of the internal resistance of the charge pump is coupled to the output end of the charge pump circuit. 4. The NMOS low dropout linear voltage regulator according to claim 1, wherein the switch control circuit comprises: a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, second capacitor and Schmitt trigger, Wherein, the control pole of the second transistor is coupled to the first output terminal of the Schmitt trigger, the first pole of the second transistor is coupled to the third voltage terminal, and the second pole of the second transistor coupled to the first end of the third resistor; The control pole of the third transistor is coupled to the second output terminal of the Schmitt trigger, the first pole of the third transistor is coupled to the first end of the third resistor, and the third transistor The second pole of is coupled to the second voltage terminal; the second end of the third resistor is coupled to the first end of the second capacitor; The control pole of the fourth transistor is coupled to the first terminal of the second capacitor, the first pole of the fourth transistor is coupled to the first terminal of the fourth resistor, and the second terminal of the fourth transistor pole coupled to the second node; The second end of the fourth resistor is coupled to the first node; The second end of the second capacitor is coupled to the second voltage end; The input end of the Schmitt trigger is coupled to the output end of the soft start circuit. 5. The NMOS low dropout linear voltage regulator according to claim 4, wherein the Schmitt trigger comprises: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a fifth resistor and a sixth resistor, Wherein, the control pole of the fifth transistor is coupled to the input terminal of the Schmitt trigger, the first pole of the fifth transistor is coupled to the first voltage terminal, and the second pole of the fifth transistor coupling the first pole of the sixth transistor and the first pole of the ninth transistor; The control pole of the sixth transistor is coupled to the input terminal of the Schmitt trigger, and the second pole of the sixth transistor is coupled to the first pole of the seventh transistor and the Schmitt trigger. second output terminal; The control electrode of the seventh transistor is coupled to the input terminal of the Schmitt trigger, and the second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor and the first electrode of the tenth transistor. pole; The control pole of the eighth transistor is coupled to the input terminal of the Schmitt trigger, and the second pole of the eighth transistor is coupled to the second voltage terminal; The control pole of the ninth transistor is coupled to the second output end of the Schmitt trigger, and the second pole of the ninth transistor is coupled to the first end of the sixth resistor; The control pole of the tenth transistor is coupled to the second output end of the Schmitt trigger, and the second pole of the tenth transistor is coupled to the first end of the fifth resistor; The second terminal of the fifth resistor is coupled to the first voltage terminal; The second end of the sixth resistor is coupled to the second voltage end; The control electrode of the eleventh transistor is coupled to the second output end of the Schmitt trigger, the first electrode of the eleventh transistor is coupled to the first voltage end, and the eleventh transistor the second pole is coupled to the first output terminal of the Schmitt trigger; The control electrode of the twelfth transistor is coupled to the second output end of the Schmitt trigger, and the first electrode of the twelfth transistor is coupled to the first output end of the Schmitt trigger. The second pole of the twelfth transistor is coupled to the second voltage end. 6. The NMOS low-dropout linear voltage regulator according to claim 5, wherein when the startup signal output by the output end of the soft-start circuit does not reach the preset voltage value, the Schmidt The output of the first output terminal of the special trigger is low level, and the output of the second output terminal of the Schmitt trigger is high level; when the start signal output by the output terminal of the soft start circuit reaches the When the voltage is preset, the output of the first output terminal of the Schmitt trigger is high level, and the output of the second output terminal of the Schmitt trigger is low level. 7. The NMOS low dropout linear voltage regulator according to claim 6, wherein when the first output terminal of the Schmitt trigger outputs a low level, the second output of the Schmitt trigger When the output terminal outputs a high level, the fourth transistor is turned on, the first transistor is short-circuited, and the NMOS power transistor is turned off. 8. The NMOS low dropout linear voltage regulator according to claim 6, wherein when the first output terminal of the Schmitt trigger outputs a high level, the second output of the Schmitt trigger When the output end is low level, the fourth transistor is turned off, the first transistor is connected to the circuit, and the NMOS power transistor is turned on. 9. A chip, characterized by comprising the NMOS low dropout linear voltage regulator according to any one of claims 1-8. 10. An electronic device, comprising the chip according to claim 9.

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