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CN116053306A - Gallium nitride-based high electron mobility transistor device and preparation method thereof - Google Patents

Gallium nitride-based high electron mobility transistor device and preparation method thereof Download PDF

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CN116053306A
CN116053306A CN202310098925.3A CN202310098925A CN116053306A CN 116053306 A CN116053306 A CN 116053306A CN 202310098925 A CN202310098925 A CN 202310098925A CN 116053306 A CN116053306 A CN 116053306A
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gan
substrate
electron mobility
high electron
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郭涛
吴畅
刘捷龙
李程程
王凯
吴佳燕
刘安
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Hubei Jiufengshan Laboratory
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • HELECTRICITY
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Abstract

The invention provides a gallium nitride-based high electron mobility transistor device and a preparation method thereof, wherein the gallium nitride-based high electron mobility transistor device comprises: epitaxial substrate, source electrode, drain electrode and grid electrode; the epitaxial substrate comprises a substrate layer, an m-GaN layer and epsilon-Ga 2 O 3 A layer, wherein the m-GaN layer is disposed on the substrate, epsilon-Ga 2 O 3 The layer is arranged on one side of the m-GaN layer, which is away from the substrate layer; the grid is arranged on epsilon-Ga 2 O 3 The layer is away from the side of the m-GaN layer, and the source electrode and the drain electrode are both arranged on the side of the m-GaN layer away from the substrate layer and are positioned on epsilon-Ga 2 O 3 Both ends of the layer. The high electron mobility transistor device passesDisposing an m-GaN layer and epsilon-Ga on a substrate 2 O 3 Layer formation of epsilon-Ga 2 O 3 m-GaN heterojunction in which ε -Ga 2 O 3 Compared with the prior art, the device has the advantages of large saturation current, low leakage current, and high stability and reliability.

Description

基于氮化镓的高电子迁移率晶体管器件及其制备方法GaN-based high electron mobility transistor device and its preparation method

技术领域technical field

本发明涉及半导体技术领域,具体涉及一种基于氮化镓的高电子迁移率晶体管器件及其制备方法。The invention relates to the technical field of semiconductors, in particular to a gallium nitride-based high electron mobility transistor device and a preparation method thereof.

背景技术Background technique

GaN(氮化镓)材料具有禁带宽度大、击穿场强高、高功率密度、迁移率高等特点,因此,基于GaN制备的HEMT(高电子迁移率晶体管器件)器件在高压和高频领域具有很大优势。基于GaN的HEMT一般采用异质结来诱导产生2DEG(二维电子气),通过氮化镓一侧的能带弯曲,将电子限制在势阱中,在源漏电极中间施加电场使电子获得横向高的迁移速度。目前,基于GaN的HEMT采用的异质结势垒材料一般为AlGaN(铝镓氮)、AlN(氮化铝)和InAlN(铟铝氮),其具有一定的缺陷,例如:GaN (gallium nitride) materials have the characteristics of large band gap, high breakdown field strength, high power density, and high mobility. has great advantages. GaN-based HEMTs generally use heterojunctions to induce 2DEG (two-dimensional electron gas). By bending the energy band on one side of gallium nitride, electrons are confined in the potential well, and an electric field is applied between the source and drain electrodes to enable electrons to obtain lateral direction. High migration speed. At present, the heterojunction barrier materials used in GaN-based HEMTs are generally AlGaN (aluminum gallium nitride), AlN (aluminum nitride) and InAlN (indium aluminum nitride), which have certain defects, such as:

第一、AlGaN作为势垒层,诱导的2DEG浓度不够高,无法满足更高功率的应用需求,若是通过提高Al组分来提高2DEG浓度,将会恶化AlGaN和GaN界面,增加电子散射的概率,降低迁移率;First, AlGaN is used as a barrier layer, and the induced 2DEG concentration is not high enough to meet the application requirements of higher power. If the 2DEG concentration is increased by increasing the Al composition, the interface between AlGaN and GaN will be deteriorated, and the probability of electron scattering will be increased. reduce mobility;

第二、AlN作为势垒层,虽然可以提高极化强度获得较大的2DEG浓度,但是AlN与GaN晶格失配较大,失配带来的应力问题会影响器件可靠性;Second, AlN is used as a barrier layer, although it can increase the polarization intensity to obtain a larger 2DEG concentration, but the lattice mismatch between AlN and GaN is large, and the stress problem caused by the mismatch will affect the reliability of the device;

第三、InAlN作为势垒层,可以获得比AlGaN更高的2DEG浓度,比AlN更大的电子迁移率,但是InAlN的击穿特性比较差,且In在工艺退火过程中存在析出迁移,导致势垒层退化。Third, InAlN, as a barrier layer, can obtain a higher 2DEG concentration than AlGaN, and a greater electron mobility than AlN, but the breakdown characteristics of InAlN are relatively poor, and In has precipitation migration during the annealing process, resulting in potential Barrier degradation.

因此,现有的高电子迁移率晶体管器件均存在一定的缺点,需要设计出一种新的基于氮化镓的高电子迁移率晶体管器件作为理想材料。Therefore, the existing high electron mobility transistor devices have certain shortcomings, and it is necessary to design a new gallium nitride-based high electron mobility transistor device as an ideal material.

发明内容Contents of the invention

基于上述表述,本发明提供了一种基于氮化镓的高电子迁移率晶体管器件及其制备方法,以解决现有技术中由于异质结势垒缺陷导致高电子迁移率晶体管器件导致性能不佳的技术问题。Based on the above statement, the present invention provides a GaN-based high electron mobility transistor device and its preparation method to solve the poor performance of the high electron mobility transistor device caused by heterojunction barrier defects in the prior art technical issues.

本发明解决上述技术问题的技术方案如下:The technical scheme that the present invention solves the problems of the technologies described above is as follows:

第一方面,本发明提供一种基于氮化镓的高电子迁移率晶体管器件,包括:外延衬底、源极、漏极及栅极;In a first aspect, the present invention provides a gallium nitride-based high electron mobility transistor device, comprising: an epitaxial substrate, a source, a drain, and a gate;

所述外延衬底包括衬底层、m-GaN层和ε-Ga2O3层,其中,所述m-GaN层设于所述衬底层上,所述ε-Ga2O3层设于所述m-GaN层背离所述衬底层的一侧;The epitaxial substrate includes a substrate layer, an m-GaN layer and an ε-Ga 2 O 3 layer, wherein the m-GaN layer is disposed on the substrate layer, and the ε-Ga 2 O 3 layer is disposed on the The side of the m-GaN layer away from the substrate layer;

所述栅极设于所述ε-Ga2O3层背离所述m-GaN层的一侧,所述源极和所述漏极均设于所述m-GaN层背离所述衬底层的一侧、且位于所述ε-Ga2O3层的两端。The gate is set on the side of the ε- Ga2O3 layer away from the m- GaN layer, the source and the drain are both set on the side of the m-GaN layer away from the substrate layer One side and two ends of the ε-Ga 2 O 3 layer.

在上述技术方案的基础上,本发明还可以做如下改进。On the basis of the above technical solutions, the present invention can also be improved as follows.

进一步地,所述ε-Ga2O3层的厚度为2~30nm。Further, the thickness of the ε-Ga 2 O 3 layer is 2-30 nm.

进一步地,所述外延衬底还包括第一钝化层;Further, the epitaxial substrate also includes a first passivation layer;

所述第一钝化层设于所述ε-Ga2O3层背离所述m-GaN层的一侧。The first passivation layer is disposed on a side of the ε-Ga 2 O 3 layer away from the m-GaN layer.

进一步地,所述栅极设于所述第一钝化层背离所述ε-Ga2O3层的一侧。Further, the gate is disposed on a side of the first passivation layer away from the ε-Ga 2 O 3 layer.

进一步地,所述第一钝化层设有刻蚀区,所述栅极穿过所述刻蚀区与所述Ga2O3层连接。Further, the first passivation layer is provided with an etching region, and the gate is connected to the Ga 2 O 3 layer through the etching region.

进一步地,所述栅极为T形栅。Further, the gate is a T-shaped gate.

进一步地,所述基于氮化镓的高电子迁移率晶体管器件还包括第二钝化层;Further, the gallium nitride-based high electron mobility transistor device also includes a second passivation layer;

所述第二钝化层盖设于所述外延衬底、所述源极、所述漏极和所述栅极的外表面。The second passivation layer covers the outer surfaces of the epitaxial substrate, the source, the drain and the gate.

第二方面,本发明还提供一种用于制备如第一方面中任一项所述的基于氮化镓的高电子迁移率晶体管器件的制备方法,包括:In the second aspect, the present invention also provides a method for preparing the gallium nitride-based high electron mobility transistor device according to any one of the first aspect, comprising:

在衬底层上依次沉积m-GaN和ε-Ga2O3,得到外延衬底;Deposit m-GaN and ε-Ga 2 O 3 sequentially on the substrate layer to obtain an epitaxial substrate;

在所述外延衬底的m-GaN层上沉积金属制作源极和漏极;depositing metal on the m-GaN layer of the epitaxial substrate to make source and drain;

在所述外延衬底的ε-Ga2O3层上沉积金属制作栅极。Metal is deposited on the ε-Ga 2 O 3 layer of the epitaxial substrate to make a gate.

在上述技术方案的基础上,本发明还可以做如下改进。On the basis of the above technical solutions, the present invention can also be improved as follows.

进一步地,在制作栅极之后,还包括:Further, after making the grid, it also includes:

对所述外延衬底、所述源极、所述漏极和所述栅极的外表面进行钝化处理。Passivation treatment is performed on the outer surfaces of the epitaxial substrate, the source, the drain and the gate.

与现有技术相比,本申请的技术方案具有以下有益技术效果:Compared with the prior art, the technical solution of the present application has the following beneficial technical effects:

本发明提供的基于氮化镓的高电子迁移率晶体管器件通过在衬底设置m-GaN层和ε-Ga2O3层形成ε-Ga2O3/m-GaN异质结,其中,ε-Ga2O3层为势垒层,相较于现有技术,该高电子迁移率晶体管器件具有如下优点:The gallium nitride-based high electron mobility transistor device provided by the present invention forms an ε-Ga 2 O 3 /m-GaN heterojunction by setting an m-GaN layer and an ε-Ga 2 O 3 layer on a substrate, wherein, ε -The Ga 2 O 3 layer is a potential barrier layer. Compared with the prior art, the high electron mobility transistor device has the following advantages:

第一、器件饱和电流大:由于势垒层ε-Ga2O3自发强度大,使得ε-Ga2O3/m-GaN异质结的界面处的2DEG浓度可以达到1014cm-2的量级,器件呈现出大的饱和电流,能够表现出更为优良的功率特性。First, the device saturation current is large: due to the high spontaneous strength of the barrier layer ε-Ga 2 O 3 , the 2DEG concentration at the interface of ε-Ga 2 O 3 /m-GaN heterojunction can reach 10 14 cm -2 On the order of magnitude, the device exhibits a large saturation current and can exhibit better power characteristics.

第二、器件漏电流低:ε-Ga2O3具有4.9eV的大禁带宽度,因此栅极通过势垒层隧穿漏电的概率下降,器件表现出低的漏电流水平。Second, the leakage current of the device is low: ε-Ga 2 O 3 has a large forbidden band width of 4.9eV, so the probability of tunneling leakage of the gate through the barrier layer is reduced, and the device exhibits a low level of leakage current.

第三、器件稳定性和可靠性高:由ε-Ga2O3和m-GaN的晶格常数非常接近,使得器件的异质结晶格失配小,器件的异质结应变更小,因此,该器件拥有更高的可靠性和稳定性。Third, the stability and reliability of the device are high: the lattice constants of ε-Ga 2 O 3 and m-GaN are very close, so that the heterogeneous crystal lattice mismatch of the device is small, and the heterojunction strain of the device is smaller, so , the device has higher reliability and stability.

附图说明Description of drawings

图1为本发明提供的基于氮化镓的高电子迁移率晶体管器件的结构示意图之一;Fig. 1 is one of the structural schematic diagrams of the gallium nitride-based high electron mobility transistor device provided by the present invention;

图2为本发明提供的基于氮化镓的高电子迁移率晶体管器件的结构示意图之二;Fig. 2 is the second structural schematic diagram of the gallium nitride-based high electron mobility transistor device provided by the present invention;

图3为本发明提供的外延衬底的结构示意图之一;Fig. 3 is one of the structural schematic diagrams of the epitaxial substrate provided by the present invention;

图4为本发明提供的外延衬底的结构示意图之二;Fig. 4 is the second structural schematic diagram of the epitaxial substrate provided by the present invention;

图5为本发明提供的基于氮化镓的高电子迁移率晶体管器件的部分结构示意图之一;Fig. 5 is one of the partial structural schematic diagrams of the gallium nitride-based high electron mobility transistor device provided by the present invention;

图6为本发明提供的基于氮化镓的高电子迁移率晶体管器件的部分结构示意图之二;FIG. 6 is the second partial structural schematic diagram of the GaN-based high electron mobility transistor device provided by the present invention;

图7为本发明实施例提供的基于氮化镓的高电子迁移率晶体管器件的制备方法示意图;FIG. 7 is a schematic diagram of a preparation method of a gallium nitride-based high electron mobility transistor device provided by an embodiment of the present invention;

图8为本发明提供的基于氮化镓的高电子迁移率晶体管器件的仿真数据效果图之一;Fig. 8 is one of the simulation data renderings of the gallium nitride-based high electron mobility transistor device provided by the present invention;

图9为本发明提供的基于氮化镓的高电子迁移率晶体管器件的仿真数据效果图之二;Fig. 9 is the second rendering of the simulation data of the gallium nitride-based high electron mobility transistor device provided by the present invention;

附图标记:Reference signs:

1、衬底层;2、m-GaN层;3、ε-Ga2O3层;4、第一钝化层;5、源极;6、漏极;7、栅极;8、第二钝化层。1. Substrate layer; 2. m-GaN layer; 3. ε-Ga 2 O 3 layer; 4. First passivation layer; 5. Source; 6. Drain; 7. Gate; 8. Second passivation layers.

具体实施方式Detailed ways

为了便于理解本申请,下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是,本申请可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使本申请的公开内容更加透彻全面。In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the application are given in the drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.

射频电路的前端芯片的制备主要使用的是CMOS(互补金属氧化物半导体晶体管器件)和SOI(绝缘体附着硅技术),然而,受限于本身工艺的耐受功率,芯片的有效发射功率较低,因此,同等距离的覆盖面积需要更大阵面的辐射,这导致了系统占据的幅面以及电路开发成本的提高;同时,更大的阵面对应着更窄的天线波束,为满足广域的用户覆盖需求,需要更加频繁和复杂的波束调度算法,增加了大量数字开销,影响了系统的有效频谱利用率。The preparation of the front-end chip of the radio frequency circuit mainly uses CMOS (complementary metal oxide semiconductor transistor device) and SOI (silicon on insulator technology). Therefore, the coverage of the same distance requires radiation from a larger front, which leads to an increase in the area occupied by the system and the cost of circuit development; at the same time, a larger front corresponds to a narrower antenna beam. User coverage requirements require more frequent and complex beam scheduling algorithms, which increases a large amount of digital overhead and affects the effective spectrum utilization of the system.

基于氮化镓制备的高电子迁移率晶体管器件能够解决这一问题,但是如前所述,现有的氮化镓制备的高电子迁移率晶体管器件均存在一定的缺陷,并非理想材料,因此,本发明实施例提供了一种新的基于氮化镓制备的高电子迁移率晶体管器件,该结构中的异质结具有晶格失配小和2DEG浓度高的优点,具体实施例如下。High electron mobility transistor devices based on gallium nitride can solve this problem, but as mentioned above, the existing high electron mobility transistor devices made of gallium nitride have certain defects and are not ideal materials. Therefore, The embodiment of the present invention provides a new high electron mobility transistor device based on gallium nitride. The heterojunction in this structure has the advantages of small lattice mismatch and high 2DEG concentration. The specific examples are as follows.

下面结合附图和实施例对本发明的实施方式作进一步详细描述,以下实施例用于说明本发明,但不能用来限制本发明的范围。The embodiments of the present invention will be described in further detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

第一方面,如图1所示,本发明实施例提供的基于氮化镓的高电子迁移率晶体管器件,包括:外延衬底、源极5、漏极6及栅极7。In the first aspect, as shown in FIG. 1 , the gallium nitride-based high electron mobility transistor device provided by the embodiment of the present invention includes: an epitaxial substrate, a source 5 , a drain 6 and a gate 7 .

外延衬底包括衬底层1、m-GaN层2和ε-Ga2O3层3,其中,m-GaN层2设于衬底层1上,ε-Ga2O3层3设于m-GaN层2背离衬底层1的一侧。The epitaxial substrate includes a substrate layer 1, an m-GaN layer 2 and an ε- Ga2O3 layer 3, wherein the m-GaN layer 2 is set on the substrate layer 1, and the ε- Ga2O3 layer 3 is set on the m-GaN Layer 2 is the side facing away from substrate layer 1 .

栅极7设于ε-Ga2O3层3背离GaN层2的一侧,源极5和漏极6均设于m-GaN层2背离衬底层1的一侧、且位于ε-Ga2O3层3的两端,源极5和漏极6间距为0.5~2um。The gate 7 is set on the side of the ε- Ga2O3 layer 3 away from the GaN layer 2, the source 5 and the drain 6 are both set on the side of the m-GaN layer 2 away from the substrate layer 1, and are located on the ε- Ga2 The distance between the source electrode 5 and the drain electrode 6 at both ends of the O 3 layer 3 is 0.5-2um.

具体地,此处的m-GaN是指具有m面的GaN,其是一种具有非极性面的GaN材料,研究表明该材料可以消除压电极化导致的氮化物器件辐射复合效率降低和发光波长蓝移等问题。Specifically, m-GaN here refers to GaN with an m-plane, which is a GaN material with a non-polar plane. Studies have shown that this material can eliminate the decrease in the radiative recombination efficiency of nitride devices caused by piezoelectric polarization and Issues such as blue shift of luminescence wavelength.

ε-Ga2O3是指具有ε晶相的Ga2O3,Ga2O3有多种晶系,此处优选六方晶系ε-Ga2O3,ε-Ga2O3禁带宽度大(4.9eV),器件栅极7电子的隧穿几率小,器件整体的漏电水平更小,具有较好的稳定性,因此,其作为势垒层,将能够避免出现势垒层退化的问题,确保器件性能的稳定性。ε-Ga 2 O 3 refers to Ga 2 O 3 with ε crystal phase. Ga 2 O 3 has many crystal systems, here the hexagonal system ε-Ga 2 O 3 is preferred, and the band gap of ε-Ga 2 O 3 Large (4.9eV), the tunneling probability of the device gate 7 electrons is small, the overall leakage level of the device is smaller, and it has better stability. Therefore, as a barrier layer, it will be able to avoid the problem of barrier layer degradation , to ensure the stability of device performance.

衬底层1采用蓝宝石、GaN、硅和碳化硅中的任意一种制备而成。其中,以硅为例,Si衬底层的晶向包括(100)、(111)和

Figure BDA0004072663360000061
以蓝宝石为例,蓝宝石衬底层晶向包括
Figure BDA0004072663360000062
和(0001);以碳化硅为例,碳化硅衬底层的晶向包括
Figure BDA0004072663360000063
Figure BDA0004072663360000064
碳化硅衬底层1的晶向包括(110)和(102)等。The substrate layer 1 is made of any one of sapphire, GaN, silicon and silicon carbide. Among them, taking silicon as an example, the crystal orientation of the Si substrate layer includes (100), (111) and
Figure BDA0004072663360000061
Taking sapphire as an example, the crystal orientation of the sapphire substrate layer includes
Figure BDA0004072663360000062
and (0001); taking silicon carbide as an example, the crystal orientation of the silicon carbide substrate layer includes
Figure BDA0004072663360000063
and
Figure BDA0004072663360000064
The crystal orientation of the silicon carbide substrate layer 1 includes (110) and (102) and the like.

此外,衬底层1可以为如图3所示的平整面衬底,衬底层1还可以设计为如图4所示的图形化衬底,对于其图形不作具体限定,依据实际需要进行设置即可。In addition, the substrate layer 1 can be a flat substrate as shown in FIG. 3, and the substrate layer 1 can also be designed as a patterned substrate as shown in FIG. 4. There is no specific limitation on its pattern, and it can be set according to actual needs. .

本发明实施例提供的基于氮化镓的高电子迁移率晶体管器件通过在衬底层1设置m-GaN层2和ε-Ga2O3层3形成ε-Ga2O3/m-GaN异质结,其中,ε-Ga2O3层3为势垒层,相较于现有技术,该高电子迁移率晶体管器件具有如下优点:器件饱和电流大:由于势垒层ε-Ga2O3自发强度大,使得ε-Ga2O3/m-GaN异质结的界面处的2DEG浓度可以达到1014cm-2的量级,器件呈现出大的饱和电流,能够表现出更为优良的功率特性;器件漏电流低:ε-Ga2O3具有4.9eV的大禁带宽度,因此栅极7通过势垒层隧穿漏电的概率下降,器件表现出低的漏电流水平;器件稳定性和可靠性高:由ε-Ga2O3和m-GaN的晶格常数非常接近,使得器件的异质结晶格失配小,器件的异质结应变更小,因此,该器件拥有更高的可靠性和稳定性。The gallium nitride-based high electron mobility transistor device provided by the embodiment of the present invention forms an ε-Ga 2 O 3 /m-GaN heterogeneous structure by setting an m-GaN layer 2 and an ε- Ga 2 O 3 layer 3 on a substrate layer 1 In which, the ε-Ga 2 O 3 layer 3 is a barrier layer. Compared with the prior art, the high electron mobility transistor device has the following advantages: the device saturation current is large: due to the barrier layer ε-Ga 2 O 3 The spontaneous intensity is large, so that the 2DEG concentration at the interface of the ε-Ga 2 O 3 /m-GaN heterojunction can reach the order of 10 14 cm -2 , the device presents a large saturation current, and can show more excellent Power characteristics; device leakage current is low: ε-Ga 2 O 3 has a large forbidden band width of 4.9eV, so the probability of gate 7 tunneling leakage through the barrier layer decreases, and the device exhibits a low leakage current level; device stability and high reliability: the lattice constants of ε-Ga 2 O 3 and m-GaN are very close, so that the heterogeneous crystal lattice mismatch of the device is small, and the heterojunction strain of the device is smaller. Therefore, the device has a higher reliability and stability.

进一步,在上述实施例的基础上,ε-Ga2O3层3的厚度为2~30nm。Further, on the basis of the above embodiments, the thickness of the ε-Ga 2 O 3 layer 3 is 2-30 nm.

具体地,由于ε-Ga2O3自发强度大,使用ε-Ga2O3/m-GaN异质结的界面处的2DEG浓度可以达到1014cm-2的量级,器件呈现出大的饱和电流,表现出优良的功率特性。Specifically, due to the large spontaneous intensity of ε-Ga 2 O 3 , the 2DEG concentration at the interface using ε-Ga 2 O 3 /m-GaN heterojunction can reach the order of 10 14 cm -2 , and the device exhibits a large saturation current, showing excellent power characteristics.

进一步,在上述实施例的基础上,如图3所示,外延衬底还包括第一钝化层4。Further, on the basis of the above embodiments, as shown in FIG. 3 , the epitaxial substrate further includes a first passivation layer 4 .

第一钝化层4设于ε-Ga2O3层3背离m-GaN层2的一侧。The first passivation layer 4 is disposed on the side of the ε-Ga 2 O 3 layer 3 away from the m-GaN layer 2 .

如图1所示,栅极7设于第一钝化层4背离ε-Ga2O3层3的一侧。As shown in FIG. 1 , the gate 7 is disposed on the side of the first passivation layer 4 away from the ε-Ga 2 O 3 layer 3 .

进一步,在上述实施例的基础上,如图1所示,第一钝化层4设有刻蚀区,栅极7穿过刻蚀区与ε-Ga2O3层3连接。Further, on the basis of the above embodiments, as shown in FIG. 1 , the first passivation layer 4 is provided with an etching region, and the gate 7 is connected to the ε-Ga 2 O 3 layer 3 through the etching region.

在实际操作中,栅极7与外延衬底的连接有以下三种方式:In actual operation, the gate 7 is connected to the epitaxial substrate in the following three ways:

第一种、外延衬底无第一钝化层4,栅极7直接与ε-Ga2O3层3的上表面连接;In the first type, the epitaxial substrate has no first passivation layer 4, and the gate 7 is directly connected to the upper surface of the ε- Ga2O3 layer 3;

第二种、外延衬底设有第一钝化层4,栅极7与第一钝化层4的上表面连接;In the second type, the epitaxial substrate is provided with a first passivation layer 4, and the gate 7 is connected to the upper surface of the first passivation layer 4;

第三种、外延衬底设有第一钝化层4,第一钝化层4上设有刻蚀区,栅极7穿设于该刻蚀区与ε-Ga2O3层3的上表面连接。The third type is that the epitaxial substrate is provided with a first passivation layer 4, and an etching area is provided on the first passivation layer 4, and the gate 7 is provided on the etching area and the ε- Ga2O3 layer 3 surface connection.

需要说明的是,第一钝化层4的材质为GaN或SiN,其作用是用来保护ε-Ga2O3It should be noted that the material of the first passivation layer 4 is GaN or SiN, and its function is to protect ε-Ga 2 O 3 .

在可选的实施例中,如图1所示,栅极7为T形栅,栅长为20~100nm,具体长度依据实际需要进行设置即可。In an optional embodiment, as shown in FIG. 1 , the gate 7 is a T-shaped gate with a gate length of 20-100 nm, and the specific length can be set according to actual needs.

进一步,在上述实施例的基础上,为了实现对整个器件的保护,如图2所示,基于氮化镓的高电子迁移率晶体管器件还包括第二钝化层8。Further, on the basis of the above embodiments, in order to protect the entire device, as shown in FIG. 2 , the gallium nitride-based high electron mobility transistor device further includes a second passivation layer 8 .

第二钝化层8盖设于外延衬底、源极5、漏极6和栅极7的外表面。The second passivation layer 8 covers the outer surfaces of the epitaxial substrate, the source 5 , the drain 6 and the gate 7 .

第二方面,如图7所示,本发明实施例还提供了一种用于制备如第一方面中任一项的基于氮化镓的高电子迁移率晶体管器件的制备方法,包括:In the second aspect, as shown in FIG. 7 , an embodiment of the present invention also provides a method for preparing a gallium nitride-based high electron mobility transistor device according to any one of the first aspect, including:

步骤S1:在衬底层1上依次沉积m-GaN和ε-Ga2O3,得到外延衬底;Step S1: sequentially depositing m-GaN and ε-Ga 2 O 3 on the substrate layer 1 to obtain an epitaxial substrate;

步骤S2:在外延衬底的m-GaN层2上沉积金属制作源极5和漏极6;Step S2: Depositing metal on the m-GaN layer 2 of the epitaxial substrate to form the source 5 and the drain 6;

步骤S3:在外延衬底的ε-Ga2O3层3上沉积金属制作栅极7。Step S3: Deposit metal on the ε-Ga 2 O 3 layer 3 of the epitaxial substrate to make the gate 7 .

进一步,在制作栅极7之后,还包括:Further, after making the gate 7, it also includes:

对外延衬底、源极5、漏极6和栅极7的外表面进行钝化处理。The outer surfaces of the epitaxial substrate, the source 5 , the drain 6 and the gate 7 are passivated.

具体地,在步骤S1中,首先,制备衬底层1,衬底层1可以为硅衬底、蓝宝石衬底和碳化硅衬底中的一种,此处可选择蓝宝石衬底为例进行介绍;然后在蓝宝石衬底的上表面生长m-GaN,进一步在m-GaN的m面生长ε-Ga2O3作为势垒层,得到异质结构为ε-Ga2O3/m-GaN。Specifically, in step S1, first, a substrate layer 1 is prepared, and the substrate layer 1 can be one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate, and a sapphire substrate can be selected as an example for introduction here; then The m-GaN is grown on the upper surface of the sapphire substrate, and ε-Ga 2 O 3 is further grown on the m-plane of the m-GaN as a barrier layer to obtain a heterostructure of ε-Ga 2 O 3 /m-GaN.

可根据实际需要选择性的在ε-Ga2O3上表面沉积钝化层,对势垒层进行保护。A passivation layer can be selectively deposited on the surface of ε-Ga 2 O 3 according to actual needs to protect the barrier layer.

在步骤S2中,电极的制备有如下两种实现方式:In step S2, the preparation of the electrode has the following two implementation methods:

方式一、源漏再生长法:使用干法在ε-Ga2O3层3和m-GaN层2上刻蚀出源漏再生长区域,刻蚀气体为BCl3和Cl2,刻蚀深度30~100nm;刻蚀完成后,使用有机化学气相沉积法(MOCVD)或者分子束外延法(MBE)在源漏刻蚀区域再生长高掺杂的GaN,掺杂浓度大于1019cm-3,生长厚度为30~100nm。使用光刻揭开一剥离(lift-off)工艺形成GaN电极,在该电极上利用电子束蒸发源漏金属Ti/Pt/Au,使其沉积形成源漏电极,其总厚度为0.1~0.5um,得到的结构如图5所示。Method 1. Source-drain regrowth method: use a dry method to etch the source-drain regrowth region on the ε-Ga 2 O 3 layer 3 and the m-GaN layer 2. The etching gas is BCl 3 and Cl 2 , and the etching depth is 30-100nm; After the etching is completed, use organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) to re-grow highly doped GaN in the source and drain etching regions, the doping concentration is greater than 10 19 cm -3 , and the growth The thickness is 30-100nm. Use photolithography to uncover a lift-off (lift-off) process to form a GaN electrode, use an electron beam to evaporate the source and drain metal Ti/Pt/Au on the electrode, and deposit it to form a source and drain electrode with a total thickness of 0.1-0.5um , the resulting structure is shown in Figure 5.

方式二、合金退火法:使用光刻技术在m-GaN层2上限定出源漏欧姆金属区域,在该区域沉积金属Ti/Al/Ni/Au,对应的厚度分别可以为10/160/55/45nm,进行退火处理,退火温度为830℃,退火氛围为氮气,退火时间50S,得到的结构如图6所示。Method 2. Alloy annealing method: use photolithography to define the source and drain ohmic metal regions on the m-GaN layer 2, and deposit metal Ti/Al/Ni/Au in this region, and the corresponding thicknesses can be 10/160/55 /45nm, annealing treatment was performed, the annealing temperature was 830°C, the annealing atmosphere was nitrogen, and the annealing time was 50S. The obtained structure is shown in Figure 6.

在步骤S3中,对合金退火得到结构,使用光刻和lift-off工艺在ε-Ga2O3上表面形成GaN HEMT栅极7电极形状,然后电子束蒸发T形栅金属Ni、Pt或Au,总厚度为0.4~0.8um,栅足长度为20~100nm,得到的结构如图1所示。In step S3, anneal the alloy to obtain the structure, use photolithography and lift-off process to form GaN HEMT grid 7 electrode shapes on the upper surface of ε-Ga 2 O 3 , and then electron beam evaporate T-shaped grid metal Ni, Pt or Au , the total thickness is 0.4 ~ 0.8um, the gate foot length is 20 ~ 100nm, the resulting structure is shown in Figure 1.

最后,为了保护整个器件,在制备得到HEMT器件的外表面沉积第二钝化层8,使用等离子增强气相沉积法(PECVD)生长SiNx钝化保护层,其厚度为1~3um,得到的结构如图2所示。Finally, in order to protect the entire device, the second passivation layer 8 is deposited on the outer surface of the prepared HEMT device, and the SiNx passivation protection layer is grown by plasma enhanced vapor deposition (PECVD), and its thickness is 1-3um. The obtained structure is as follows Figure 2 shows.

通过仿真将本发明实施例提供的异质结构为ε-Ga2O3/m-GaN的HEMT器件与该器件结构相同、异质结为AlN/GaN的HEMT器件的性能进行对比,结果如图8和图9所示,可以看出,本发明实施例提供的HEMT器件具有更大的饱和电流,比采用AlN势垒层的HEMT器件大了一倍以上;而且,本发明提供的HEMT器件表现出低的漏电流水平,这得益于ε-Ga2O3接近5eV的大禁带宽度,栅极7通过势垒层隧穿漏电的概率下降。因此,本发明实施例提供的基于氮化镓的高电子迁移率晶体管器件相较于现有技术,具有更好的电学特性。Through simulation, the performance of the HEMT device with the heterostructure of ε-Ga 2 O 3 /m-GaN provided by the embodiment of the present invention is compared with the performance of the HEMT device with the same structure of the device and the heterojunction is AlN/GaN, and the results are shown in the figure 8 and 9, it can be seen that the HEMT device provided by the embodiment of the present invention has a larger saturation current, which is more than double that of the HEMT device using an AlN barrier layer; and the HEMT device provided by the present invention exhibits A low level of leakage current is achieved, thanks to the large forbidden band width of ε-Ga 2 O 3 close to 5eV, and the probability of tunneling leakage of the gate 7 through the barrier layer is reduced. Therefore, compared with the prior art, the high electron mobility transistor device based on gallium nitride provided by the embodiment of the present invention has better electrical characteristics.

在本说明书的描述中,参考术语“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明实施例的至少一个实施例或示例中。在本说明书中,描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外,在不相互矛盾的情况下,本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。In the description of this specification, descriptions with reference to the terms "specific examples" or "some examples" mean that specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment of the embodiments of the present invention or example. In this specification, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

最后应说明的是:以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (9)

1. A gallium nitride-based high electron mobility transistor device, comprising: epitaxial substrate, source electrode, drain electrode and grid electrode;
the epitaxial substrate comprises a substrate layer, an m-GaN layer and epsilon-Ga 2 O 3 A layer, wherein the m-GaN layer is arranged on the substrate layer, and the epsilon-Ga 2 O 3 The layer is arranged on one side of the m-GaN layer, which is away from the substrate layer;
the grid electrode is arranged on the epsilon-Ga 2 O 3 The layer is away from one side of the m-GaN layer, the source electrode and the drain electrode are both arranged on one side of the m-GaN layer away from the substrate layer and are positioned on the epsilon-Ga 2 O 3 Both ends of the layer.
2. Gallium nitride-based high electron mobility transistor device according to claim 1, wherein the epsilon-Ga 2 O 3 The thickness of the layer is 2-30 nm.
3. The gallium nitride-based high electron mobility transistor device of claim 1, wherein the epitaxial substrate further comprises a first passivation layer;
the first passivation layer is arranged on the epsilon-Ga 2 O 3 The side of the layer facing away from the m-GaN layer.
4. A gallium nitride-based high electron mobility transistor device according to claim 3, wherein said gate is disposed on said first passivation layer facing away from said epsilon-Ga 2 O 3 One side of the layer.
5. A gallium nitride-based high electron mobility transistor device according to claim 3, wherein the first passivation layer is provided with an etched region through which the gate passes with the epsilon-Ga 2 O 3 The layers are connected.
6. The gallium nitride-based high electron mobility transistor device of claim 1, wherein the gate is a T-gate.
7. The gallium nitride based high electron mobility transistor device of claim 1, further comprising a second passivation layer;
the second passivation layer covers the outer surfaces of the epitaxial substrate, the source electrode, the drain electrode and the grid electrode.
8. A method for preparing the gallium nitride-based high electron mobility transistor device of any of claims 1 to 7, comprising:
sequentially depositing m-GaN and epsilon-Ga on a substrate layer 2 O 3 Obtaining an epitaxial substrate;
depositing metal on the m-GaN layer of the epitaxial substrate to manufacture a source electrode and a drain electrode;
epsilon-Ga on said epitaxial substrate 2 O 3 And depositing metal on the layer to manufacture the grid electrode.
9. The method of manufacturing of claim 8, further comprising, after the gate is manufactured:
and passivating the outer surfaces of the epitaxial substrate, the source electrode, the drain electrode and the grid electrode.
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