CN116015305A - Low-power consumption single-slope ADC circuit based on clock locking - Google Patents

Abstract

The invention provides a low-power consumption single-slope ADC circuit based on clock locking, and belongs to the field of analog integrated circuits. Comprising the following steps: the device comprises a ramp generating circuit, a sampling hold circuit, a comparator, three registers, an inverter and a switch. Input signal V _PIXEL As the non-inverting input of the comparator, V _RAMP As an inverting input of the comparator. Based on the basic properties of the comparator, if the input signal V _PIXEL Greater than V _RAMP The output V of the comparator _{COMP_out} Is at a high level; if input signal V _PIXEL Less than the comparison signal, the output V of the comparator _{COMP_out} Is low. The invention adopts a dichotomy mode to determine the range corresponding to the input voltage, shortens and locks the working interval of the counter, reduces the switching power consumption of the counter, and further reduces the power consumption of the single-slope ADC.

Description

A low power single slope ADC circuit based on clock locking

Technical Field

The invention relates to the field of analog integrated circuits, and in particular to the design of a low-power single-slope ADC circuit for a CMOS image sensor.

Background Art

Image sensors are sensor elements that use the photoelectric conversion function of photoelectric devices to convert light signals into electrical signals and finally process them into image information. With the continuous improvement of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) processes and technologies, CMOS image sensors have low cost, high integration, low power consumption, and high speed, making them account for an increasing proportion in the market. CMOS image sensors are mainly composed of row control circuits, pixel arrays, PGA (Programmable Gain Amplifier), ADC circuits, and LVDS (Low Voltage Differential Signaling) circuits. After the pixel signal of the image sensor is output from the pixel array, it will be transmitted to the PGA and then to the storage. At this time, the analog signal of the pixel is stored in the storage. The analog signal will then be transmitted to the ADC circuit for processing and converted into a digital signal. Because the pixel signal in the image sensor is read out column by column, the image sensor has strict requirements on the area of the readout circuit. Since the single slope ADC (Analog to Digital Converter) has the advantages of simple structure and small area, the single slope ADC is currently widely used in CMOS image sensors. In CMOS image sensor systems, low power consumption design is an extremely important aspect of system design. On the one hand, low power consumption plays a very important role in the portability of the device and the service life of the battery. On the other hand, the use of low power consumption design can reduce costs. There are two main sources of power consumption. On the one hand, when a logic flip occurs, the flip power consumption caused by the charging and discharging of the load capacitor. On the other hand, when the series-parallel structure of the PMOS and NMOS tubes are both turned on, a short-circuit current will be generated, which is called short-circuit power consumption. The traditional single-slope ADC has a large flip power consumption because the counter is always counting during the quantization process and the logic will continuously flip. In order to reduce the power consumption of the single-slope ADC, the present invention proposes a new structure, namely a low-power ADC circuit based on clock locking, which greatly reduces the flip power consumption caused by the counter flip.

Summary of the invention

The present invention solves the problem of high power consumption of single slope ADC and proposes a low power consumption two-step single slope ADC circuit structure based on clock locking. For the traditional N-bit single slope ADC, the specific structure includes a sampling and holding circuit, a comparator, a counter, a register, and a slope generating circuit. The present invention not only retains the advantages of the traditional single slope ADC with simple structure and small area, but also solves the problem of high power consumption, which is of great engineering significance.

The working process of the traditional single slope ADC is as follows: the sampling and holding circuit samples the pixel signal V _PIXEL from the pixel array onto the holding capacitor and outputs it to the in-phase terminal of the comparator. The ramp generating circuit generates a ramp signal V _RAMP and connects it to the inverting terminal of the comparator. The ramp signal V _RAMP is compared with the input signal V _PIXEL through the comparator. The voltage of the ramp signal V _RAMP is less than the input signal V _PIXEL . The counter keeps counting according to the clock cycle. As the voltage of the ramp signal V _RAMP keeps increasing, when the voltage of the ramp signal V _RAMP is greater than the input signal V _PIXEL , the comparator output jumps, the counter stops counting, and the quantization result is stored in the register. If the value of V _PIXEL is large, the counter will also extend the counting time accordingly. However, the flip power consumption will be increased during the counting process of the counter, that is, the longer the counting process of the counter lasts, the greater the flip power consumption will be. Therefore, the flip of the counter is the main power consumption source of the single slope ADC. In order to reduce the power consumption of the single slope ADC, it is necessary to reduce the working time of the counter and partially lock the counter. The present invention aims to propose a solution for partially locking a counter, and proposes a low-power single-slope ADC structure based on count locking.

The technical solution of the present invention is as follows:

A low-power single-slope ADC circuit based on clock locking comprises: a slope generating circuit, a sampling and holding circuit, a comparator, three registers, an inverter and a switch. The sampling and holding circuit is used to store the output signal of the pixel, and is connected to the non-phase end of the comparator. The pixel output signal stored in the sampling and holding circuit is used as the non-phase input signal of the comparator. The slope generating circuit is connected to the inverting end of the comparator, and a switch S _RAMP is arranged between them. The slope voltage generated by the slope generating circuit is used as the inverting input signal of the comparator. The switch _SM is connected to the inverting end of the comparator, and the other ends of the two switches _SS and _SL under the switch _SM are connected to _VS and _VL respectively. The _VS and _VL are the outputs of the inverter. The output end of the comparator is connected to the three registers respectively, and the order from top to bottom is SRAM2, SRAM1, and SRAM3. The registers are used to store the output signal of the comparator. There is a switch _S1 between the comparator and the register SRAM1, and the right end of SRAM1 is connected to switches _S2 and _S4 respectively, and the right ends of _S2 and _S4 are connected to two inverters connected in series. There is a switch _S3 between the comparator and the register SRAM2, and the right end of SRAM2 is connected to two inverters connected in series. There is a switch Swrite between the comparator and the register SRAM3. The right end of SRAM3 is connected to a counter and a register in sequence. The output of the inverter is used to control the generation of a lock signal. The counting state of the counter is controlled by Vctrl, that is, when Vctrl is at a high level, the counter starts counting, and when Vctrl is at a low level, the counter stops counting. The Vctrl is connected to the output of a NAND gate, and the input of the NAND gate is the output signal Vcomp_out of the comparator and the counter lock signal LOCK_OUT.

Furthermore, the comparator is used to compare the size of the input signal. If the in-phase input signal is greater than the inverting input signal, the comparator outputs a high level. On the contrary, if the in-phase input signal is less than the inverting input signal, the comparator outputs a low level. As described above, the in-phase input signal of the comparator is a pixel output signal, which is a fixed level. The inverting input signal of the comparator is a ramp signal or a _VM signal, which is determined by the switch-off condition. If S _Ramp is closed and _SM is disconnected, the inverting input signal of the comparator is V _ramp , that is, a ramp voltage with a fixed slope but a variable voltage value. If S _Ramp is disconnected and _SM is closed, the inverting input signal of the comparator is _VM . Similarly, if _SS is closed, Vs is selected. If _SL is closed, _VL is selected. The Vs and _VL are the outputs of the inverter connected to the right end of SRAM1.

Furthermore, the ramp signal is divided into four parts, namely LOCK1, LOCK2, LOCK3, and LOCK4. The division is as follows: LOCK1 does not trigger the lock signal, LOCK2 locks 0-1/4V _ramp , LOCK3 locks 0-2/4V _ramp , and LOCK4 locks 0-3/4V _ramp . The LOCK_OUT signal is one of LOCK1, LOCK2, LOCK3, and LOCK4, which is specifically controlled by the switch off. The control signal of the switch is controlled by the output signal of the inverter.

Furthermore, the LOCK_OUT signal is used as the input of the NAND gate and the output of the comparator to control the counting state of the counter. The counter is formed by a D flip-flop, and the formation principle is to continuously use the output of the previous stage as the CLK input of the next stage, thereby realizing step-by-step frequency division to achieve counting.

Beneficial effects of the present invention: The present invention reduces the use frequency of the high-speed clock as much as possible by refining the counting interval, thereby reducing the switching power consumption caused by the frequent triggering of the D flip-flop in the counter caused by the use of the high-speed clock.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic diagram of a traditional single-slope ADC.

Figure 2 is a schematic diagram of a low-power single-slope ADC based on count lock.

The meanings of the switch and voltage of the present invention are respectively:

S _S controls the switch of low potential; S _M controls the switch of medium potential; S _L controls the switch of high potential; S ₁ controls the switch of the first stage comparison; S ₂ sends the first stage comparison result to the switch of the inverter input; Vs is a smaller potential; V _L is a larger potential; V ₁₂ is a 1 2 level potential; V ₃₄ is a 3 4 level potential; S ₃ controls the switch for secondary comparison with a smaller or larger potential; S4 is used to control the switch for further refinement of the smaller or larger voltage range; S _RAMP is used to control the switch of the ramp signal; Vctrl is used to control the logic signal of the switch state of the M tube; Swrite is used to control the switch of the counter count value writing into the SRAM:

The principle diagram of the present invention is shown in Figure 2. The present invention mainly consists of two parts, including a counter front-end locking function signal LOCK_OUT generating circuit composed of a comparator COMP, a switch, an inverter, an SRAM, etc., and a counter back-end locking function circuit composed of a DFF, a flip control switch M, and a NAND gate. The front-end locking means that the counting stage corresponding to the voltage less than the input signal is stopped. The back-end locking means that the counting stage after the top of the ramp signal is stopped. By locking the counter, the counter is only flipped at the ramp signal near the input signal, which greatly reduces the switch power consumption caused by the counter flipping.

FIG3 is a switching timing diagram of the LOCK_OUT clock front-end locking signal, which is used to determine which LOCK to use according to the specific size of V _PIXEL .

FIG4 is a detailed expansion diagram of the LOCK signal. By using the binary method, the counter processing range is refined to generate four LOCKs that can be used by V _PIXELs with different input ranges, thereby achieving counter front-end locking.

FIG5 is a diagram illustrating an example.

DETAILED DESCRIPTION

The input signal V _PIXEL is used as the non-inverting input terminal of the comparator, and V _RAMP is used as the inverting input terminal of the comparator. According to the basic properties of the comparator, if the input signal V _PIXEL is greater than V _RAMP , the output V _{COMP_out} of the comparator is high level; if the input signal V _PIXEL is less than the comparison signal, the output V _{COMP out} of the comparator is low level. The present invention adopts a binary method to determine the range corresponding to the input voltage, shorten and lock the working range of the counter, reduce the switching power consumption of the counter, and further reduce the power consumption of the single slope ADC.

The specific implementation method is divided into the following steps:

The first step is to divide the input voltage into a preliminary range. Switches S _M , S ₁ , and S ₂ are closed, and the other switches are turned off. The input signal V _PIXEL is compared with V _M to determine whether the range of V _PIXEL is greater than or less than V _M. The output result of the comparator is stored in SRAM1. If the input signal V _PIXEL is less than V _M , the comparator outputs a low level, _{V S is} a high level, the switch Ss is closed, and the input signal V _PIXEL should continue to be compared with V _S ; if the input signal V _PIXEL is greater than V _M , the comparator outputs a high level, V _L is a high level, the switch S _L is closed, and the input signal V _PIXEL should continue to be compared with V _L.

The second step is to further subdivide the voltage range corresponding to the input voltage V _PIXEL . If the input signal V _PIXEL is less than V _M , the switches S _S and S ₃ are closed, and the other switches are turned off. The input signal V _PIXEL is compared with VS to determine whether the range of V _PIXEL should be greater than VS or less than VS. The output result is stored in SRAM2. If the input signal V _PIXEL is less than _VS , Vlow is high level, and the input signal V _PIXEL corresponds to LOCK1. If the input signal V _PIXEL is greater than _VS , Vupper is high level, and the input signal V _PIXEL corresponds to LOCK2. If the input signal V _PIXEL is greater than V _M , switches S _L , S ₃ are closed, and the other switches are turned off. The input signal V _PIXEL is compared with V _L to determine whether the range of the input signal V _PIXEL should be greater than V _L or less than V _L . If the input signal V _PIXEL is less than V _L , Vlow is at a high level, and the input signal V _PIXEL corresponds to LOCK3 . If the input signal VIN1 is greater than V _L , Vupper is at a high level, and the input signal V _PIXEL corresponds to LOCK4 .

In the third step, switch _S4 is closed and the other switches are turned off. The output signal of the comparator stored in SRAM1 can be used to determine the level of _V12 and _V34 . If _VPIXEL is greater than _VM , _V34 is high, and LOCK3 or LOCK4 is selected and output as LOCK_OUT. If _VPIXEL is less than _VM , _V12 is high, and LOCK1 or LOCK2 is selected and output as LOCK_OUT.

In the fourth step, switches S _RAMP and S _write are closed, and the other switches are turned off. At this time, the working process of the traditional single slope ADC is realized, the ramp signal V _RAMP is input, and the input signal V _PIXEL is compared with the ramp signal V _RAMP and output.

与时钟锁定信号LOCK_OUT，该与非门产生的输出信号Vctrl用于控制M管的关断与导通状态，M管的源极接在DFF(D Flip-flop)输入端D上，漏极接在DFF的输出反向端QN上。若控制信号Vctrl为高电平，则M导通，若控制信号Vctrl为低电平，则M关断。当与非门的输入信号均为高电平时，输出低电平，M管关断，计数器停止计数。当与非门的输入信号不均为高电平时，输出高电平，M管导通，计数器继续计数。The counter is composed of a D flip-flop as shown in Figure 1. The input signal of the two-input NAND gate is the inversion signal of the comparator output signal.

The output signal Vctrl generated by the NAND gate is used to control the on and off state of the M tube, and the source of the M tube is connected to the DFF (D Flip-flop) input terminal D, and the drain is connected to the output reverse terminal QN of the DFF. If the control signal Vctrl is high, the M tube is turned on, and if the control signal Vctrl is low, the M tube is turned off. When the input signals of the NAND gate are all high, the output is low, the M tube is turned off, and the counter stops counting. When the input signals of the NAND gate are not all high, the output is high, the M tube is turned on, and the counter continues counting.

相组合，得到输出信号V_ctrl，由图5所示，计数器只有在V_ctrl为高电平时才会计数，有效计数时间大大降低，由此可见，基于时钟锁定的单斜坡ADC实现了时钟锁定的功能，有效的减小了由于计数器开关所引起的功耗，本发明在降低功耗方面有着较为重要的作用。Take Figure 5 as an example. If the input signal is between 2/4V and 3/4V, the lock signal should correspond to LOCK3.

5, the counter will count only when V _ctrl is at a high level, and the effective counting time is greatly reduced. It can be seen that the single slope ADC based on clock _locking realizes the function of clock locking and effectively reduces the power consumption caused by the counter switch. The present invention plays an important role in reducing power consumption.

Claims (4)

1. A low-power single-slope ADC circuit based on clock locking, characterized in that it includes a ramp generating circuit, a sampling and holding circuit, a comparator, three registers, an inverter and a switch; the sampling and holding circuit is used to store the output signal of the pixel, and is connected to the non-inverting end of the comparator, and the pixel output signal stored in it is used as the non-inverting input signal of the comparator; the ramp generating circuit is connected to the inverting end of the comparator, and a switch S _RAMP is arranged between them, and the ramp voltage generated by the ramp generating circuit is used as the inverting input signal of the comparator; the switch _SM is connected to the inverting end of the comparator, and the other ends of the two switches _SS and _SL under the switch _SM are connected to _VS and _VL respectively, and the _VS and _VL are the outputs of the inverter; the output end of the comparator is connected to the three registers respectively, and the order from top to bottom is SRAM2, SRAM1, and SRAM3, and the registers are used to store the output signal of the comparator; there is a switch _S1 between the comparator and the register SRAM1, and the right end of SRAM1 is connected to switches _S2 and _S4 respectively, _S2 , S ₄ is connected to two inverters in series; there is a switch _S3 between the comparator and the register SRAM2, and the right end of SRAM2 is connected to two inverters in series; there is a switch Swrite between the comparator and the register SRAM3; the right end of SRAM3 is connected to the counter and the register in sequence; the output of the inverter is used to control the generation of the lock signal; the counting state of the counter is controlled by Vctrl, that is, when Vctrl is at a high level, the counter starts counting, and when Vctrl is at a low level, the counter stops counting; the Vctrl is connected to the output of the NAND gate, and the input of the NAND gate is the output signal Vcomp_out of the comparator and the counter lock signal LOCK_OUT. 2. A low-power single-slope ADC circuit based on clock locking according to claim 1, characterized in that the comparator is used to compare the size of the input signal, if the in-phase input signal is greater than the inverting input signal, the comparator outputs a high level; on the contrary, if the in-phase input signal is less than the inverting input signal, the comparator outputs a low level; the in-phase input signal of the comparator is a pixel output signal, which is a fixed level; the inverting input signal of the comparator is a ramp signal or a _VM signal, which is determined by the switch-off condition; if S _Ramp is closed and _SM is disconnected, the inverting input signal of the comparator is V _ramp , that is, a ramp voltage with a fixed slope but a variable voltage value; if S _Ramp is disconnected and _SM is closed, the inverting input signal of the comparator is _VM , similarly, if _SS is closed, Vs is selected; if _SL is closed, _VL is selected; Vs and _VL are the outputs of the inverter connected to the right end of SRAM1. 3. A low-power single-slope ADC circuit based on clock locking according to claim 1, characterized in that the ramp signal is divided into 4 parts, namely LOCK1, LOCK2, LOCK3, and LOCK4; the division is as follows: LOCK1 does not trigger the locking signal, LOCK2 locks 0~1/4V _ramp , LOCK3 locks 0~2/4V _ramp , and LOCK4 locks 0~3/4V _ramp , and the LOCK_OUT signal is one of LOCK1, LOCK2, LOCK3, and LOCK4, which is specifically controlled by the turning off of the switch; the control signal of the switch is controlled by the output signal of the inverter. 4. A low-power single-slope ADC circuit based on clock locking according to claim 1, characterized in that the LOCK_OUT signal is used as the input of the NAND gate, and together with the output of the comparator, controls the counting state of the counter; the counter is formed by a D flip-flop, and continuously uses the output of the previous stage as the CLK input of the next stage, thereby realizing step-by-step frequency division to achieve counting.

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