CN115985981B - Solar cell, preparation method thereof and photovoltaic module - Google Patents

Abstract

The application relates to a solar cell, a preparation method thereof and a photovoltaic module, comprising the following steps: a semiconductor substrate having a first surface and a second surface disposed opposite to each other; an emitter electrode and a first passivation layer positioned on the first surface of the semiconductor substrate; a tunneling layer located on the second surface of the semiconductor substrate; the first doped conductive layer and the blocking layer are positioned on the surface of the tunneling layer, wherein the first doped conductive layer is positioned between the tunneling layer and the blocking layer, and the first doped conductive layer and the blocking layer correspond to the metallized area; the second doped conductive layer is positioned on the surface of the tunneling layer, covers the tunneling layer and the blocking layer of the non-metallized region, and has a doping concentration greater than that of the first doped conductive layer; the second passivation layer is positioned on the surface of the second doped conductive layer; a second electrode penetrating the second passivation layer and contacting the second doped polysilicon layer, and a first electrode penetrating the first passivation layer and contacting the emitter.

Description

Solar cell and its preparation method, photovoltaic module

technical field

The present application relates to the technical field of photovoltaic cells, in particular, to a solar cell, a preparation method thereof, and a photovoltaic module.

Background technique

With the continuous development of solar cell technology, the recombination loss in the metal contact area has become one of the important factors restricting the further improvement of solar cell conversion efficiency. In order to improve the conversion rate of solar cells, the solar cells are often passivated by passivating contacts to reduce the recombination in the body and surface of the solar cells. Commonly used passivated contact cells include heterojunction (Heterojunction with Intrinsic Thin-layer, HIT) cells and tunnel oxide passivated contact (Tunnel Oxide Passivated Contact, TOPCon) cells. However, the improvement of the passivation performance of the passivation structure of the existing battery is limited, so that the conversion efficiency of the passivated contact battery needs to be improved, and it is not easy to mass-produce.

Therefore, how to improve the passivation performance of passivated contact cells has become an urgent problem to be solved in the photovoltaic industry.

Contents of the invention

In view of this, the present application proposes a solar cell, a preparation method thereof, and a photovoltaic module. The solar cell can improve the low passivation performance of the metallization region while ensuring the lateral transport capability of carriers.

In a first aspect, the present application provides a solar cell, the solar cell comprising: a semiconductor substrate, the semiconductor substrate has a first surface and a second surface opposite to each other;

an emitter and a first passivation layer located on the first surface of the semiconductor substrate;

a tunneling layer located on the second surface of the semiconductor substrate;

A first doped conductive layer and a barrier layer located on the surface of the tunneling layer, wherein the first doped conductive layer is located between the tunneling layer and the barrier layer, and the first doped the conductive layer and said barrier layer correspond to metallized areas;

A second doped conductive layer located on the surface of the tunneling layer, the second doped conductive layer covers the tunneling layer and the blocking layer in the non-metallized region, the second doped conductive layer The doping concentration is greater than the doping concentration of the first doped conductive layer;

a second passivation layer located on the surface of the second doped conductive layer;

A second electrode that penetrates through the second passivation layer and forms contact with the second doped conductive layer, and a first electrode that penetrates the first passivation layer and forms contact with the emitter.

In a second aspect, the present application provides a method for preparing a solar cell, comprising the following steps:

providing a semiconductor substrate comprising opposed first and second surfaces;

forming an emitter on the first surface of the semiconductor substrate after texturing;

forming a tunneling layer on the second surface of the semiconductor substrate;

forming a first non-conductive layer on the surface of the tunneling layer, the first non-conductive layer corresponds to a metallized area and a non-metallized area;

forming a retardation layer on the surface of the first non-conductive layer, wherein the retardation layer corresponds to a metallized region;

A second non-conductive layer is formed on the surface of the first non-conductive layer and the retarder layer, and the second non-conductive layer is doped so that the second non-conductive layer and the non-metallized region are located The first non-conductive layer is transformed into a second doped conductive layer, and the first non-conductive layer located in the metallization region is transformed into a first doped conductive layer, wherein the doping of the second doped conductive layer The impurity concentration is greater than the doping concentration of the first doped conductive layer;

forming a second passivation layer on the surface of the second doped conductive layer and forming a first passivation layer on the surface of the emitter;

A second electrode is formed on the surface of the second passivation layer and a first electrode is formed on the surface of the first passivation layer.

In the third aspect, the embodiment of the present application provides a photovoltaic module, the photovoltaic module includes a cover plate, an encapsulation material layer, and a solar cell string, and the solar cell string includes a plurality of solar cells prepared by the preparation method described in the first aspect Or the solar cell described in the second aspect.

The technical solution of the present application has at least the following beneficial effects:

In the present application, a low-concentration first doped conductive layer and a retardation layer are arranged only on the metallized region of the second surface of the battery, and a second doped conductive layer with a higher concentration is arranged on the entire second surface of the battery. On the one hand , the first doped conductive layer with a lower concentration is in contact with the tunneling layer, which can reduce the passivation effect of doping elements on the tunneling layer, and reduce the recombination current density J _0,metal of the metallized region. The difference qVD of the quasi-Fermi energy level between the doped conductive layer and the semiconductor substrate is small, which is conducive to improving the theoretical open circuit voltage and the photoelectric conversion efficiency of the solar cell; in addition, the higher concentration of the second doped The heteroconductive layer exists in the metallized area and the non-metallized area, which can ensure the lateral transport rate of the charge carriers on the back of the battery, and the distance between the second doped conductive layer in the non-metallized area and the semiconductor substrate is relatively short , it can avoid that the energy band bending effect of the second doped conductive layer is weakened too much because the distance between the second doped conductive layer and the semiconductor substrate is too far due to the low concentration of the first doped conductive layer and the retarder layer , so as to ensure the selective transport of carriers.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are only For some embodiments of the present application, those of ordinary skill in the art can also obtain other drawings based on these drawings without creative effort.

Fig. 1 is a structural schematic diagram 1 of the solar cell of the present application;

Fig. 2 is the preparation flowchart of the solar cell of the present application;

FIG. 3 is a schematic structural view of the first emitter of the semiconductor substrate in the present application;

FIG. 4 is a schematic structural view of forming a tunneling layer on the second surface of a semiconductor substrate in the present application;

Fig. 5 is a schematic structural diagram of forming a first non-conductive layer on the surface of the tunneling layer according to the present application;

FIG. 6 is a schematic structural diagram showing the formation of a retardation layer in the first non-conductive layer of the present application;

Fig. 7 is a schematic structural view of the present application forming a second non-conductive layer on the surface of the first non-conductive layer and the retardation layer located in the non-metallized region;

FIG. 8 is a schematic structural view of the structure formed in FIG. 7 after doping treatment in the present application;

9 is a schematic structural view of the present application after forming a first passivation layer and a second passivation layer on a semiconductor substrate;

FIG. 10 is a schematic structural diagram of a photovoltaic module of the present application.

In the figure: 1-semiconductor substrate;

2 - emitter;

3 - first passivation layer;

4-tunneling layer;

5 - the first doped conductive layer;

6-retardation layer;

7-the second doped conductive layer;

8 - second passivation layer;

9 - first electrode;

10 - second electrode;

11 - a first non-conductive layer;

12 - second non-conductive layer;

1000-photovoltaic modules;

100 - solar cells;

200-the first cover plate;

300-the first packaging adhesive layer;

400-the second packaging adhesive layer;

500 - Second cover plate.

Detailed ways

In order to better understand the technical solutions of the present application, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.

It should be clear that the described embodiments are only some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

Terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

It should be understood that the term "and/or" used herein is only an association relationship describing associated objects, which means that there may be three relationships, for example, A and/or B, which may mean that A exists alone, and A and B exist simultaneously. B, there are three situations of B alone. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.

Optimizing the surface passivation of crystalline silicon solar energy is one of the important means to improve its efficiency. In recent years, with the development of theoretical technology and people's pursuit of better passivation effect, the tunnel oxide passivated contact (TOPCon) structure is widely favored because of its higher theoretical efficiency. The TOPCon structure is composed of ultra-thin silicon oxide and heavily doped silicon film, which has a good passivation effect and forms a field passivation effect, so that the efficiency of crystalline silicon cells prepared using TOPCon technology has reached more than 26%.

Most of the existing TOPCon batteries use poly-Si (polysilicon) as the doped layer. First, a layer of amorphous silicon (a-Si:H) is deposited by chemical vapor deposition (CVD) and then annealed to make a-Si: H is transformed into poly-Si, which greatly improves the crystallinity, further activates the doping of poly-Si, and improves the conductivity of the TOPCon battery. The researchers found that the quasi-Fermi The energy level difference qVD is a physical quantity that determines the upper limit of the open circuit voltage. When qVD is larger, the upper limit of the battery's open circuit voltage Voc is also higher. The doping concentration of the traditional doped polysilicon layer needs to reach a certain height, so that it can form a good contact with the metal electrode, but the polysilicon layer with high doping concentration also has two problems: the diffusion of phosphorus into the oxide layer will affect the passivation of the tunneling layer. and the qVD between doped polysilicon and silicon substrate is small, resulting in a low upper limit of theoretical open circuit voltage, which limits the improvement of TOPCon cell conversion efficiency.

In view of this, the embodiment of the present application provides a solar cell, as shown in FIG. 1 , which is a schematic structural diagram of the solar cell provided in the embodiment of the present application, including:

A semiconductor substrate 1, the semiconductor substrate 1 has a first surface and a second surface opposite to each other;

The emitter 2 and the first passivation layer 3 located on the first surface of the semiconductor substrate 1;

a tunneling layer 4 located on the second surface of the semiconductor substrate 1;

The first doped conductive layer 5 and the barrier layer 6 located on the surface of the tunneling layer 4, wherein the first doped conductive layer 5 is located between the tunneling layer 4 and the barrier layer 6, the first doped conductive layer 5 and the barrier layer 6 The barrier layer 6 corresponds to the metallization area;

The second doped conductive layer 7 located on the surface of the tunneling layer 4, the second doped conductive layer 7 covers the tunneling layer 4 and the blocking layer 6 in the non-metallized region, and the doping concentration of the second doped conductive layer 7 is greater than The doping concentration of the first doped conductive layer 5;

A second passivation layer 8 located on the surface of the second doped conductive layer 7;

A first electrode 9 in contact with the emitter 2 and a second electrode 10 in contact with the second doped conductive layer 7 .

In the above scheme, the present application only arranges the low-concentration first doped conductive layer 5 and the retardation layer 6 on the metallized area of the second surface of the battery, and arranges the second doped conductive layer 6 with a higher concentration on the entire surface of the second surface of the battery. The doped conductive layer 7, on the one hand, the first doped conductive layer 5 with a lower concentration is in contact with the tunneling layer 4, which can reduce the passivation effect of doping elements on the tunneling layer 4, and reduce the recombination current density of the metallized region J _0,metal , at the same time, the difference qVD of the quasi-Fermi level between the first doped conductive layer 5 with a lower concentration and the semiconductor substrate 1 is small, which is conducive to improving the theoretical open circuit voltage and improving the performance of the solar cell. Photoelectric conversion efficiency; in addition, the second doped conductive layer 7 with higher concentration exists in the metallized area and the non-metallized area, which can ensure the lateral transmission rate of the charge carriers on the back of the battery, and the second doped conductive layer 7 in the non-metallized area The distance between the doped conductive layer 7 and the semiconductor substrate 1 is relatively close, which can avoid the gap between the second doped conductive layer 7 and the semiconductor substrate 1 due to the low concentration of the first doped conductive layer 5 and the retarder layer 6. If the distance between them is too far, the band bending effect of the second doped conductive layer 7 will be weakened too much, so as to ensure the selective transport of carriers. Compared with sequentially setting the entire lightly doped conductive layer, the entire surface retardation layer 6 and the entire surface heavily doped conductive layer on the tunneling layer 4 on the back of the solar cell to improve the passivation effect, the local area of the present application The design of the optimized doped conductive layer can not only improve the passivation effect of the metallized area, but also ensure the lateral transmission efficiency of carriers, which can effectively improve the battery efficiency.

In some embodiments, the first surface of the semiconductor substrate 1 can be the front side of the solar cell, or the back side of the solar cell. When the first surface of the semiconductor substrate 1 is the front side of the solar cell, the semiconductor substrate 1 The second surface of the semiconductor substrate 1 is the back side of the solar cell; correspondingly, when the first surface of the semiconductor substrate 1 is the back side of the solar cell, the second surface of the semiconductor substrate 1 is the front side of the solar cell. It can be understood that the front side of the solar cell The surface facing the sun (that is, the light-receiving surface), and the back of the solar cell is the surface that faces away from the sun (that is, the backlight surface). Hereinafter, description will be made by taking the first surface of the semiconductor substrate 1 as the front side of the solar cell and the second surface of the semiconductor substrate 1 as the back side of the solar cell as an example.

For those skilled in the art, the metallization region refers to the region where the second electrode 10 of the solar cell penetrates the second passivation layer 8 and forms contact (direct or indirect contact) with the doped conductive layer. In some cases, The conductive metal particles in the electrode formation process will dissociate from the main structure of the electrode to form indirect contact; the non-metallized area refers to the area other than the area where the second electrode 10 penetrates the second passivation layer 8 and forms contact with the doped conductive layer. areas or areas other than metallized areas.

In some implementation manners, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), and may also be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) is, for example, one of a polycrystalline silicon substrate, a single crystal silicon substrate, a microcrystalline silicon substrate or a silicon carbide substrate, and the embodiment of the present application does not limit the specific type of the semiconductor substrate 1 . The doping element of the semiconductor substrate 1 may be phosphorus, nitrogen or the like.

In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm-240 μm, specifically 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm or 240 μm, etc., which is not limited here.

In some embodiments, the emitter 2 can be an emitter 2 structure with a uniform doping depth, or can be a selective emitter 2 structure with different doping concentrations and doping depths, specifically, the selective emitter 2 is the heavily doped emitter region corresponding to the metal electrode, and the other regions are lightly doped emitter regions. The region of the emitter 2 may be located within the surface of the semiconductor substrate 1 , or may be located outside the surface of the semiconductor substrate 1 to form an independent structure of the emitter 2 . When the semiconductor substrate 1 is N-type, the emitter 2 is P-type, and the semiconductor substrate 1 and the emitter 2 form a PN junction.

In some embodiments, the material of the first passivation layer 3 may include but not limited to single-layer oxide layers or multi-layer structures such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc., and the first passivation layer 3 can The semiconductor substrate 1 produces a good passivation effect, which helps to improve the conversion efficiency of the battery. It should be noted that the first passivation layer 3 can also function to reduce the reflection of incident light, and in some instances, it can also be called an anti-reflection layer.

In some embodiments, the thickness of the first passivation layer 3 ranges from 10nm to 120nm, specifically 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or 120nm, etc. Of course, it can also be Other values within the above range are not limited here.

In some embodiments, the tunneling layer 4 is a thin oxide layer, such as silicon oxide or metal oxide, and may contain other additional elements, such as nitrogen. Exemplarily, the tunneling layer 4 may be one or more stacked structures of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer. In other embodiments, the tunneling layer 4 may also be an oxygen-containing silicon nitride layer, an oxygen-containing silicon carbide layer, and the like. The tunneling layer 4 may not in practical effect have a perfect tunneling barrier, since eg it contains defects such as pinholes, which may cause other charge carrier transport mechanisms (eg drift, diffusion) to dominate over the tunneling effect.

In some embodiments, the thickness of the tunneling layer 4 is 0.5nm~2nm, specifically 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm or 2nm, etc. The thinner tunneling layer in this application 4. It is beneficial to prevent the transport of majority carriers and promote the tunneling collection of minority carriers.

In some embodiments, the material of the first doped conductive layer 5 includes semiconductor materials such as polysilicon, microcrystalline silicon, and silicon carbide, and the embodiment of the present application does not limit the specific type of the first doped conductive layer 5 . Preferably, the material of the first doped conductive layer 5 includes polysilicon, that is, the first doped conductive layer 5 is a first doped polysilicon layer, and the second doped conductive layer 7 is a second doped polysilicon layer.

In some embodiments, the doping element in the first doped conductive layer 5 includes at least one of boron, phosphorus, gallium and arsenic.

In some embodiments, the doping concentration of the first doped conductive layer 5 is 1E18 cm ^-3 to 1.5E21cm ^-3 , specifically 1E18 cm ^-3 , 3E18cm ^-3 , 8E18cm ^-3 , 1E19cm ^-3 , 5E19cm ^{-3 3.} 1E20cm ^-3 , 5E20cm ^-3 , 8E20cm ^-3 , 1E21cm ^-3 or 1.5E21cm ^-3 , etc. specific:

When the doping element in the first doped conductive layer 5 is phosphorus and its material is polysilicon, the first doped conductive layer 5 is a phosphorus-doped polysilicon layer; the concentration of phosphorus in the phosphorus-doped polysilicon layer is 1E19 cm ⁻³ ~ 1.5E21cm ^-3 , specifically 1E19cm ^-3 , 5E19cm ^-3 , 1E20cm ^-3 , 5E20cm ^-3 , 8E20cm ^-3 , 1E21cm ^-3 or 1.5E21cm ^{-3 ,} etc. Controlling the concentration of phosphorus in the phosphorus-doped polysilicon layer within the above-mentioned range is beneficial to obtain excellent passivation and metal contact performance. It can be understood that the concentration of phosphorus in the phosphorus-doped polysilicon layer refers to that only the The concentration of the dopant element phosphorus at the silicon lattice sites.

When the doping element in the first doped conductive layer 5 is arsenic and its material is polysilicon, the first doped conductive layer 5 is an arsenic-doped polysilicon layer; the concentration of the arsenic element in the arsenic-doped polysilicon layer is 1E19 cm ⁻³ ~ 1.5E21cm ^-3 , specifically 1E19cm ^-3 , 5E19cm ^-3 , 1E20cm ^-3 , 5E20cm ^-3 , 8E20cm ^-3 , 1E21cm ^-3 or 1.5E21cm ^{-3 ,} etc. Controlling the concentration of arsenic in the arsenic-doped polysilicon layer within the above range is beneficial to obtain excellent passivation and metal contact performance.

When the doping element in the first doped conductive layer 5 is boron and its material is polysilicon, the first doped conductive layer 5 is a boron-doped polysilicon layer; the concentration of boron in the boron-doped polysilicon layer is 1E18 cm ⁻³ ~ 4.5E19cm ^-3 , specifically 1E18cm ^-3 , 5E18cm ^-3 , 1E19cm ^-3 , 2E19cm ^-3 , 3E19cm ^-3 , 4E19cm ^-3 or 4.5E19cm ^-3 . Controlling the concentration of boron in the boron-doped polysilicon layer within the above-mentioned range is beneficial to obtain excellent passivation performance while ensuring contact with the metal electrode.

When the doping element in the first doped conductive layer 5 is gallium and its material is polysilicon, the first doped conductive layer 5 is a gallium-doped polysilicon layer; the concentration of gallium in the gallium-doped polysilicon layer is 1E18 cm ^-3 ~ 4.5E19cm ^-3 , specifically 1E18cm ^-3 , 5E18cm ^-3 , 1E19cm ^-3 , 2E19cm ^-3 , 3E19cm ^-3 , 4E19cm ^-3 or 4.5E19cm ^-3 . Controlling the concentration of gallium in the gallium-doped polysilicon layer within the above-mentioned range is beneficial to obtain excellent passivation performance while ensuring contact with the metal electrode.

In some embodiments, the thickness of the first doped conductive layer 5 is 20 nm to 150 nm, specifically 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm. nm, 120 nm, 130 nm, 140 nm or 150 nm etc.

In some embodiments, the blocking layer 6 of the present application is a film layer structure used to block the migration of doping elements in the second doped conductive layer 7 to the first doped conductive layer 5 located in the metallization region, It can reduce the diffusion of doping elements to the tunneling layer 4 in the metallization region, increase the doping concentration of the doping elements in the second doped conductive layer 7 , and further improve the field passivation capability. The material of the retardation layer 6 includes silicon oxide (such as SiO _x ), silicon carbide (such as SiC), silicon nitride (such as SiN _x ) and magnesium fluoride (such as MgF ₂ ). at least one of . The diffusion rate of dopant ions in the above materials is much lower than that of dopant ions in polysilicon. Specifically, there are many grain boundaries in polysilicon, and the tetrahedral lattice structure of polysilicon bulk Si-Si is more suitable for retardation layers. impurity atom diffusion; and retardation layer, exemplary, SiC is because its amorphous state causes impurity element diffusion to be slow, and SiO _x is that impurity element is diffused slowly because of its lattice property, makes impurity element grow in this retardation layer Time lingers, diffuses slowly and thus acts as a block.

In this embodiment, the retardation capability of the retardation layer 6 is defined by the longest distance that the thermally diffused dopant ions can migrate in the direction of the first doped conductive layer toward the tunneling layer. The shorter the longest distance that can migrate, the stronger the retardation ability of the retardation layer 6 is, and the longer the longest distance that the dopant ions can migrate, the weaker the retardation ability of the retardation layer 6 .

In some embodiments, along the direction parallel to the tunneling layer 4, that is, the X-axis direction in FIG. 1, the ratio of the width of the first doped conductive layer 5 to the width of the retardation layer 6 is 1:(1~2 ), specifically can be 1:1, 1:1.2, 1:1.5, 1:1.7 or 1:2, etc., preferably, the ratio of the width of the first doped conductive layer 5 to the width of the retardation layer 6 is 1: 1.2. It can be understood that, in some embodiments, the orthographic projection of the retardation layer 6 on the tunneling layer 4 coincides with the orthographic projection of the first doped conductive layer 5 on the tunneling layer 4. In other embodiments, The orthographic projection of the retardation layer 6 on the tunneling layer 4 partially overlaps with the orthographic projection of the first doped conductive layer 5 on the tunneling layer 4. Under the limitation of the above ratio, it can be ensured that the first doped conductive layer 5 is doped When the dopant concentration is in a lower range, the passivation effect of the doping elements on the tunneling layer 4 can be reduced, which is beneficial to increase the theoretical open circuit voltage and further improve the conversion efficiency of the solar cell.

In some embodiments, the retardation layer 6 has a thickness of 0.5 nm to 4 nm, for example, 0.5 nm, 1 nm, 2 nm, 3 nm or 4 nm. It can be understood that the thickness direction of the retardation layer 6 refers to the direction along the direction of the first doped conductive layer 5 to the tunneling layer 4, and the thickness of the retardation layer 6 is controlled within the above-mentioned range, so that the retardation along the direction perpendicular to the tunneling layer can be prevented. The doping elements in the direction of the surface where the layer 4 is located enter the first doped conductive layer 5 , so that the doping concentration in the first doped conductive layer 5 is relatively low. If the thickness of the retardation layer 6 is less than 0.5nm, the retardation ability of the retardation layer 6 is relatively poor, and the first doped conductive layer 5 with a lower concentration cannot be obtained. If the thickness of the retardation layer 6 is greater than 4nm, the retardation Layer 6 will greatly hinder the transport of carriers in the Z-axis direction, and cannot guarantee the effective transport of carriers.

In some embodiments, the second doped conductive layer 7 covers the tunneling layer 4 and the blocking layer 6 in the non-metallized region, and the material of the second doped conductive layer 7 includes semiconductor materials such as polycrystalline silicon, microcrystalline silicon, and silicon carbide. In the embodiment of the present application, the specific type of the second doped conductive layer 7 is not limited. Preferably, the material of the second doped conductive layer 7 includes polysilicon.

In some embodiments, the doping element in the second doped conductive layer 7 includes at least one of boron, phosphorus, gallium and arsenic.

In some embodiments, the doping concentration of the second doped conductive layer 7 is 5E18 cm ^-3 to 2E21cm ^-3 , specifically 5E18cm ^-3 , 8E18cm ^-3 , 1E19cm ^-3 , 5E19cm ^-3 , 1E20cm ^-3 , 5E20cm ^-3 , 8E20cm ^-3 , 1E21cm ^-3 or 2E21cm ^-3 , etc. specific:

When the doping element in the second doped conductive layer 7 is phosphorus and its material is polysilicon, the second doped conductive layer 7 is a phosphorus-doped polysilicon layer; the concentration of phosphorus in the phosphorus-doped polysilicon layer is 5E19 cm ^-3 ~ 2E21cm ^-3 , specifically 5E19cm ^-3 , 1E20cm ^-3 , 5E20cm ^-3 , 8E20cm ^-3 , 1E21cm ^-3 or 2E21cm ^{-3 ,} etc. Controlling the concentration of phosphorus in the phosphorus-doped polysilicon layer within the above-mentioned range can ensure the lateral transport of carriers and help improve the fill factor. It can be understood that the concentration of phosphorus in the phosphorus-doped polysilicon layer refers to the phosphorus-doped polysilicon layer The concentration of the dopant element phosphorus that only occupies the silicon lattice sites in the silicon.

When the doping element in the second doped conductive layer 7 is arsenic and its material is polysilicon, the second doped conductive layer 7 is an arsenic-doped polysilicon layer; the concentration of the arsenic element in the arsenic-doped polysilicon layer is 5E19 cm ^-3 ~ 2E21cm ^-3 , specifically 5E19cm ^-3 , 1E20cm ^-3 , 5E20cm ^-3 , 8E20cm ^-3 , 1E21cm ^-3 or 2E21cm ^{-3 ,} etc. Controlling the concentration of arsenic in the arsenic-doped polysilicon layer within the above-mentioned range can ensure the lateral transport of carriers and is beneficial to improve the fill factor.

When the doping element in the second doped conductive layer 7 is boron and its material is polysilicon, the second doped conductive layer 7 is a boron-doped polysilicon layer; the concentration of boron in the boron-doped polysilicon layer is 5E18 cm ⁻³ ~ 5E19cm ^-3 , specifically 5E18cm ^-3 , 1E19cm ^-3 , 2E19cm ^-3 , 3E19cm ^-3 , 4E19cm ^-3 or 5E19cm ^-3 . Controlling the concentration of boron in the boron-doped polysilicon layer within the above-mentioned range is beneficial to obtain excellent passivation performance while ensuring contact with the metal electrode.

When the doping element in the second doped conductive layer 7 is gallium and its material is polysilicon, the second doped conductive layer 7 is a gallium-doped polysilicon layer; the concentration of gallium in the gallium-doped polysilicon layer is 5E18 cm ^-3 ~ 5E19cm ^-3 , specifically 5E18cm ^-3 , 1E19cm ^-3 , 2E19cm ^-3 , 3E19cm ^-3 , 4E19cm ^-3 or 5E19cm ^-3 . Controlling the concentration of gallium in the gallium-doped polysilicon layer within the above-mentioned range is beneficial to obtain excellent passivation performance while ensuring contact with the metal electrode.

In some embodiments, the thickness of the second doped conductive layer 7 is 20nm~200nm, specifically 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm etc. It can be understood that since the first doped conductive layer 5 only corresponds to a local metallization area, the second doped conductive layer 7 covers the first doped conductive layer 5, and the second doped conductive layer 7 corresponds to the entire back of the battery (that is, corresponds to metallized and non-metallized areas). Therefore, the thickness of the first doped conductive layer 5 is smaller than the thickness of the second doped conductive layer 7 .

In some embodiments, the surface area of the tunneling layer 4 in contact with the first doped conductive layer 5 is denoted as S1, and the surface area of the tunneling layer 4 in contact with the first doped conductive layer 5 and the second The sum of the surface areas of the tunneling layer 4 in contact with the doped conductive layer 7 is denoted as S2, S1:S2=1:(5~50), specifically 1:5, 1:10, 1:20, 1: 30, 1:40, 1:45 or 1:50, etc., within the above range, it can not only ensure the passivation performance of the doped conductive layer in the metallization area, but also ensure the loading of the doped conductive layer in other areas. The lateral transport of carriers is beneficial to improve the photoelectric conversion efficiency of the battery. If S1:S2 is greater than 1:5, the proportion of the first doped conductive layer 5 is too large, resulting in greater resistance to the lateral transport of carriers in the polysilicon layer, affecting the battery fill factor, and reducing the photoelectric conversion efficiency; if S1 : S2 is less than 1:50, the proportion of the second doped conductive layer 7 is too much, resulting in the increase of the carrier recombination rate in the metal region, the passivation effect is significantly reduced, the open circuit voltage of the battery is affected, and the photoelectric conversion efficiency is reduced.

In some embodiments, the embodiment of the present application also provides a method for preparing a solar cell, which can be used to manufacture the solar cell provided in the embodiment of the present application. In the process of preparing the doped conductive layer, first prepare the covering tunneling layer 4 The first non-conductive layer 11 of the first non-conductive layer 11, and then prepare the barrier layer 6 in the metallized area, then prepare the second non-conductive layer 12 on the surface of the tunneling layer 4 and the barrier layer 6 covering the non-metallized area, and finally perform doping treatment, so that the second non-conductive layer 12 and the first non-conductive layer 11 located in the non-metallized area are converted into the second doped conductive layer 7, and the first non-conductive layer 11 located in the metallized area is converted into the first doped conductive layer 7. Due to the presence of the retardation layer 6 in the heteroconductive layer 5, as the doping process progresses, the resistance of the dopant elements entering the first non-conductive layer 11 to become the first doped conductive layer 5 becomes larger and larger, so that Along the direction of the first doped conductive layer 5 pointing to the tunneling layer 4, the doping concentration of the first doped conductive layer 5 decreases successively, so that the diffusion of doping elements to the tunneling layer 4 can be reduced as much as possible. It is beneficial to improve the passivation performance of the metallized area.

In some embodiments, during the doping process, due to the existence of the blocking layer 6 in the metallization region, the transmission of dopant elements to the direction of the first non-conductive layer 11 is prevented, so that the second non-conductive layer located in the metallization region There are many doping elements in the conductive layer 12, but in the non-metallized region, without the barrier of the retardation layer 6, the doping elements can diffuse relatively uniformly throughout the non-metallized region, resulting in The doping elements in the first non-conductive layer 11 and the second non-conductive layer 12 are less, that is, the doping concentration of the second doped conductive layer 7 located in the non-metallized region is higher than that of the second doped conductive layer 7 located in the metallized region. The doping concentration of layer 7 is set in such a way that the concentration of the region in contact with the second electrode 10 in the second doped conductive layer 7 is relatively large, which is beneficial to the lateral transport of carriers and the connection between the second doped conductive layer 7 and the second electrode 10. The second electrode 10 forms a better contact.

In some implementations, along the layer direction parallel to the plane where the tunneling layer 4 is located, since both sides of the first doped conductive layer 5 border on the second doped conductive layer 7 respectively, during the doping process, the second The doping element in the doped conductive layer 7 will also diffuse into the first doped conductive layer 5 along the direction parallel to the plane layer where the tunneling layer 4 is located, so that the first doped conductive layer towards the second doped conductive layer 7 is conductive The doping concentration of layer 5 is greater than the doping concentration of first doped conductive layer 5 facing away from second doped conductive layer 7 .

The manufacturing method of the solar cell provided by the embodiment of the present application can be used to make the TOPCon battery. Below, the preparation method of the TOPCon battery of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiment of the present invention. The described implementation Examples are only some embodiments of the present invention, not all embodiments.

The embodiment of the present application provides a method for preparing a solar cell, as shown in FIG. 2 , which is a method for preparing a solar cell of the present application, including the following steps:

In step S100 , a semiconductor substrate 1 is provided, and the semiconductor substrate 1 includes a first surface and a second surface opposite to each other.

Step S200 , forming an emitter 2 on the first surface of the textured semiconductor substrate 1 .

Step S300 , forming a tunneling layer 4 on the second surface of the semiconductor substrate 1 .

Step S400 , forming a first non-conductive layer 11 on the surface of the tunneling layer 4 , the first non-conductive layer 11 corresponds to the metallized area and the non-metallized area.

Step S500 , forming a retardation layer 6 on the surface of the first non-conductive layer 11 , wherein the retardation layer 6 corresponds to a metallization region.

Step S600, forming a second non-conductive layer 12 on the surface of the first non-conductive layer 11 and the retardation layer 6, and performing doping treatment on the second non-conductive layer 12, so that the second non-conductive layer 12 and the non-metallized area are located The first non-conductive layer 11 is transformed into the second doped conductive layer 7, and the first non-conductive layer 11 located in the metallization region is transformed into the first doped conductive layer 5, wherein the doping of the second doped conductive layer 7 The concentration is greater than the doping concentration of the first doped conductive layer 5 .

Step S700 , forming the second passivation layer 8 on the surface of the second doped conductive layer 7 and forming the first passivation layer 3 on the surface of the emitter 2 .

Step S800 , forming the second electrode 10 on the surface of the second passivation layer 8 and forming the first electrode 9 on the surface of the first passivation layer 3 .

In the above scheme, the present application sequentially forms the first non-conductive layer 11, the retardation layer 6 and the second non-conductive layer 12 on the second surface of the semiconductor substrate 1, and then performs doping treatment, the existence of the retardation layer 6 During the doping process, less doping elements will enter into the first non-conductive layer 11 between the blocking layer 6 and the tunneling layer 4, so that the second non-conductive layer 12 and the first non-conductive layer located in the non-metallized region A non-conductive layer 11 is transformed into a second doped conductive layer 7, the first non-conductive layer 11 located in the metallization region is transformed into a first doped conductive layer 5, and the doping concentration of the second doped conductive layer 7 is greater than that of the first doped conductive layer The doping concentration of a doped conductive layer 5, the second non-conductive layer 12 and the first non-conductive layer 11 located in the non-metallized area are transformed into the second doped conductive layer 7, the first non-conductive layer located in the metallized area 11 transforms into the first doped conductive layer 5 , wherein the doping concentration of the second doped conductive layer 7 is greater than that of the first doped conductive layer 5 . On the one hand, the first doped conductive layer 5 with a lower concentration is in contact with the tunneling layer 4, which can reduce the passivation effect of doping elements on the tunneling layer 4, and at the same time, the first doped conductive layer 5 with a lower concentration is in contact with the semiconductor The difference qVD of the quasi-Fermi energy level between the substrates 1 is small, which is conducive to improving the theoretical open circuit voltage and the photoelectric conversion efficiency of the solar cell; in addition, the second doped conductive layer 7 with a higher concentration exists in the The metallized area and the non-metallized area can ensure the lateral transmission rate of the charge carriers on the back of the battery, and the distance between the second doped conductive layer 7 in the non-metallized area and the semiconductor substrate 1 is relatively close, which can avoid The energy band bending effect of the second doped conductive layer 7 is weakened because the first doped conductive layer 5 and the retardation layer 6 are set at a low concentration so that the distance between the second doped conductive layer 7 and the semiconductor substrate 1 is too far away. Too much, thus ensuring the selective transport of carriers.

In some embodiments, the first surface of the semiconductor substrate 1 is the front side of the solar cell, and the second surface of the semiconductor substrate 1 is the back side of the solar cell as an example to clearly and completely describe the preparation method of the solar cell in this application.

In step S100 , a semiconductor substrate 1 is provided, and the semiconductor substrate 1 includes a first surface and a second surface opposite to each other.

In some implementation manners, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), and may also be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) is, for example, one of a polycrystalline silicon substrate, a single crystal silicon substrate, a microcrystalline silicon substrate or a silicon carbide substrate, and the embodiment of the present application does not limit the specific type of the semiconductor substrate 1 . The doping element of the semiconductor substrate 1 may be phosphorus, nitrogen or the like.

In some embodiments, the thickness of the semiconductor substrate 1 is 110 μm to 250 μm, specifically, the thickness of the semiconductor substrate 1 can be 110 μm, 120 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 180 μm μm, 190 μm, 200 μm, 210 μm, 220 μm, 230 μm, 240 μm or 250 μm, etc., the embodiment of the present application does not limit the thickness of the semiconductor substrate 1 .

In step S200 , as shown in FIG. 3 , an emitter 2 is formed on the first surface of the textured semiconductor substrate 1 .

In some implementation manners, the front surface of the semiconductor substrate 1 may be textured to form a textured surface or a surface texture structure (eg, a pyramid structure). The methods of texturing can be chemical etching, laser etching, mechanical method, plasma etching, etc., which are not limited here. Exemplarily, NaOH solution may be used to perform texturing treatment on the front surface of the semiconductor substrate 1 , since the corrosion of NaOH solution is anisotropic, a pyramid textured structure may be prepared.

It can be understood that the surface of the semiconductor substrate 1 has a textured structure through the texturing process, which produces a light trapping effect and increases the amount of light absorbed by the solar cell, thereby improving the conversion efficiency of the solar cell.

In some embodiments, before the texturing treatment, a step of cleaning the semiconductor substrate 1 may also be included to remove metal and organic pollutants on the surface.

In some embodiments, the emitter 2 can be formed on the front surface of the semiconductor substrate 1 by any one or more methods of high temperature diffusion, slurry doping or ion implantation. Specifically, the emitter 2 is formed by diffusing boron atoms through a boron source. The boron source, for example, can be diffused with boron tribromide, so that the microcrystalline silicon phase of crystalline silicon is transformed into a polycrystalline silicon phase. Since the surface of the semiconductor substrate 1 has a relatively high concentration of boron, a borosilicate glass layer (BSG) is usually formed. This layer of borosilicate glass layer has a metal gettering effect, which will affect the normal operation of the solar cell and needs to be removed later.

In some embodiments, the emitter 2 may be an emitter 2 structure with a uniform doping depth, or may be a selective emitter 2 structure with different doping concentrations and doping depths.

In step S300 , as shown in FIG. 4 , a tunneling layer 4 is formed on the second surface of the semiconductor substrate 1 .

In some implementation manners, the embodiment of the present application does not limit the specific operation manner of forming the tunneling layer 4 . Exemplarily, any one of an ozone oxidation method, a high temperature thermal oxidation method, and a nitric acid oxidation method may be used to perform oxidation tunneling on the rear surface of the semiconductor substrate 1 . The tunneling layer 4 may be one or more of a silicon oxide layer, an aluminum oxide layer and a silicon oxynitride layer.

In step S400 , as shown in FIG. 5 , a first non-conductive layer 11 is formed on the surface of the tunneling layer 4 , and the first non-conductive layer 11 corresponds to the metallized area and the non-metallized area.

In some embodiments, the first non-conductive layer 11 is deposited by low temperature, specifically, the amorphous silicon layer can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition ( ALD) by any one or more methods, and the present invention does not limit the preparation method of the doped amorphous silicon layer 400 . Correspondingly, the equipment used for deposition may be CVD equipment, PVD equipment, ALD equipment, etc.

In some embodiments, the temperature of low temperature deposition is 100°C~300°C, and the temperature of low temperature deposition can be 100°C, 110°C, 120°C, 150°C, 170°C, 200°C, 220°C, 250°C or 300°C etc. Limiting the temperature of low-temperature deposition to the above-mentioned range is conducive to the formation of non-conductive film layers, and can also crystallize local non-conductive materials, thereby improving the photoelectric performance of the battery.

In some embodiments, the thickness of the first non-conductive layer 11 is 20nm~150nm, specifically 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm , 120 nm, 130 nm, 140 nm or 150 nm, etc.

In step S500 , as shown in FIG. 6 , a blocking layer 6 is formed on the surface of the first non-conductive layer 11 , wherein the blocking layer 6 corresponds to a metallization region.

In some embodiments, in a gas atmosphere of silicon oxide, silicon carbide, silicon nitride, magnesium fluoride, etc., local laser treatment is performed on the surface of the first non-conductive layer 11 to form a retardation layer 6 corresponding to the metallized region. . Partial laser processing Compared with the existing mask plate processing method, the partial laser processing process of the present application is simple, with high productivity and easy mass production. Of course, the localized barrier layer 6 can also be formed in other ways, and this application is not limited to this. In the process of forming the barrier layer 6, the barrier layer 6 can be completely in the metallization area, or can be partially The retardation layer 6 is located inside the non-metallized area to obtain a stronger retardation effect.

In some embodiments, the pulse width of the laser used in the laser treatment is 1 ps-100 ns, specifically 1 ps, 100 ps, 500 ps, 1 ns, 5 ns, 10 ns, 50 ns or 100 ns.

In some embodiments, the wavelength of the laser is 250 nm to 532 nm, specifically 250 nm, 280 nm, 300 nm, 350 nm, 400 nm, 480 nm, 500 nm or 532 nm.

In some embodiments, the power of laser treatment is 20mJ/cm ² ~500mJ/cm ² , specifically 20 mJ/cm ² , 50 mJ/cm ² , 80 mJ/cm ² , 100 mJ/cm ² , 150 mJ /cm ² , 200 mJ/cm ² , 300 mJ/cm ² , 400 mJ/cm ² or 500 mJ/cm ² , for silicon nitride with better absorption in the blue-green band, it can be processed with a low-power laser; Materials with wide band gaps such as silicon oxide need to be processed with high-power lasers.

In some embodiments, the frequency of laser treatment is 100 kHz to 160 kHz, specifically 100 kHz, 300 kHz, 800 kHz, 1000 kHz, 1300 kHz or 1600 kHz.

In some embodiments, the number of pulse irradiations for laser treatment is 1-5 times.

Step S600, forming a second non-conductive layer 12 on the surface of the first non-conductive layer 11 and the retardation layer 6, the obtained structure is shown in FIG. 7, and the second non-conductive layer 12 is doped, and the obtained structure is as follows Figure 8 shows.

In the above steps, in the process of doping the second non-conductive layer 12, the dopant element diffuses along the Z-axis direction shown in FIG. Layer 12 → retardation layer 6 → first non-conductive layer 11 for transmission, during the process of transmission, due to the existence of the retardation layer 6, doping elements are transferred from the second non-conductive layer 12 to the first non-conductive layer 11 The difficulty of diffusion increases. Under the action of doping pressure, some doping elements can still diffuse into the first non-conductive layer 11, so that the second non-conductive layer 12 and the first non-metallized region The non-conductive layer 11 is transformed into the second doped conductive layer 7, the first non-conductive layer 11 located in the metallization area is transformed into the first doped conductive layer 5, and the doping concentration of the second doped conductive layer 7 is higher than that of the first The doping concentration of the doped conductive layer 5 . It can be understood that the thickness of the first doped conductive layer 5 is the thickness of the first non-conductive layer 11, and the thickness of the second doped conductive layer 7 is the thickness of the first non-conductive layer 11 plus the thickness of the second non-conductive layer 12. thickness of.

In some embodiments, during the doping process, as the doping process progresses, the resistance of doping elements entering the first non-conductive layer 11 to become the first doped conductive layer 5 becomes greater and greater, The doping concentration of the first doped conductive layer 5 decreases sequentially along the direction from the first doped conductive layer 5 to the tunneling layer 4 .

In some embodiments, during the doping process, due to the existence of the blocking layer 6 in the metallization region, the transmission of dopant elements to the direction of the first non-conductive layer 11 is prevented, so that the second non-conductive layer located in the metallization region There are many doping elements in the crystalline silicon, but in the non-metallized area, there is no barrier of the barrier layer 6, and the doping elements can be diffused relatively uniformly throughout the non-metallized area, resulting in the first The doping elements in the first non-conductive layer 11 and the second non-conductive layer 12 are less, that is, the doping concentration of the second doped conductive layer 7 located in the non-metallized region is higher than that of the second doped conductive layer located in the metallized region 7 doping concentration.

In some implementations, along the layer direction parallel to the plane where the tunneling layer 4 is located, since both sides of the first doped conductive layer 5 border on the second doped conductive layer 7 respectively, during the doping process, the second The doping element in the doped conductive layer 7 will also diffuse into the first doped conductive layer 5 along the direction parallel to the plane layer where the tunneling layer 4 is located, so that the first doped conductive layer towards the second doped conductive layer 7 is conductive The doping concentration of layer 5 is greater than the doping concentration of first doped conductive layer 5 facing away from second doped conductive layer 7 .

In some embodiments, the doping treatment adopts a high-temperature deposition and diffusion method, and its specific preparation process is as follows: nitrogen gas is introduced into the high-temperature equipment for 20 minutes to exhaust the air in the furnace tube, so that the high-temperature equipment is heated to 600 ° C ~ 1100 ° C, and a mixture of doped Inert gas with impurity sources, such as Ar/ _N2 , etc., react at high temperature for 5 minutes to 50 minutes; then introduce oxygen, continue the oxidation reaction at 600°C to 1100°C for 5 minutes to 60 minutes, and cool the high temperature equipment to room temperature after oxidation. Can.

In some embodiments, the dopant element of the doping treatment includes at least one of boron, gallium, phosphorus and arsenic. The dopant source for doping treatment includes at least one of boron source, gallium source, phosphorus source and arsenic source, typical but not limiting, boron source can be BCl ₃ , BBr ₃ , B ₂ H ₄ , organic boron source, for example and at least one of solid silicon containing high-concentration boron simple substance, the gallium source can be, for example, trimethylgallium and solid silicon containing high-concentration gallium simple substance, and the phosphorus source can be, for example, POCl ₃ , PH ₃ , organic phosphorus source and At least one of solid silicon with a high concentration of simple phosphorus. The source of arsenic can be, for example, AsH ₃ and solid silicon containing a high concentration of arsenic.

In some embodiments, the conductivity type of the dopant element is the same as that of the semiconductor substrate 1 . For example, if the semiconductor substrate 1 is an N-type substrate, then the doped element is an N-type doping element, such as phosphorus or arsenic, and the doped layer formed can be a phosphorus-doped layer or an arsenic-doped silicon layer; If the substrate 1 is a P-type substrate, the doped element is a P-type doped element, such as boron or gallium, and the doped layer formed is a boron-doped layer or a gallium-doped layer.

In step S700 , as shown in FIG. 9 , a second passivation layer 8 is formed on the surface of the second doped conductive layer 7 and a first passivation layer 3 is formed on the surface of the emitter 2 .

In some embodiments, in some embodiments, the first passivation layer 3 may include, but not limited to, a single-layer oxide layer or a multi-layer structure such as silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. Certainly, the first passivation layer 3 can also adopt other types of passivation layers, and the present invention does not limit the specific material of the first passivation layer 3, and the above-mentioned first passivation layer 3 can produce good passivation to the semiconductor substrate 1. and anti-reflection effects, which help to improve the conversion efficiency of the battery.

In some embodiments, the second passivation layer 8 may include but not limited to a single-layer oxide layer or a multi-layer structure such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like. For example, the second passivation layer 8 is made of silicon nitride, and the silicon nitride film layer can act as an anti-reflection film, and the silicon nitride film has good insulation, compactness, stability and resistance to impurity ions. Masking ability, the silicon nitride film layer can passivate the semiconductor substrate 1, and obviously improve the photoelectric conversion efficiency of the solar cell.

Step S800 , forming the second electrode 10 on the surface of the second passivation layer 8 and forming the first electrode 9 on the surface of the first passivation layer 3 .

In some embodiments, paste is used to print the front main gate and front sub-gate on the front side of the semiconductor substrate 1, and then dried to form the corresponding first electrode 9, and the paste is used to print the back main gate on the back side of the semiconductor substrate 1. grid and rear sub-gate, and drying to form the corresponding second electrode 10, and finally sintering the dried cell sheet to obtain a solar cell.

The specific materials of the first electrode 9 and the second electrode 10 are not limited in the embodiment of the present invention. For example, the first electrode 9 is a silver electrode or a silver/aluminum electrode, and the second electrode 10 is a silver electrode or a silver/aluminum electrode.

In a third aspect, the embodiment of the present application provides a photovoltaic module 1000, including a battery string formed by electrical connection of solar cells as described above.

Specifically, please refer to FIG. 10 , the photovoltaic module 1000 includes a first cover plate 200 , a first encapsulation adhesive layer 300 , solar cell strings, a second encapsulation adhesive layer 400 and a second cover plate 500 .

In some embodiments, the solar cell string includes a plurality of solar cells 100 connected by conductive strips, and the connection between the solar cells 100 may be partial lamination or splicing.

In some embodiments, the first cover 200 and the second cover 500 may be transparent or opaque covers, such as glass cover or plastic cover.

Both sides of the first encapsulation adhesive layer 300 are in contact with the first cover plate 200 and the battery strings respectively, and both sides of the second encapsulation adhesive layer 400 are respectively in contact with the second cover plate 500 and the battery strings. Wherein, the first encapsulation adhesive layer 300 and the second encapsulation adhesive layer 400 can be ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene co-elastomer (POE) film or polyethylene terephthalate Ester (PET) film.

The photovoltaic module 1000 can also be packaged with full side encapsulation, that is, the sides of the photovoltaic module 1000 are completely covered and packaged with packaging tape, so as to prevent the lamination deviation of the photovoltaic module 1000 during the lamination process.

The photovoltaic module 1000 also includes an edge sealing component, which is fixed and packaged on a part of the edge of the photovoltaic module 1000 . The edge sealing component can be fixed and packaged on the edge near the corner of the photovoltaic module 1000 . The sealing part can be high temperature resistant tape. The high-temperature-resistant tape has excellent high-temperature-resistant properties, will not decompose or fall off during the lamination process, and can ensure reliable packaging of the photovoltaic module 1000 . Wherein, two ends of the high temperature resistant adhesive tape are respectively fixed on the second cover plate 500 and the first cover plate 200 . The two ends of the high temperature resistant tape can be bonded to the second cover 500 and the first cover 200 respectively, and the middle part can realize the limit of the side of the photovoltaic module 1000 to prevent the photovoltaic module 1000 from being damaged during the lamination process. Lamination offset.

The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (12)

1. A solar cell, the solar cell comprising:

a semiconductor substrate having oppositely disposed first and second surfaces;

an emitter electrode and a first passivation layer positioned on the first surface of the semiconductor substrate;

a tunneling layer located on the second surface of the semiconductor substrate;

the first doped conductive layer and the blocking layer are positioned on the surface of the tunneling layer, wherein the first doped conductive layer is positioned between the tunneling layer and the blocking layer, and the first doped conductive layer and the blocking layer correspond to a metalized area;

the second doped conductive layer is positioned on the surface of the tunneling layer, the second doped conductive layer covers the tunneling layer and the blocking layer of the non-metalized area, the blocking layer is used for blocking the migration of doped elements in the second doped conductive layer into the first doped conductive layer, and the doping concentration of the second doped conductive layer is larger than that of the first doped conductive layer;

The second passivation layer is positioned on the surface of the second doped conductive layer;

a second electrode penetrating the second passivation layer and contacting the second doped conductive layer, and a first electrode penetrating the first passivation layer and contacting the emitter.

2. The solar cell according to claim 1, wherein a ratio of a width of the first doped conductive layer to a width of the blocking layer is 1 (1-2).

3. The solar cell of claim 1, wherein the surface area of the tunneling layer in contact with the first doped conductive layer is denoted as S1 and the sum of the surface area of the tunneling layer in contact with the first doped conductive layer and the surface area of the tunneling layer in contact with the second doped conductive layer is denoted as S2, S1: s2=1: (5-50).

4. The solar cell of claim 1, wherein the doping element in the first doped conductive layer comprises at least one of boron, phosphorus, gallium, and arsenic; and/or the doping concentration of the first doped conductive layer is 1E18 cm ^-3 ~1.5E21cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the thickness of the first doped conductive layer is 20 nm-150 nm.

5. The solar cell of claim 1, wherein the doping element in the second doped conductive layer comprises at least one of boron, phosphorus, gallium, and arsenic; and/or the doping concentration of the second doped conductive layer is 5E18 cm ^-3 ~2E21cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the thickness of the second doped conductive layer is 20 nm-200 nm.

6. The solar cell of claim 1, wherein the blocking layer comprises at least one of silicon oxide, silicon carbide, silicon nitride, and magnesium fluoride; and/or the thickness of the retardation layer is 0.5 nm-4 nm.

7. The solar cell of claim 1, wherein a thickness of the first doped conductive layer is less than a thickness of the second doped conductive layer.

8. The solar cell of claim 1, wherein a doping concentration of the second doped conductive layer in the non-metallized region is greater than a doping concentration of the second doped conductive layer in the metallized region.

9. The solar cell of claim 1, wherein the doping concentration of the first doped conductive layer decreases in sequence along the direction of the first doped conductive layer toward the tunneling layer.

10. The solar cell of claim 1, wherein a doping concentration of the first doped conductive layer toward the second doped conductive layer is greater than a doping concentration of the first doped conductive layer away from the second doped conductive layer, parallel to a plane in which the tunneling layer is located.

11. A method of manufacturing a solar cell, comprising the steps of:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged;

forming an emitter on the first surface of the semiconductor substrate after the texturing;

forming a tunneling layer on a second surface of the semiconductor substrate;

forming a first non-conductive layer on the surface of the tunneling layer, wherein the first non-conductive layer corresponds to a metalized area and a non-metalized area;

forming a blocking layer on the surface of the first non-conductive layer, wherein the blocking layer corresponds to a metalized area;

forming a second non-conductive layer on the surfaces of the first non-conductive layer and the blocking layer, and carrying out doping treatment on the second non-conductive layer so that the second non-conductive layer and the first non-conductive layer positioned in a non-metalized area are converted into a second doped conductive layer, and the first non-conductive layer positioned in a metalized area is converted into a first doped conductive layer, wherein the doping concentration of the second doped conductive layer is larger than that of the first doped conductive layer;

forming a second passivation layer on the surface of the second doped conductive layer and forming a first passivation layer on the surface of the emitter;

And forming a second electrode on the surface of the second passivation layer and forming a first electrode on the surface of the first passivation layer.

12. A photovoltaic module, characterized in that it comprises a cover plate, a layer of encapsulating material and a solar cell string comprising a solar cell according to any one of claims 1 to 10 or a solar cell manufactured according to the manufacturing method of claim 11.

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