CN115942744B - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents

Abstract

The disclosure provides a manufacturing method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of active areas, the active areas extend along a first direction, and bit line structures extending along a second direction are formed on each active area; forming a first groove part between each bit line structure, wherein the first groove part extends into the substrate to expose part of the active area, and the maximum dimension of the first groove part is a first width in the third direction; forming a second groove part between each bit line structure, wherein the second groove part is arranged above the first groove part and connected with the first groove part, and the maximum size of the second groove part is a second width in the third direction, and the first width is larger than the second width; filling the first and second trench portions forms a storage node contact structure. The present disclosure reduces both the contact resistance of the storage node contact structure and the parasitic capacitance between the storage node contact structure and the bit line structure by improving the shape of the storage node contact structure.

Description

Method for manufacturing semiconductor structure and semiconductor structure

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure.

Background

With the increase of the integration level of the semiconductor memory, the integration density of the semiconductor devices is increased, the distance between adjacent semiconductor devices in the semiconductor memory is reduced, parasitic capacitance between adjacent conductive devices may be increased, signal delay of the semiconductor memory may be caused, the response speed of the semiconductor memory is reduced, and the performance and reliability of the semiconductor memory are seriously affected.

However, in compliance with the trend of semiconductor memories, the integration density of semiconductor memories will continue to rise, and the difficulty and complexity of design and process for reducing parasitic capacitance between adjacent conductive devices will continue to increase.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure including:

providing a substrate, wherein the substrate comprises a plurality of independently arranged active areas, the active areas extend along a first direction, a bit line structure is formed on each active area, and the bit line structures extend along a second direction;

forming a first groove part between each bit line structure, wherein the first groove part extends into the substrate and at least exposes part of the active region, and the maximum dimension of the first groove part is a first width in a third direction perpendicular to the second direction;

Forming a second groove part between each bit line structure, wherein the second groove part is above the first groove part and is connected with the first groove part, and in the third direction, the maximum size of the second groove part is a second width, and the first width is larger than the second width;

the first and second trench portions are filled to form a storage node contact structure between the bit line structures.

Optionally, an insulating layer is filled between each bit line structure, and the first groove part and the second groove part are formed in the insulating layer.

Optionally, the insulating layer includes insulating sidewalls covering the bit line structures and an insulating dielectric layer filled between adjacent ones of the insulating sidewalls.

Optionally, before forming the first groove part and the second groove part between the bit line structures, forming a first groove in the insulating layer between the bit line structures, and etching the active region along the first groove to form the first groove part.

Optionally, after forming the first groove, forming a first conductive contact structure in the first groove;

and depositing an isolation layer on the side wall of the first groove to form a second groove part in the first groove, forming a second conductive contact structure filling the second groove part after forming the second groove part, and connecting the first conductive contact structure and the second conductive contact structure to form the storage node contact structure.

Optionally, forming a first conductive contact structure in the first groove portion includes:

forming a contact layer covering the active region exposed by the first groove part, wherein the contact layer comprises metal silicide;

and forming a first conductive layer, covering the contact layer and filling the first groove part, wherein the contact layer is connected with the first conductive layer to form the first conductive contact structure.

Optionally, the second groove part is formed in the insulating medium layer, the second groove part exposes the active region, the insulating layer and the active region are continuously etched along the second groove part, and the first groove part is formed.

Optionally, forming a storage node contact structure includes:

forming a contact layer on the active region exposed by the first groove part;

and forming a conductive layer which covers the contact layer and fills the first groove part and the second groove part, wherein the contact layer and the conductive layer in the first groove part form a first conductive contact structure, and the conductive layer in the second groove part forms a second conductive contact structure.

Optionally, the method for manufacturing the semiconductor structure further comprises the following steps:

depositing a metal layer, wherein the metal layer covers the top surface of the storage node contact structure and the bit line structure;

And patterning the metal layer, and forming a bonding pad on each storage node contact structure, wherein the bonding pad is in contact connection with the storage node contact structure.

Optionally, an insulating layer is filled between each bit line structure, and the storage node contact structure is formed in the insulating layer; patterning the metal layer and simultaneously patterning the insulating layer under the metal layer, and forming an isolation trench between the storage node contact structure and the bit line structure adjacent thereto.

Optionally, depositing an isolation layer on the sidewall of the first trench includes: and sequentially depositing a first isolation layer and a second isolation layer on the side wall of the first groove, wherein the materials of the first isolation layer and the second isolation layer are different.

A second aspect of the present disclosure provides a semiconductor structure comprising:

a substrate comprising a plurality of independently disposed active regions, the active regions extending in a first direction;

a plurality of bit line structures arranged on the substrate, wherein the bit line structures extend along a second direction, and the bit line structures are independently arranged;

and the storage node contact structures are arranged between the bit line structures, each storage node contact structure comprises a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extends into the substrate and is in contact connection with the active region, the second conductive contact structure is arranged on the first conductive contact structure and is connected with the first conductive contact structure, the maximum size of the first conductive contact structure is a first width in a third direction perpendicular to the second direction, the maximum size of the second conductive contact structure is a second width, and the first width is larger than the second width.

Optionally, the top surface of the first conductive contact structure is not lower than the top surface of the substrate.

Optionally, the first conductive contact structure includes a contact layer and a first conductive layer, the contact layer being located on the active region, the first conductive layer completely covering the contact layer.

Optionally, an insulating layer is filled between each bit line structure, and the storage node contact structure is embedded in the insulating layer.

Optionally, the insulating layer includes insulating sidewalls covering the bit line structures.

Optionally, the semiconductor structure further includes:

and the isolation layer is arranged between the second conductive contact structure and the insulating side wall.

Optionally, along the third direction, the isolation layer includes a first isolation layer and a second isolation layer sequentially disposed between the bit line structure and the second conductive contact structure, and materials of the first isolation layer and the second isolation layer are different.

Optionally, the insulating layer further includes an insulating dielectric layer filled between the insulating sidewall and the second conductive contact structure.

Optionally, the semiconductor structure further includes:

and the bonding pad is arranged above the storage node contact structure and the bit line structure, is in contact connection with the storage node contact structure, and is electrically connected with the active region through the storage node contact structure.

In the manufacturing method of the semiconductor structure and the semiconductor structure, the problem that parasitic capacitance exists between the storage node contact structure and the bit line structure is utilized, the shape of the storage node contact structure is improved, the improved storage node contact structure comprises a first conductive contact structure and a second conductive contact structure which are sequentially arranged on an active area, the largest dimension of the first conductive contact structure in the third direction is larger than the largest dimension of the second conductive contact structure in the third direction, the contact resistance of the storage node contact structure can be reduced, the parasitic capacitance between the storage node contact structure and the bit line structure can be reduced, and the stability and reliability of a semiconductor device are improved.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

Fig. 2 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

Fig. 3 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

Fig. 4 is a top view of a substrate after forming a bit line structure, according to an example embodiment.

FIG. 5 is a schematic view of a substrate in section A-A, shown according to an exemplary embodiment.

FIG. 6 is a schematic diagram illustrating a cross-section A-A after forming a bit line structure, according to an example embodiment.

Fig. 7 is a schematic diagram at section A-A after forming an insulating dielectric layer, according to an example embodiment.

Fig. 8 is a schematic diagram illustrating a cross-section A-A after forming a first trench, according to an example embodiment.

Fig. 9 is a schematic diagram illustrating a cross-section A-A after formation of a contact layer, according to an example embodiment.

Fig. 10 is a schematic diagram at section A-A after forming a first conductive contact structure, according to an example embodiment.

FIG. 11 is a schematic diagram at section A-A after deposition of an isolation material, according to an example embodiment.

Figure 12 is a schematic diagram illustrating a cross-section A-A after forming a spacer layer, according to an exemplary embodiment.

Fig. 13 is a top view illustrating the first and second groove portions after they are formed, according to an exemplary embodiment.

Fig. 14 is a schematic diagram at section B-B after forming a second conductive layer, according to an example embodiment.

Fig. 15 is a schematic diagram at section B-B after forming a metal layer, according to an example embodiment.

Fig. 16 is a schematic diagram at a B-B cross-section of a semiconductor structure formed in accordance with an exemplary embodiment.

Fig. 17 is a top view after forming a storage node contact structure in accordance with an example embodiment.

Fig. 18 is a schematic diagram at a C-C section after forming an isolation layer, according to an example embodiment.

Fig. 19 is a schematic diagram at a C-C cross-section of a semiconductor structure formed in accordance with an example embodiment.

FIG. 20 is a schematic view at section C-C after forming a second slot portion, according to an example embodiment.

FIG. 21 is a schematic view at section C-C after forming a first slot portion, according to an example embodiment.

Fig. 22 is a schematic diagram illustrating a C-C cross section after forming a contact layer, according to an example embodiment.

Fig. 23 is a schematic diagram at section C-C after formation of a conductive layer, according to an example embodiment.

Fig. 24 is a schematic diagram at a C-C section after forming a metal layer, according to an example embodiment.

Fig. 25 is a schematic diagram at a C-C cross-section of a semiconductor structure formed in accordance with an exemplary embodiment.

Reference numerals:

1. a substrate; 11. an active region; 111. a first doped region a; 112. a first doped region b; 113. a second doped region; 12. an isolation structure; 13. a dielectric layer; 2. a bit line structure; 21. a bit line contact layer; 211. a bit line contact plug; 22. a bit line blocking layer; 23. bit line metal layer; 24. an insulating sidewall; 241. a first nitride layer; 242. a first oxide layer; 243. a second nitride layer; 25. an insulating dielectric layer; 26. an isolation layer; 261. a first isolation layer; 262. a second isolation layer; 27. an insulating layer; 3. a word line; 4. a first trench; 41. a first groove portion; 42. a second groove portion; 5. a storage node contact structure; 51. a first conductive contact structure; 52. a second conductive contact structure; 6. a contact layer; 7. a conductive layer; 71. a first conductive layer; 72. a second conductive layer; 8. a bonding pad; 81. a metal layer; 9. an isolation trench;

d1, a first direction; d2, a second direction; d3, a third direction; l1, a first width; l2, a second width; l3, third width.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

In the process of forming a contact structure between semiconductor devices, the contact structure is generally disposed between two adjacent conductive devices, and the contact structure is formed by filling a trench after forming the trench between the two adjacent conductive devices. As the integration level of the semiconductor memory increases, the distance between two adjacent conductive devices decreases, and the distance between the contact structure and the adjacent conductive device is smaller, so that the parasitic capacitance between the contact structure and the adjacent conductive device increases, which seriously affects the response speed of the semiconductor memory.

However, if the size of the contact structure is reduced, on one hand, the aspect ratio of the trench is increased, the difficulty of filling the trench is increased, so that the filling is not full, and gaps exist in the formed contact structure, so that the resistance of the contact structure is increased; on the other hand, the decrease in the size of the contact structure results in a decrease in the contact area of the contact structure, which also increases the resistance of the contact structure, decreases the electrical performance of the semiconductor memory, and may even cause a problem that the contact resistance of the contact structure increases to a level that is difficult to meet the operation requirements of the semiconductor device.

In an exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure is provided, as shown in fig. 1, fig. 1 is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, fig. 4 to fig. 25 are schematic views of various stages of the method for fabricating a semiconductor structure, and the method for fabricating a semiconductor structure is described below with reference to fig. 4 to fig. 25.

The semiconductor structure is not limited in this embodiment, and the semiconductor structure is taken as a dynamic random access memory (Dynamic Random Access Memory, DRAM) as an example, but the embodiment is not limited thereto, and the semiconductor structure in this embodiment may be other structures.

As shown in fig. 1, a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure includes the following steps:

step S110: a substrate is provided, the substrate comprises a plurality of active areas which are independently arranged, the active areas extend along a first direction, a bit line structure is formed on each active area, and the bit line structure extends along a second direction.

Fig. 4 shows a top view of the substrate 1 after forming the bit line structure 2, fig. 5 shows a schematic view of a section A-A of the substrate 1 (refer to fig. 4), and fig. 6 shows a schematic view of a section A-A of fig. 4.

As shown in fig. 4 and 5, the substrate 1 includes a plurality of independently disposed active regions 11, the substrate 1 further includes an isolation structure 12, the isolation structure 12 dividing the substrate 1 into the plurality of independently disposed active regions 11, the isolation structure 12 being disposed between adjacent active regions 11 for isolating the adjacent active regions 11.

The active regions 11 extend along the first direction D1, and the plurality of active regions 11 are disposed parallel to each other and spaced apart from each other. The material of active region 11 comprises a semiconductor material, for example, the semiconductor material may comprise one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound. In this embodiment, the material of the active region 11 comprises silicon.

Each active region 11 includes two first doped regions a111 and b112, and one second doped region 113, where the two first doped regions are respectively located between the first doped region a111 and the first doped region b112, and the second doped region 113 is located between the first doped region a111 and the first doped region b 112. The first doped region a111 and the second doped region 113 form one memory cell, and the first doped region b112 and the second doped region 113 form another memory cell. In other words, two memory cells share one second doped region 113. The second doped region 113 may be connected to a bit line structure (refer to fig. 4 and 6), i.e., two memory cells share one bit line structure. The conductivity type of the dopant ions in the first doped region a111, the first doped region b112, and the second doped region 113 may be the same. The first doped region a111 may be one of a source region and a drain region, and the first doped region b112 may be the other of the source region and the drain region.

In some embodiments, the substrate 1 may be etched, shallow trenches (not shown) may be formed in the substrate 1, and then an insulating material may be deposited in the shallow trenches to form the isolation structures 12. The material of the isolation structure 12 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

Referring to fig. 5, the top surface of the substrate 1 is covered with a dielectric layer 13 for protecting the active region 11, so as to prevent the active region 11 from being electrically degraded due to natural oxidation when the active region 11 is exposed to a process environment, and the material of the dielectric layer 13 may include silicon oxide.

As shown in fig. 4 and 6, a plurality of bit line structures 2 are formed on the substrate 1, each bit line structure 2 extends along the second direction D2, the plurality of bit line structures 2 are disposed at intervals in the third direction D3, the first direction D1 and the second direction D2 intersect obliquely, and the second direction D2 and the third direction D3 are perpendicular. The first direction D1, the second direction D2 and the third direction D3 are all parallel to the plane of the top surface of the substrate 1. Each bit line structure 2 may be connected to a plurality of active regions 11, each bit line structure 2 being connected to a second doped region 113 of the respective active region 11 intersecting the bit line structure 2.

Referring to fig. 6, each bit line structure 2 includes a bit line contact layer 21, a bit line barrier layer 22, and a bit line metal layer 23, which are sequentially stacked. Illustratively, the material of the bit line contact layer 21 may include a semiconductor material such as polysilicon, the bit line barrier layer 22 may include titanium or titanium nitride, and the bit line metal layer 23 may include a metal material having good conductivity such as tungsten or copper, but is not limited thereto.

In some embodiments, referring to fig. 4 and 6, a portion of each bit line structure 2 is disposed above the substrate 1, and another portion of the structure extends into the second doped region 113 of each active region 11 intersecting it to form a bit line contact plug 211, the bit line contact plug 211 and the bit line contact layer 21 being formed simultaneously.

In this embodiment, referring to fig. 7, the insulating layer 27 is filled between each bit line structure 2. The insulating layer 27 includes insulating sidewalls 24 covering the bit line structures 2, and the insulating sidewalls 24 may include a multi-layered structure sequentially covering the surfaces of the bit line structures 2. In this embodiment, the insulating sidewall 24 includes a first nitride layer 241, a first oxide layer 242, and a second nitride layer 243 that sequentially cover the surface of the bit line structure 2 from inside to outside, and the insulating sidewall 24 is a stacked structure of nitride layer-oxide layer-nitride layer.

In some embodiments, referring to fig. 4, a plurality of word lines 3 spaced apart in the second direction D2 may be further disposed in the substrate 1, each word line 3 extends along the third direction D3 and penetrates through each active region 11 located in the extending direction thereof, the top surface of the word line 3 is lower than the top surface of the active region 11, and the word line 3 is a Buried Word Line (BWL) disposed in the substrate 1.

Step S120: a first trench portion is formed between the bit line structures, the first trench portion extends into the substrate and exposes at least a portion of the active region, and a maximum dimension of the first trench portion is a first width in a third direction perpendicular to the second direction.

Referring to fig. 4, 10, 13 and 21, a portion of the active region 11 and a portion of the isolation structure 12 between two adjacent bit line structures 2 are etched away, a plurality of first trench portions 41 (see fig. 21) are formed between the adjacent bit line structures 2, the plurality of first trench portions 41 are spaced apart along the second direction D2, the first trench portions 41 between two adjacent bit line structures 2 are spaced apart along the third direction D3, each first trench portion 41 is correspondingly disposed on one of the active regions 11, and each first trench portion 41 exposes a portion of the first doped region a111 or the first doped region b112 of the active region 11. The first groove 41 may extend partially into the substrate 1, another portion above the top surface of the substrate 1, or the first groove 41 may be formed in the substrate 1, the top surface of the first groove 41 being flush with the top surface of the substrate 1.

In the third direction D3, the maximum dimension of the first groove 41 is the first width L1. It is understood that the first width L1 may be greater than the distance between the insulating sidewalls 24 on two adjacent bit line structures 2 in the third direction D3.

Step S130: a second groove part is formed between each bit line structure, the second groove part is arranged above the first groove part and connected with the first groove part, and in the third direction, the maximum dimension of the second groove part is a second width, and the first width is larger than the second width.

Referring to fig. 12 and 21, the first groove 41 and the second groove 42 are formed in the insulating layer 27, and the largest dimension of the second groove 42 in the third direction D3 is a second width L2, and the second width L2 is smaller than the largest dimension of the first groove 41 in the third direction D3. The second width L2 is smaller than the first width L1, that is, the spacing between the sidewall surface of the second groove portion 42 and any bit line structure 2 located at both sides thereof is larger than the spacing between the sidewall surface of the first groove portion 41 and any bit line structure 2 located at both sides thereof in the third direction D3.

It is to be understood that the dimensions of the first groove portion 41 and the second groove portion 42 in the second direction D2 are not particularly limited in this embodiment, and the dimensions of the second groove portion 42 in the second direction D2 may be the same as those of the first groove portion 41 in the second direction D2, or the dimensions of the second groove portion 42 in the second direction D2 may be smaller than those of the first groove portion 41 in the second direction D2.

Step S140: the first and second trench portions are filled to form a storage node contact structure between the bit line structures.

Referring to fig. 15, 17, and 25, the storage node contact structure 5 may be formed by one or more fills, the storage node contact structure 5 having conductivity, and the storage node contact structure 5 and the first doping region a111 or the first doping region b112 being electrically connected. The storage node contact structure 5 formed in this embodiment includes the first conductive contact structure 51 located in the first groove portion 41 and the second conductive contact structure 52 located in the second groove portion 42, the first conductive contact structure 51 and the first doped region a111 or the first doped region b112 are directly connected, the second conductive contact structure 52 is located above the first conductive contact structure 51, and the largest dimension of the second conductive contact structure 52 in the third direction D3 is smaller than the largest dimension of the first conductive contact structure 51 in the third direction D3, so that the space between the sidewall surface of the second conductive contact structure 52 and the bit line structure 2 adjacent thereto is larger.

The method for manufacturing the semiconductor structure of the embodiment improves the shape of the storage node contact structure, the improved storage node contact structure comprises a first conductive contact structure and a second conductive contact structure which are sequentially arranged on an active area, the largest dimension of the first conductive contact structure in the third direction is larger than the largest dimension of the second conductive contact structure in the third direction, the contact resistance of the storage node contact structure can be reduced, parasitic capacitance between the storage node contact structure and a bit line structure can be reduced, the parasitic capacitance in the semiconductor structure can be ensured to be maintained in a lower range even if the characteristic size of the semiconductor structure is reduced, and the stability and reliability of a semiconductor device are improved.

According to an exemplary embodiment, which is an explanation of the above embodiment, the forming of the storage node contact structure includes the following steps:

step S141: a contact layer is formed on the active region exposed by the first groove portion.

Referring to fig. 8, 9, 21 and 22, each first trench 41 exposes a portion of the active region 11 and a portion of the isolation structure 12, specifically, a portion of the first doped region a111 or a portion of the first doped region b112 and a portion of the isolation structure 12. The contact layer 6 covers the first doped region a111 or the first doped region b112 exposed by the first groove portion 41. In some embodiments, each first trench portion 41 may also expose only the first doped region a111 or the first doped region b112, and not the isolation structure 12.

The material of the contact layer 6 may comprise a metal silicide. For example, the material of the contact layer 6 may include at least one of cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or tungsten silicide (WSi), but is not limited thereto.

Referring to fig. 9, the contact layer 6 may be formed in the following manner: first, a metal material layer (not shown in the drawing) including at least one of cobalt, titanium, nickel, or tungsten is deposited into the first groove portion 41. Then, the semiconductor structure is subjected to a heat treatment to diffuse the metal atoms of the metal material layer into the first doped region a111 or the first doped region b112 to form a metal silicide. Then, the remaining metal material layer that is not diffused into the first doped region a111 or the first doped region b112 is removed by etching, and the contact layer 6 is formed on the surface of the first doped region a111 or the first doped region b112 exposed at the first groove portion 41.

Step S142: and forming a conductive layer, covering the contact layer and filling the first groove part and the second groove part, wherein the contact layer and the conductive layer in the first groove part form a first conductive contact structure, and the conductive layer in the second groove part forms a second conductive contact structure.

Referring to fig. 16 and 23, the conductive layer 7 may be formed by deposition using any one or a combination of chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), or sputtering (sputtering).

Referring to fig. 13 and 21, the conductive layer 7 covers the contact layer 6 and fills the area where the first groove 41 is not filled, and the conductive layer 7 may fill the second groove 42 entirely or partially.

Referring to fig. 15, the conductive layer 7 in the first groove 41 and the conductive layer 7 in the second groove 42 may be formed in the same deposition process, or the first conductive layer 71 may be formed in the first groove 41 and then the second conductive layer 72 may be formed in the second groove 42, and the second conductive layer 72 is connected to the first conductive layer 71 on the first conductive layer 71, and the first conductive layer 71 and the second conductive layer 72 together form the conductive layer 7.

According to the manufacturing method of the semiconductor structure, metal atoms are diffused into the active area to form metal silicide, and a contact layer is formed on the exposed surface of the active area, so that the contact resistance of the storage node contact structure is reduced.

According to an exemplary embodiment, a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure includes the steps of:

as shown in fig. 2, a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure includes the following steps:

step S210: a substrate is provided, the substrate comprises a plurality of active areas which are independently arranged, the active areas extend along a first direction, a bit line structure is formed on each active area, and the bit line structure extends along a second direction.

Referring to fig. 4, 5 and 6, the substrate 1 of the present embodiment is the same as the substrate 1 provided in the step S110 of the above embodiment, and the bit line structure 2 formed on the substrate 1 is the same as the bit line structure 2 formed in the step S110 of the above embodiment.

Referring to fig. 7, an insulating layer 27 is filled between each bit line structure 2, and the insulating layer 27 includes insulating sidewalls 24 covering the bit line structures 2 and an insulating dielectric layer 25 filled between adjacent insulating sidewalls 24.

Referring to fig. 6, in the inside-out direction, the insulating sidewall 24 includes a first nitride layer 241, a first oxide layer 242, and a second nitride layer 243 covering the surface of the bit line structure 2, and the insulating sidewall 24 is a nitride layer-oxide layer-nitride layer stacked structure. In the third direction D3, the insulating sidewalls 24 on adjacent bit line structures 2 have a third width L3 therebetween.

Referring to fig. 7, insulating dielectric layers 25 are filled between the bit line structures 2. A chemical vapor deposition process or other deposition process may be used to deposit an insulating material to fill between the insulating sidewalls 24 on adjacent bit line structures 2, and the material of the insulating dielectric layer 25 may comprise silicon nitride or silicon oxynitride. Then, the top surface of the insulating dielectric layer 25 is polished into a flat surface.

In some embodiments, the second nitride layer 243 on the top layer of the insulating sidewall 24 may be filled in the unfilled region between the bit line structures 2, saving the process of forming the insulating dielectric layer 25.

Step S220: a first trench is formed in the insulating layer between the bit line structures, and an active region is etched along the first trench to form a first trench portion.

First, a first mask layer (not shown) is formed on the top surface of the insulating dielectric layer 25, and a pattern for forming the first trench 4 is defined on the first mask layer.

Referring to fig. 8, a portion of the insulating dielectric layer 25 and a portion of the insulating sidewalls 24 are then etched away according to the pattern defined by the first mask layer to form first trenches 4 between adjacent bit line structures 2. In the third direction D3, the first trench 4 has a first width L1, and the first width L1 is larger than the third width L3 (refer to fig. 6).

The substrate 1 is etched along the first trench 4, part of the active region 11 and part of the isolation structure 12 are removed, the first trench 4 is extended into the substrate 1, and the first doped region a111 or the first doped region b112 of the active region 11 is exposed. The bottom region of the first trench 4 extending into the substrate 1 is taken as a first groove portion 41.

Step S230: a first conductive contact structure is formed in the first slot portion.

In this embodiment, forming the first conductive contact structure includes the following steps:

step S231: and forming a contact layer which covers the active region exposed by the first groove part, wherein the contact layer comprises metal silicide.

Referring to fig. 9, each of the first trench portions 41 exposes a portion of the active region 11 (specifically, the first doped region a111 or the first doped region b 112) and a portion of the isolation structure 12, and the contact layer 6 covers only the active region 11 exposed by the first trench portion 41. The material of the contact layer 6 comprises a metal silicide, in this embodiment the material of the contact layer 6 comprises a cobalt silicide (CoSi).

First, metal cobalt is deposited into the first trench 4, the metal cobalt covering the active region 11 and the isolation structure 12 exposed by the first trench 4. Then, the semiconductor structure is thermally annealed to react the metallic cobalt with silicon on the surface of the active region 11 to form cobalt silicide, and the contact layer 6 is formed on the surface of the active region 11. Then, the metal silicon which is not reacted into cobalt silicide in the first trench 4 is etched away, exposing the top surface of the isolation structure 12.

Step S232: and forming a first conductive layer, covering the contact layer and filling the first groove part, wherein the contact layer is connected with the first conductive layer to form a first conductive contact structure.

Referring to fig. 10, the first trench 4 may be filled with a conductive material by any one deposition process selected from a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or sputtering. Then, the conductive material in the first trench 4 is etched back to a target height, forming a first conductive layer 71, the first conductive layer 71 and the contact layer 6 together forming a first conductive contact structure 51, the first conductive contact structure 51 filling the first groove portion 41.

In this embodiment, in a cross section perpendicular to the top surface of the substrate 1, the target height is higher than the top surface of the substrate 1 and lower than the bottom surface of the bit line metal layer 23, so that the top surface of the first conductive contact structure 51 is formed higher than the top surface of the substrate 1 and lower than the bottom surface of the bit line metal layer 23.

The top surface of the first conductive contact structure 51 is higher than the top surface of the substrate 1, so that the contact layer 6 can be prevented from being exposed in the process of etching to form the first conductive layer 71, and the contact layer 6 is damaged by an etching process, so that the structural integrity of the contact layer 6 is ensured, the contact electrical property of the first conductive contact structure 51 and the active region 11 is good, and the electrical property of the storage node contact structure 5 is improved.

The parasitic capacitance between the storage node contact structure 5 and the bit line structure 2 adjacent thereto is mainly formed between the storage node contact structure 5 and the bit line metal layer 23 of the bit line structure 2. In this embodiment, in a cross section perpendicular to the top surface of the substrate 1, the top surface of the first conductive contact structure 51 is lower than the bottom surface of the bit line metal layer 23 of the bit line structure 2, so that parasitic capacitance between the storage node contact structure 5 and the bit line structure 2 adjacent thereto can be effectively reduced.

Step S240: an isolation layer is deposited on the side wall of the first groove to form a second groove part in the first groove.

Referring to fig. 11, an isolation material may be deposited by an atomic layer deposition process to cover the top surface of the first conductive layer 71 and the walls of the first trenches 4. Then, the etching back of the isolation material exposes the first conductive layer 71, and as shown in fig. 12 and 13, the isolation material remaining on the sidewall of the first trench 4 forms the isolation layer 26, and the isolation layer 26 surrounds the second groove 42 above the first conductive contact structure 51, and in the third direction D3, the second groove 42 has a second width L2, and the second width L2 is smaller than the first width L1.

In some embodiments, the isolation layer 26 may be formed as a single layer structure to reduce the process steps and save time and cost. In this embodiment, the material of the isolation layer 26 may include silicon nitride.

In other embodiments, referring to fig. 17 and 18, depositing the isolation layer 26 on the sidewalls of the first trench 4 includes: a first isolation layer 261 and a second isolation layer 262 are sequentially deposited on the sidewalls of the first trench 4, the materials of the first isolation layer 261 and the second isolation layer 262 being different.

For example, a silicon oxide layer and a silicon nitride layer may be sequentially deposited into the first trench 4, and then the silicon oxide layer and the silicon nitride layer on the top surface of the first conductive contact structure 51 are removed, and the silicon oxide layer and the silicon nitride layer covering the insulating sidewall 24 are formed as the first isolation layer 261 and the second isolation layer 262, respectively. In this way, the insulating sidewall 24, the first isolation layer 261 and the second isolation layer 262 remained on the bit line structure 2 after etching to form the first trench 4 still form a stacked structure of nitride layer-oxide layer-nitride layer, and the stacked structure of nitride layer-oxide layer-nitride layer has better isolation effect, so that parasitic capacitance between the storage node contact structure 5 and the adjacent bit line structure 2 can be reduced, short circuit caused by mutual conduction between the storage node contact structure 5 and the adjacent bit line structure 2 can be avoided, and short circuit caused by mutual conduction between the adjacent bit line structure 2 can be avoided.

Step S250: and forming a second conductive contact structure filling the second groove part, wherein the first conductive contact structure and the second conductive contact structure are connected to form a storage node contact structure.

Referring to fig. 14, after forming the second trenches 42, the second conductive layer 72 may be deposited by any one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process, where the second conductive layer 72 fills each second trench 42 and covers the top surface of the first conductive contact structure 51 exposed by each second trench 42, and the second conductive layer 72 also covers the top surface of the insulating sidewall 24.

Referring to fig. 15 and 16, the patterned second conductive layer 72 forms a plurality of second conductive contact structures 52 independently disposed in each second trench 42, and the second conductive contact structure 52 in each second trench 42 forms a storage node contact structure 5 with the first conductive contact structure 51 at the bottom thereof.

It will be appreciated that, during the deposition to form the second conductive layer 72, instead of filling the second trench 42 as a deposition target, the second conductive layer 72 may only fill a partial region of the second trench 42, and leave a partial space in the second trench 42 for forming the bonding pad 8 in a subsequent process (which will be described in detail in the following embodiments).

According to the manufacturing method of the semiconductor structure, the first conductive contact structure is formed in the first groove part with the larger size, the second groove part with the smaller size is formed above the first conductive contact structure, and then the second conductive contact structure is formed in the second groove part, so that the first groove part and the second groove part are respectively filled, the depth-to-width ratio of each deposited groove part is reduced, the filling effect can be improved, the formed storage node contact structure does not fill gaps which are incompletely formed, and the electrical property of the storage node contact structure is better.

As shown in fig. 3, according to an exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure includes the following steps:

step S310: a substrate is provided, the substrate comprises a plurality of active areas which are independently arranged, the active areas extend along a first direction, a bit line structure is formed on each active area, and the bit line structure extends along a second direction.

Referring to fig. 4, 5, 6, and 7, the substrate 1 of the present embodiment is the same as the substrate 1 provided in step S110 of the above embodiment, and the bit line structure 2 formed on the substrate 1 is the same as the bit line structure 2 formed in step S110 of the above embodiment.

An insulating layer 27 is filled between each bit line structure 2. The insulating layer 27 includes insulating sidewalls 24 covering the bit line structures 2 and an insulating dielectric layer 25 filled between adjacent insulating sidewalls 24.

Step S320: and forming a second groove part in the insulating medium layer, wherein the second groove part exposes the active region, and continuing to etch the insulating layer and the active region along the second groove part to form a first groove part.

Referring to fig. 7, first, a second mask layer (not shown) is formed on the top surface of the insulating dielectric layer 25, and a pattern forming the second groove 42 is defined on the second mask layer. According to the second mask layer etching insulating dielectric layer 25, a part of insulating dielectric layer 25 is removed, and as shown in fig. 20, a plurality of second grooves 42 are formed in insulating dielectric layer 25, and in third direction D3, the maximum size of second grooves 42 is a second width L2, and second width L2 is smaller than or equal to third width L3 (refer to fig. 6).

In this embodiment, in the process of etching the insulating dielectric layer 25, an endpoint monitoring method may be adopted, and the top surface of the substrate 1 is used as an etching endpoint, so as to ensure that the formed second trench portions 42 are located above the substrate 1, and each second trench portion 42 exposes a part of the top surface of the first doped region a111 or the first doped region b112 of the active region 11 and the top surface of the surrounding isolation structure 12.

In some embodiments, the etching ratio of the insulating dielectric layer 25 and the dielectric layer 13 of the substrate 1 on top is different, and the top surface of the dielectric layer 13 of the substrate 1 may be used as the end point of etching the insulating dielectric layer 25.

Then, referring to fig. 21, the insulating layer 27 and the active region 11 (specifically, the first doped region a111 or the first doped region b 112) exposed by the second groove 42 are etched and removed, a portion of the insulating sidewall 24, a portion of the insulating dielectric layer 25, a portion of the active region 11, and a portion of the isolation structure 12 are removed, a first groove 41 is formed under the second groove 42, the first groove 41 extends into the substrate 1, and in the third direction D3, a maximum size of the first groove 41 is a first width L1, and the first width L1 is greater than a second width L2. In this embodiment, the first groove 41 may be etched by a dry process, a wet process, or a combination of both processes.

Step S330: a contact layer is formed on the active region exposed by the first groove portion.

Referring to fig. 22, the process of forming the contact layer 6 in this embodiment is the same as that of forming the contact layer 6 in the above embodiment, and will not be described here again.

Step S340: a conductive layer is formed to cover the contact layer and to fill the first and second trench portions.

Referring to fig. 23, the conductive layer 7 may be formed by filling the unfilled region of the first trench 41 and the second trench 42 with a conductive material by any one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or sputtering, and the conductive layer 7 also covers the top surface of the insulating dielectric layer 25.

In this embodiment, the conductive layer 7 fills the area where the first trench 41 is not filled and the partial area of the second trench 42, and the conductive layer 7 covers the trench wall of the second trench 42 and the top surface of the insulating dielectric layer 25. So as to leave a partial area of the top of the second groove portion 42 to form the pad 8 in a subsequent step (which will be described in detail later).

Step S350: and depositing a metal layer, wherein the metal layer covers the top surface of the storage node contact structure and the bit line structure.

Referring to fig. 24, the metal layer 81 may be formed by deposition using any one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process, and the metal layer 81 covers the conductive layer 7 and fills the area where the second groove portion 42 is not filled. The material of the metal layer 81 may include at least one of copper, aluminum, or tungsten.

Step S360: and patterning the metal layer, and forming a bonding pad on each storage node contact structure, wherein the bonding pad is in contact connection with the storage node contact structure.

In some embodiments, referring to fig. 24 and 25, the insulating layer 27 under the metal layer 81 is patterned while patterning the metal layer 81, forming the isolation trench 9 between the storage node contact structure 5 and the bit line structure 2 adjacent thereto.

Referring to fig. 25, an isolation trench 9 is provided between the storage node contact structure 5 and the bit line structure 2 adjacent thereto.

In this embodiment, the patterned metal layer 81 may be the following embodiment:

first, a third mask layer (not shown) is formed on the top surface of the metal layer 81, and a pattern forming the pad 8 is defined on the third mask layer.

Then, a patterning process is performed according to the third mask layer, and a portion of the metal layer 81, a portion of the conductive layer 7, a portion of the isolation layer 26, and a portion of the insulating sidewall 24 are sequentially etched and removed, so as to form a plurality of isolation trenches 9.

Referring to fig. 24 and 25, each of the first groove portions 41 and the conductive layer 7 and the contact layer 6 remaining in the second groove portion 42 connected thereto form together the storage node contact structure 5, wherein the portions of the contact layer 6 and the conductive layer 7 located in the first groove portion 41 form the first conductive contact structure 51, and the portions of the conductive layer 7 located in the second groove portion 42 form the second conductive contact structure 52. The isolation trench 9 divides the metal layer 81 into a plurality of independently disposed pads 8, each pad 8 corresponding to the top surface of the conductive layer 7 covering one storage node contact structure 5, and is connected to the first doped region a111 or the first doped region b112 of the active region 11 through the storage node contact structure 5.

According to the manufacturing method of the semiconductor structure, the second groove part is formed firstly, and then the first groove part is formed below the second groove part, so that the conductive layers in the first groove part and the second groove part can be formed in the same deposition process, and the storage node contact structure and the bonding pad are simultaneously divided in the same patterning process, so that the steps of forming the storage node contact structure can be saved, the processing efficiency is improved, and the time cost is saved.

According to an exemplary embodiment, a semiconductor structure is provided, which includes a substrate 1, a plurality of bit line structures 2 disposed on the substrate 1, and a storage node contact structure 5 disposed between the bit line structures 2, as shown in fig. 16, 17, 19, and 25. The substrate 1 includes a plurality of active regions 11 disposed independently, the active regions 11 extend along a first direction D1, the bit line structures 2 extend along a second direction D2, and the plurality of bit line structures 2 are disposed independently. Each storage node contact structure 5 comprises a first conductive contact structure 51 and a second conductive contact structure 52, the first conductive contact structure 51 extending into the substrate 1 in contact with the active region 11, the second conductive contact structure 52 being arranged on the first conductive contact structure 51 in contact with the first conductive contact structure 51, the first conductive contact structure 51 having a largest dimension of a first width L1 and the second conductive contact structure 52 having a largest dimension of a second width L2 in a third direction D3 perpendicular to the second direction D2, the first width L1 being larger than the second width L2.

Referring to fig. 4, each active region 11 includes two first doped regions and one second doped region 113. The two first doped regions are a first doped region a111 and a first doped region b112, respectively, and the second doped region 113 is located between the first doped region a111 and the first doped region b 112. The conductivity type of the dopant ions in the first doped region a111, the first doped region b112, and the second doped region 113 may be the same. The first doped region a111 may be one of a source region and a drain region, and the first doped region b112 may be the other of the source region and the drain region.

The first doped region a111 and the second doped region 113 form one memory cell and the first doped region b112 and the second doped region 113 form another memory cell. In other words, two memory cells share one second doped region 113. Each bit line structure 2 may be connected to a plurality of active regions 11, each bit line structure 2 is connected to a second doped region 113 of each active region 11 intersecting the bit line structure 2, and two memory cells share one bit line structure 2.

Referring to fig. 4, a plurality of word lines 3 are disposed in the substrate 1, each word line 3 extends along the third direction D3, the plurality of word lines 3 are disposed at intervals in the second direction D2, each word line 3 penetrates through each active region 11 located in the extending direction thereof, the top surface of the word line 3 is lower than the top surface of the active region 11, and the word line 3 is a Buried Word Line (BWL) disposed in the substrate 1. One active region 11 may be spanned across two word lines 3. One of the word lines 3 may be located between the first doped region a111 and the second doped region 113, and the other word line 3 may be located between the first doped region b112 and the second doped region 113.

In some embodiments, as shown in fig. 16, 19, and 25, the top surface of the first conductive contact structure 51 is not lower than the top surface of the substrate 1.

In some embodiments, as shown in fig. 16, 19, and 25, each bit line structure 2 includes a bit line contact layer 21, a bit line barrier layer 22, and a bit line metal layer 23 sequentially stacked on the substrate 1. The top surface of the first conductive contact structure 51 is lower than the bottom surface of the bit line metal layer 23 of the bit line structure 2.

In some embodiments, as shown in fig. 16, 19 and 25, the first conductive contact structure 51 includes a contact layer 6 and a first conductive layer 71, the contact layer 6 is located on the first doped region a111 and the first doped region b112, and the first conductive layer 71 completely covers the contact layer 6.

In some embodiments, an insulating layer 27 is filled between each of the bit line structures 2, and the storage node contact structures 5 are embedded in the insulating layer 27.

In some embodiments, the insulating layer 27 includes insulating sidewalls 24 that cover the bit line structures 2.

In some embodiments, as shown in fig. 16, 19, and 25, the semiconductor structure further includes an isolation layer 26, the isolation layer 26 being disposed between the second conductive contact structure 52 and the insulating sidewall 24.

In some embodiments, as shown in fig. 19, in the third direction D3, the isolation layer 26 includes a first isolation layer 261 and a second isolation layer 262 sequentially disposed between the bit line structure 2 and the second conductive contact structure 52 from inside to outside, and materials of the first isolation layer 261 and the second isolation layer 262 are different.

In some embodiments, insulating layer 27 further includes insulating dielectric layer 25, insulating dielectric layer 25 filling between insulating sidewall 24 and second conductive contact structure 52.

In some embodiments, as shown in fig. 16, 19 and 25, the semiconductor structure further includes a pad 8 disposed over the storage node contact structure 5 and the bit line structure 2, the pad 8 being in contact with the storage node contact structure 5, the pad 8 being electrically connected through the storage node contact structure 5 and the first doped region a111 and the first doped region b 112.

In the semiconductor structure of the present embodiment, by increasing the distance between the second conductive contact structure 52 of the storage node contact structure 5 and the adjacent bit line structure 2 in the third direction D3, the parasitic capacitance between the storage node contact structure 5 and the adjacent bit line structure 2 is reduced, and even if the feature size of the semiconductor structure is reduced, the parasitic capacitance in the semiconductor structure can be ensured to be maintained in a lower range, and the stability and reliability of the semiconductor device can be improved.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (13)

1. The manufacturing method of the semiconductor structure is characterized by comprising the following steps of:

providing a substrate, wherein the substrate comprises a plurality of independently arranged active areas, the active areas extend along a first direction, a bit line structure is formed on each active area, and the bit line structures extend along a second direction;

an insulating layer is filled between the bit line structures, the insulating layer comprises insulating side walls covering the bit line structures and insulating medium layers filled between the adjacent insulating side walls, a first mask layer is formed on the top surface of the insulating medium layers, patterns for forming first grooves are defined on the first mask layer, according to the patterns defined by the first mask layer, a part of the insulating medium layers and a part of the insulating side walls are etched and removed, a first groove is formed in the insulating layer between the bit line structures, the active area is etched along the first groove to form a first groove part in each bit line structure, the first groove part extends into the substrate, at least a part of the active area is exposed, and the maximum size of the first groove part is a first width in a third direction perpendicular to the second direction;

After the first groove part is formed, a first conductive contact structure is formed in the first groove part, an isolation layer is deposited on the side wall of the first groove to form a second groove part in the first groove part, the second groove part is arranged above the first groove part and connected with the first groove part, the first groove part and the second groove part are formed in the insulating layer, the maximum dimension of the second groove part is a second width in the third direction, the first width is larger than the second width, and the first width is larger than the distance between the insulating side walls on two adjacent bit line structures in the third direction;

after the second groove part is formed, a second conductive contact structure filling the second groove part is formed, and the first conductive contact structure and the second conductive contact structure are connected to form a storage node contact structure between the bit line structures.

2. The method of fabricating a semiconductor structure of claim 1, wherein forming a first conductive contact structure in the first trench portion comprises:

forming a contact layer covering the active region exposed by the first groove part, wherein the contact layer comprises metal silicide;

And forming a first conductive layer, covering the contact layer and filling the first groove part, wherein the contact layer is connected with the first conductive layer to form the first conductive contact structure.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein the second trench portion is formed in the insulating dielectric layer, the active region is exposed by the second trench portion, and etching of the insulating layer and the active region is continued along the second trench portion to form the first trench portion.

4. The method of fabricating a semiconductor structure of claim 3, wherein forming a storage node contact structure comprises:

forming a contact layer on the active region exposed by the first groove part;

and forming a conductive layer which covers the contact layer and fills the first groove part and the second groove part, wherein the contact layer and the conductive layer in the first groove part form a first conductive contact structure, and the conductive layer in the second groove part forms a second conductive contact structure.

5. The method of fabricating a semiconductor structure of claim 1, further comprising the steps of:

depositing a metal layer, wherein the metal layer covers the top surface of the storage node contact structure and the bit line structure;

And patterning the metal layer, and forming a bonding pad on each storage node contact structure, wherein the bonding pad is in contact connection with the storage node contact structure.

6. The method of fabricating a semiconductor structure as claimed in claim 5, wherein an insulating layer is filled between each of the bit line structures, the storage node contact structure being formed in the insulating layer; patterning the metal layer and simultaneously patterning the insulating layer under the metal layer, and forming an isolation trench between the storage node contact structure and the bit line structure adjacent thereto.

7. The method of claim 1, wherein depositing an isolation layer on a sidewall of the first trench comprises: and sequentially depositing a first isolation layer and a second isolation layer on the side wall of the first groove, wherein the materials of the first isolation layer and the second isolation layer are different.

8. A semiconductor structure, the semiconductor structure comprising:

a substrate comprising a plurality of independently disposed active regions, the active regions extending in a first direction;

a plurality of bit line structures arranged on the substrate, wherein the bit line structures extend along a second direction, and the bit line structures are independently arranged;

A storage node contact structure disposed between each of the bit line structures, the storage node contact structure including a first conductive contact structure extending into the substrate in contact with the active region and a second conductive contact structure disposed on and connected to the first conductive contact structure, the first conductive contact structure having a first width at a maximum dimension and a second width at a maximum dimension in a third direction perpendicular to the second direction, the first width being greater than the second width, wherein the first width is greater than a distance between insulating sidewalls on two adjacent bit line structures in the third direction;

an insulating layer is filled between the bit line structures, the storage node contact structures are embedded in the insulating layer, and the insulating layer comprises insulating side walls which cover the bit line structures;

the semiconductor structure further includes:

and the isolation layer is arranged between the second conductive contact structure and the insulating side wall.

9. The semiconductor structure of claim 8, wherein a top surface of the first conductive contact structure is not lower than a top surface of the substrate.

10. The semiconductor structure of claim 8, wherein the first conductive contact structure comprises a contact layer and a first conductive layer, the contact layer being located on the active region, the first conductive layer completely covering the contact layer.

11. The semiconductor structure of claim 8, wherein in the third direction, the isolation layer comprises a first isolation layer and a second isolation layer disposed in sequence between the bit line structure and the second conductive contact structure, the first isolation layer and the second isolation layer being of different materials.

12. The semiconductor structure of claim 8, wherein the insulating layer further comprises an insulating dielectric layer filled between the insulating sidewall and the second conductive contact structure.

13. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises:

and the bonding pad is arranged above the storage node contact structure and the bit line structure, is in contact connection with the storage node contact structure, and is electrically connected with the active region through the storage node contact structure.