CN113437070B

CN113437070B - Semiconductor device and method for forming the same

Info

Publication number: CN113437070B
Application number: CN202110778040.9A
Authority: CN
Inventors: 童宇诚; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2023-05-23
Anticipated expiration: 2041-07-09
Also published as: CN113437070A

Abstract

The invention discloses a semiconductor device and a forming method thereof. The bit line is disposed on the substrate. The first contact is disposed on the substrate and spaced apart from the bit line. The first spacer and the second spacer are arranged between each bit line and the first contact and respectively have a first height and a second height. The second contacts are respectively arranged above the first contacts, and the metal silicide layer is arranged between the first contacts and the second contacts, wherein the end face of the metal silicide layer is clamped between the second clearance wall and the first clearance wall. The semiconductor device of the invention can have a plug structure with more optimized structure, and can improve the electrical connection between the storage node and the underlying transistor assembly.

Description

Semiconductor device and method for forming the same

Technical Field

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor memory device and a method for forming the same.

Background

With the trend toward miniaturization of various electronic products, the design of semiconductor memory devices must meet the requirements of high integration and high density. For the DRAM (dynamic random access memory, DRAM) with recessed gate structure, the current trend is that it has gradually replaced the DRAM with planar gate structure because it can obtain longer carrier channel length in the same semiconductor substrate to reduce the leakage of capacitor structure.

In general, a dram with a recessed gate structure is formed by aggregating a large number of memory cells (memory cells) to form an array region for storing information, and each memory cell may be formed by a transistor element in series with a capacitor element for receiving voltage information from Word Lines (WL) and Bit Lines (BL). In response to product requirements, the density of memory cells in the array region must be increased continuously, which results in increased difficulty and complexity in the related manufacturing process and design. Therefore, the prior art needs to be further improved to effectively improve the performance and reliability of the related memory device.

Disclosure of Invention

One of the objectives of the present invention is to provide a method for forming a semiconductor device, which is to additionally provide a metal silicide layer between a lower contact and an upper contact through a metal silicide process, so that the metal silicide layer can be disposed between spacers on both sides of a bit line. Therefore, the forming method of the invention can form a plug structure with better contact with the substrate, and form a semiconductor device with more optimized structure so as to improve the electrical connection between the storage node plug and the underlying transistor component.

Another object of the present invention is to provide a semiconductor device, in which a metal silicide layer is disposed between the lower contact and the upper contact, so that the metal silicide layer can be disposed across the spacers on both sides of the bit line. Therefore, the semiconductor device of the invention can have a plug structure with more optimized structure, and can improve the electrical connection between the storage node plug and the underlying transistor assembly.

In order to achieve the above object, one embodiment of the present invention provides a method for forming a semiconductor device, which includes the following steps. First, a substrate is provided, and a plurality of bit lines are formed on the substrate. Then, a plurality of first contacts are formed on the substrate, and the bit lines and the first contacts are alternately arranged with each other. Then, a first spacer is formed on the substrate and located between each bit line and the first contact, the first spacer is disposed on the substrate and extends upwards from the top surface of the substrate to a first height, a second spacer is formed on the first spacer and located between the first spacer and the first contact, the second spacer is disposed on the substrate and extends upwards from the top surface of the substrate to a second height, and the first height is higher than the second height. And forming a plurality of second contacts above the first contacts respectively, and forming a metal silicide layer on the substrate, wherein the metal silicide layer is positioned between the first contacts and the second contacts, and the end face of the metal silicide layer is clamped between the second clearance wall and the first clearance wall.

In order to achieve the above object, one embodiment of the present invention provides a semiconductor device, which includes a substrate, a plurality of bit lines, a plurality of first contacts, a first spacer, a second spacer, a plurality of second contacts, and a metal silicide layer. The bit line is disposed on the substrate. The first contact is disposed on the substrate and spaced apart from the bit line. The first spacers are arranged between the bit lines and the first contacts, the first spacers are arranged on the substrate and extend upwards from the top surface of the substrate to a first height, the second spacers are arranged between the first spacers and the first contacts, the second spacers are arranged on the substrate and extend upwards from the top surface of the substrate to a second height, and the first height is higher than the second height. The second contacts are respectively arranged above the first contacts. The metal silicide layer is arranged between the first contact and the second contact, wherein the end face of the metal silicide layer is clamped between the second spacer and the first spacer.

Drawings

Fig. 1 to 7 are schematic views illustrating steps of a method for forming a semiconductor device according to a first embodiment of the present invention, wherein:

FIG. 1 is a schematic top view of a semiconductor device after forming bit lines;

FIG. 2 is a schematic cross-sectional view of FIG. 1 along the line A-A';

FIG. 3 is a schematic cross-sectional view of a semiconductor device after an etching process;

FIG. 4 is a schematic cross-sectional view of a semiconductor device after forming a conductive layer;

FIG. 5 is a schematic cross-sectional view of a semiconductor device after forming a metal silicide layer; and

FIG. 6 is a schematic cross-sectional view of a semiconductor device after forming storage node plugs; and

fig. 7 is a schematic cross-sectional view of a semiconductor device after forming a storage node pad.

Fig. 8 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

Fig. 9 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

Fig. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

Fig. 11 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.

Fig. 12 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention.

Fig. 13 is a schematic cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention.

Wherein reference numerals are as follows:

100. 200, 300, 400, 500, 600, 700 semiconductor device

101. Insulating region

103. Active region

105. An opening

107. An opening

110. Substrate and method for manufacturing the same

110a top surface

120. Word line

130. Dielectric layer

131. Oxide layer

133. Nitride layer

135. Oxide layer

160. 162, 164 bit lines

160a bit line contact

161. Semiconductor layer

163. Barrier layer

165. Conductive layer

167. Cover layer

170. 370 spacer structure

171. Spacer wall

171a side wall

173. Spacer wall

175. Spacer wall

175a top surface

190. 290, 390, 490, 590, 690, 790 storage node plug

191. Conductive layer

193. 393, 493, 593, 693, 793 contacts

195. 295, 395, 495, 595, 695, 795 contacts

201. 203, 204, 205, 206, 207 metal silicide layers

205a first part

205b second part

206a arc type top surface

207a first part

207b second part

210. Dielectric layer

220. Storage node bonding pad

276. Spacer wall

377. Spacer wall

377a shoulder

D1, D2 direction

h1, h2 height

Width W1, W2

Detailed Description

The following description of the preferred embodiments of the present invention will be presented to enable those skilled in the art to which the invention pertains and to further illustrate the invention and its advantages. Those of skill in the art will be able to make substitutions, rearrangements, and combinations of features from several different embodiments to accomplish other embodiments without departing from the spirit of the invention by referring to the following examples.

Referring to fig. 1 to 6, which are schematic views illustrating steps of a method for forming a semiconductor device 100 according to a first embodiment of the present invention, fig. 1 is a schematic top view of the semiconductor device in a forming stage, and fig. 2 to 6 are schematic cross-sectional views of the semiconductor device in the forming stage. The semiconductor device 100 of the present embodiment is, for example, a dynamic random access memory (dynamic random access memory, DRAM) device, which includes at least one transistor device (not shown) and at least one capacitor device (not shown) as the smallest component cell (memory cell) in the DRAM array and receives voltage information from the bit line 160 and the word line 120.

The semiconductor device 100 includes a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., siC, siGe, etc.), or a silicon-on-insulator (SOI) substrate, etc., at least one insulating region 101, such as a shallow trench isolation (shallow trench isolation, STI), is formed in the substrate 110, and a plurality of Active Areas (AA) 103 are defined on the substrate 100. The insulating region 101 is formed, for example, by etching a plurality of trenches (not shown) in the substrate 100, and then filling an insulating material (such as silicon oxide or silicon oxynitride) into the trenches.

As shown in fig. 1, a plurality of buried gates (not shown) may be formed in the substrate 110, and the buried gates extend in the same direction D1, for example, parallel to each other, and cross the active region 103 to serve as a Buried Word Line (BWL) 120 of the semiconductor device 100. A plurality of source/drain regions (not shown) may be formed in the substrate 110 on both sides of the buried gate, such that the buried gate and the source/drain regions may together form transistor elements (not shown) of the semiconductor device 100. A plurality of bit lines 160 may be formed on the substrate 110 and extend parallel to each other along another direction D2 perpendicular to the buried word lines 120 to simultaneously cross the active region 103 and the buried word lines 120 within the substrate 110. Referring to fig. 2 together, in a direction D1, each bit line 160 is formed on the substrate 110 separately from each other and includes a semiconductor layer (e.g. including polysilicon) 161, a barrier layer 163 (e.g. including titanium and/or titanium nitride), a conductive layer 165 (e.g. including low-resistance metal such as tungsten, aluminum or copper), and a cap layer 167 (e.g. including silicon oxide, silicon nitride or silicon oxynitride, etc.), which are stacked in sequence, but not limited thereto. It should be noted that a portion of the bit line 162 is formed on the dielectric layer 130 above the substrate 110, wherein the dielectric layer 130 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure including an oxide layer 131-nitride layer 133-oxide layer 135; another portion of the bit line 164 has a Bit Line Contact (BLC) 160a formed thereunder, and may extend further into the substrate 110. The bit lines 162 and 164 are, for example, alternately arranged, so that each bit line 164 may be located between two adjacent bit lines 162, and the bit line contact 160a under the bit line 164 is, for example, integrally formed with the semiconductor layer 161 of the bit line 164 and directly contacts the substrate 110, as shown in fig. 2.

As shown in fig. 2,

spacers

171 and 173 are formed on the sidewalls of each bit line 160 in sequence. In one embodiment, the

spacers

171 and 173 are formed by different deposition and etching processes, such that the

spacers

171 and 173 each have a long shape and comprise different insulating materials. For example, a spacer 171 may be formed by first performing a process of forming a spacer 171, integrally depositing a silicon nitride material layer (not shown) on the bit lines 160 and the substrate 110, covering the top surface and the sidewalls of each bit line 160 and the top surface of the dielectric layer 130, and then performing an etching back process to partially remove the silicon nitride material layer to form the spacer 171 (including silicon nitride and other materials); then, a spacer 173 is formed by integrally depositing a silicon oxide layer (not shown) to cover the top surface of each bit line 160, the spacer 171, and the top surface 110a of the substrate 110, and performing another etching back process to partially remove the silicon oxide layer to form the spacer 173 (including silicon oxide). As such, the

spacers

171, 173 may have top surfaces that are flush with each other. In addition, after the etching back process of the spacer 171, the underlying dielectric layer 130 may be further patterned, so that the spacer 173 to be formed later may be directly formed on the top surface 110a of the substrate. It should be noted that in the present embodiment, the

spacers

171 and 173 formed on a portion of the bit line 162 are respectively located on the top surface of the dielectric layer 130 and the top surface 110a of the substrate 110, and the

spacers

171 and 173 formed on another portion of the bit line 164 extend further into the substrate 110, and are located on the sidewalls of the bit line contact 160a, as shown in fig. 2.

Then, an interlayer dielectric layer (interlayer dielectric layer, ILD, not shown) is formed on the substrate 110, at least filling the space between the bit line 160 and the

spacers

171, 173 and having a substantially flat top surface, and then etching the substrate 110 through the bit line 160 and the

spacers

171, 173 as an etching mask, so as to remove a portion of the interlayer dielectric layer and the underlying substrate 110 (active region 103) and insulating region 101 to define a plurality of openings 105 between adjacent bit lines 160 and

spacers

171, 173 as plug openings. Wherein the bottom of each opening 105 is below the top surface 110a of the substrate 110, as shown in fig. 2. Next, as shown in fig. 3, another etching process is performed to remove the spacers 173 on the top surface 110a of the substrate 110, leaving only the spacers 173 extending into the substrate 110 and on the sidewalls of the bit line contacts 160 a. Thus, the opening 105 may be enlarged into the opening 107 to expose a portion of the top surface 110a of the substrate 110.

As shown in fig. 4, a deposition and etching back process is sequentially performed to form spacers 175 on the sidewalls of each opening 107, on the exposed top surface 110a of the substrate 110 and the remaining spacers 173; then, a conductive layer 191 is formed in each opening 107 by deposition and planarization (e.g., chemical mechanical polishing) processes, so as to fill the opening 107 and directly contact the underlying substrate 110 (active region 103) and insulating region 101. In one embodiment, the spacers 175 preferably comprise a material different from the

spacers

171, 173, such as silicon oxynitride, silicon hydroxide, etc., to reduce the resistance; the conductive layer 191 is preferably formed by an epitaxial growth (epi) process, and may include, but not limited to, polysilicon, silicon-phosphorus (SiP), and the like.

Then, as shown in fig. 5, an etching process is performed through the bit line 160 and the spacer 171 as an etching mask, a portion of the spacer 175 and a portion of the conductive layer 191 are removed, and then a metal silicide process or a self-aligned metal silicide process is performed to simultaneously form a plurality of contacts 193 respectively filling the lower half of the opening 107 and a metal silicide (silicide) layer 201 on the top surface of each contact 193. In detail, contacts 193 are spaced apart from bit line 160, isolated from each other by

spacers

171, 173, 175, the bottoms of each contact 193 directly contacting active region 103 and/or insulating region 101 within substrate 110. The metal silicide layer 201 spans the contact 193 and the spacer 175, so that the end surfaces of both sides can be sandwiched between the top surface 175a of the spacer 175 and the sidewall 171a of the spacer 171, and contact the spacer 175 (top surface 175 a) and the spacer 171 (sidewall 171 a). In one embodiment, the metal silicide layer 201 comprises, for example, titanium silicide (titanium silicide, tiSi _x ) Tungsten silicide (tungsten silicide, WSi) _x ) Tantalum silicide (tantalum silicide, taSi) _x ) Molybdenum silicide (molybdenum silicide, moSi) _x ) Cobalt silicide (CoSi) _x ) Or nickel silicide (NiSi) _x ) Such materials are not limited thereto.

It should be noted that, since the metal silicide layer 201 consumes a portion of the conductive layer 191 during formation, the top surface (not shown) of the conductive layer 191 after etching is slightly higher than the top surface 175a of the spacer 175 during etching of the portion of the spacer 175 and the conductive layer 191. Thus, after the metal silicide layer 201 is formed, the top surface of the contact 193 may be substantially flush with the top surface 175a of the spacer 175, and the metal silicide layer 201 may be located approximately at the interface between the conductive layer 165 and the cap layer 167 of the bit line 160, as shown in fig. 5. Moreover, since the lattice structure of the metal silicide layer 201 is larger than that of the conductive layer 191, the volume thereof is slightly expanded to extend onto the top surface 175a of the spacer 175. Thus, the metal silicide layer 201 may directly contact the sidewall 171a of a portion of the spacer 171, the top surface 175a of the spacer 175, and the top surface of the contact 193, and have a relatively large width W2. On the other hand, after the etching process, the

spacers

175 and 171 disposed above the substrate 110 and the spacers 173 disposed in the substrate 110 may together form the spacer structure 170. Wherein, the spacers 171 are directly disposed on the sidewalls of each bit line 160 and extend upward from the substrate 110, and the spacers 171 extend upward from the top surface 110a of the substrate 110 by a height h1; spacers 175 are disposed between the bit lines 160 and the contacts 173 and also extend upward from the substrate 110, the spacers 175 extending upward from the top surface 110a of the substrate 110 to have a height h2, the height h1 being greater than the height h2; the spacer 173 is located below a portion of the spacer 175 and extends into the substrate 110, as shown in fig. 5.

Subsequently, as shown in fig. 6, another deposition and planarization (e.g., chemical mechanical polishing) process is sequentially performed, and a conductive layer is formed over the metal silicide layer 201 to at least fill the opening 107, as a plurality of contacts 195 respectively filling the upper half of the opening 107. In an embodiment, the conductive layer includes, but is not limited to, a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W). The contact 195 may have a maximum width W2 in the direction D1, which is greater than the maximum width W1 of the contact 193 in the direction D1, because it is disposed above the metal silicide layer 201. As such, contact 193, metal silicide layer 201, and contact 195 may collectively form a storage node plug (storage node contact, SNC) 190 of the semiconductor device, which may directly contact substrate 110 and/or insulating region 101.

Finally, as shown in fig. 7, a plurality of storage node pads (SN pads) 220 are formed on the dielectric layer 210 on the substrate 110 to respectively correspond to the storage node plugs 190. In one embodiment, the storage node pad 220 also includes a low resistance metal material such as aluminum, titanium, copper or tungsten, for example, but not limited to, a material different from the contact 195. Preferably, in another embodiment, the storage node pads are also optionally integrally formed with contacts 195 and may comprise the same material. Subsequently, a capacitor structure (not shown) may also continue to be formed over the substrate 110 to directly contact and electrically connect the underlying storage node pads 220. The capacitor structure includes a capacitor bottom electrode layer (not shown), a capacitor dielectric layer (not shown) and a capacitor top electrode layer (not shown) stacked in sequence, so as to form a plurality of capacitors (not shown) extending vertically as Storage Nodes (SN) of the semiconductor device 100. Thus, the storage node can be electrically connected to the transistor element through the storage node pad 220 and the storage node plug 190, so as to maintain a good contact relationship between the capacitor structure and the storage node plug 190.

Thereby, the semiconductor device 100 in the first embodiment of the present invention is completed. According to the forming method of the present embodiment, a metal silicide process is additionally performed to form a metal silicide layer 201 between the contact 193 and the contact 195. The metal silicide layer 201 is simultaneously disposed over the contact 193 and the spacer 175, so that the two side surfaces can be sandwiched between the spacer 171 and the spacer 175 to have a width W2 greater than the contact 193. Also, the metal silicide layer 201 may contact the spacers 171 (sidewalls) and the spacers 175 (top 175 a) at the same time. In this way, the contact 195 disposed above the metal silicide layer 201 may have a larger contact area, so that the storage node plug 190 may have a more stable structure, and the storage node pad 220 and the storage node formed later may be electrically connected to the transistor element through the storage node plug 190, thereby maintaining a good contact relationship between the capacitor structure and the storage node plug 190. In addition, the metal silicide layer 201 includes titanium silicide, tungsten silicide, tantalum silicide, molybdenum silicide, cobalt silicide, or nickel silicide, which can further reduce the resistance of the storage node plug 190, thereby improving the electrical connection between the storage node plug and the transistor element in the substrate 110.

In addition, it should be readily understood by those skilled in the art that other aspects of the semiconductor device and the method for forming the same are possible in order to meet the actual product requirements, and are not limited to the foregoing. Further embodiments or variations of the method of the semiconductor device of the present invention are described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present invention are labeled with like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 8, a cross-sectional view of a semiconductor device 200 according to a second embodiment of the invention is shown. The structure of the semiconductor device 200 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, including the formation of the substrate 110, the word line 120 (not shown in fig. 8), the bit line 160, and the like, and will not be repeated here. The main difference between this embodiment and the first embodiment is that a spacer 276 is additionally formed on the silicide layer 201.

In detail, in this embodiment, after the metal silicide layer 201 is formed, deposition and etching back are performed to form the spacers 276, and then the contacts 295 are formed. Thus, spacers 276 may be disposed over spacers 175 and metal silicide layer 201 to be coplanar with the top surfaces of spacers 171. The spacers 276, the

spacers

175 and 171 disposed over the substrate 110, and the spacers 173 disposed within the substrate 110 may collectively form the spacer structure 170 of the present embodiment.

Therefore, the semiconductor device 200 of the second embodiment of the invention also has an additional metal silicide layer 201, and the metal silicide layer 201 spans over the spacer 175, so that the two side end surfaces can be sandwiched between the spacer 171 and the spacer 175 to obtain a larger contact area. In this way, the storage node plug 290 can have a more stable structure, and the metal silicide layer 201 can further reduce the resistance of the storage node plug 290, thereby improving the electrical connection between the storage node plug 290 and the transistor element in the substrate 110.

Referring to fig. 9, a cross-sectional view of a semiconductor device 300 according to a third embodiment of the invention is shown. The structure of the semiconductor device 300 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, including the formation of the substrate 110, the word line 120 (not shown in fig. 9), the bit line 160, and the like, and will not be repeated here. The main difference between this embodiment and the first embodiment is that the spacer structure 370 further includes a spacer 377 covering the spacer 175 and the spacer 171.

Specifically, in this embodiment, after forming the spacer 175 with a height h2 smaller than the spacer 171, a deposition and etching back process is performed to form the spacer 377, and then the contact 393, the metal silicide layer 203 and the contact 395 are formed. Thus, spacers 377 may be disposed between spacers 175 and contacts 393 to directly contact sidewalls 171a of spacers 171 and top 175a and sidewalls of spacers 175. The portion of the spacer 377 covering the top surface 175a of the spacer 175 may form a shoulder 377a corresponding to the height difference (h 2-h 1) between the

spacers

171, 175, and the end surfaces of the two sides of the metal silicide layer 203 may be clamped on the shoulder 377a of the spacer 377 and also have a width W2 greater than the contact 393, as shown in fig. 9. In the present embodiment, the spacer 377 is also disposed above the substrate 110 and extends upward from the top surface 110a of the substrate 110 by the same height h1 as the spacer 171, but is not limited thereto. In another embodiment, the spacer 377 may also have another height (not shown) greater than the height h2 and less than the height h 1.

Thus, the semiconductor device 300 according to the third embodiment of the present invention also has an additional metal silicide layer 203, and the metal silicide layer 203 spans over the shoulder 377a of the spacer 377, so that the two side faces can be sandwiched between the spacer 171 and the spacer 175 and can contact the spacer 171 (the sidewall 171 a) and the spacer 175 (the top 175 a) at the same time. Thus, the contact 395 over the metal silicide layer 203 may have a larger contact area, so that the storage node plug 390 may have a more stable structure. Furthermore, the metal silicide layer 203 can further reduce the resistance of the storage node plug 390, thereby improving the electrical connection between the storage node plug and the transistor element in the substrate 110.

Referring to fig. 10, a cross-sectional view of a semiconductor device 400 according to a fourth embodiment of the invention is shown. The structure of the semiconductor device 400 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, including the formation of the substrate 110, the word line 120 (not shown in fig. 10), the bit line 160, and the like, and will not be repeated here. The main difference between this embodiment and the first embodiment is that the top surface of the contact 493 is higher than the top surface 175a of the spacer 175, so that the silicide layer 204 formed by the silicide process may have an inverted U shape.

In detail, the present embodiment can make the top surface (not shown) of the etched conductive layer 191 significantly higher than the top surface 175a of the spacer 175 when etching the spacer 175 and the conductive layer 191. Thus, after the metal silicide layer 204 is formed, the top surface of the contact 493 may be higher than the top surface 175a of the spacer 175, such that a recess (not shown) is formed between the top surface of the contact 493 and the top surface 175a of the spacer 175, and then, since the lattice structure of the metal silicide layer 204 is larger than that of the conductive layer 191, the volume is slightly expanded to fill the recess, so as to form an inverted U-shape as shown in fig. 10. In this arrangement, the metal silicide layer 204 may directly contact the sidewall 171a of the spacer 171, the top surface 175a of the spacer 175, and a portion of the sidewall of the contact 493, as shown in fig. 10.

Thus, the semiconductor device 400 of the fourth embodiment of the present invention also has an additional metal silicide layer 204, and the metal silicide layer 204 spans over the spacer 175, so that the two side end surfaces can be sandwiched between the spacer 171 and the spacer 175 and fill the recess between the top surface of the contact 493 and the top surface 175a of the spacer 175. Furthermore, the metal silicide layer 204 may contact the spacers 171 (sidewalls 171 a) and the spacers 175 (top 175 a) at the same time. In this manner, contact 495 disposed over metal silicide layer 204 may also achieve a larger contact area, such that storage node plug 490 may achieve a more robust structure. Furthermore, the metal silicide layer 204 may further reduce the resistance of the storage node plug 490, thereby improving the electrical connection with the transistor elements within the substrate 110.

Referring to fig. 11, a cross-sectional view of a semiconductor device 500 according to a fifth embodiment of the invention is shown. The structure of the semiconductor device 500 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, including the formation of the substrate 110, the word line 120 (not shown in fig. 11), the bit line 160, and the like, and will not be repeated here. The main difference between this embodiment and the first embodiment is that the top surface of the contact 593 is lower than the top surface 175a of the spacer 175, so that the metal silicide layer 205 formed by the metal silicide process may have a T-shape.

In detail, when etching the spacer 175 and the conductive layer 191, the top surface (not shown) of the etched conductive layer 191 is slightly lower than the top surface 175a of the spacer 175. Thus, after the metal silicide layer 205 is formed, the top surface of the contact 593 may be lower than the top surface 175a of the spacer 175, such that a height difference (not shown) may be formed between the top surface of the contact 593 and the top surface 175a of the spacer 175, and then, since the lattice structure of the metal silicide layer 205 is larger than that of the conductive layer 191, the volume may be slightly expanded and extended onto the top surface 175a of the spacer 175, so as to form a T-shape as shown in fig. 11. In this arrangement, the metal silicide layer 205 may have a first portion 205a and a second portion 205b having different widths, wherein the width of the first portion 205a is equal to the maximum width W1 of the contact 593 in the direction D1, and the width of the second portion 205b is equal to the maximum width W2 of the contact 595 in the direction D1. Furthermore, the metal silicide layer 205 may directly contact the sidewall 171a of the spacer 171, the top surface 175a of the spacer 175, and the sidewall, so as to form a more stable structure, as shown in fig. 11.

Thus, the semiconductor device 500 of the fifth embodiment of the invention also has an additional metal silicide layer 205, and the metal silicide layer 205 spans over the spacer 175, so that the two side faces can be sandwiched between the spacer 171 and the spacer 175. In addition, the metal silicide layer 205 has a first portion 205a and a second portion 205b with different widths, and can contact the spacer 171 (the sidewall 171 a) and the spacer 175 (the top surface 175 a) at the same time, so that a more stable structure can be formed. In this way, the upper contact 595 disposed above the metal silicide layer 205 can also obtain a larger contact area, further improving the structural stability of the storage node plug 590. Meanwhile, the metal silicide layer 205 may further reduce the resistance of the storage node plug 590, thereby improving the electrical connection between the storage node plug and the transistor element in the substrate 110.

Referring to fig. 12, a cross-sectional view of a semiconductor device 600 according to a sixth embodiment of the invention is shown. The structure of the semiconductor device 600 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, including the formation of the substrate 110, the word line 120 (not shown in fig. 12), the bit line 160, and the like, and will not be repeated here. The main difference between this embodiment and the first embodiment is that the parameters of the metal silicide manufacturing process are adjusted so that the metal silicide layer 206 may have an arch bridge shape.

In detail, when etching the spacer 175 and the conductive layer 191, the top surface (not shown) of the etched conductive layer 191 is slightly higher than the top surface 175a of the spacer 175, and the parameters (such as metal silicide rate) of the metal silicide process are controlled. In this manner, the arch-bridge shaped metal silicide layer 206 may be formed, and after the metal silicide layer 206 is formed, the top surface of the contact 693 may exhibit an arc surface, two sides of which may be substantially flush with the top surface 175a of the spacer 175, and the center of which is slightly higher than the top surface 175a of the spacer 175, as shown in fig. 12. Correspondingly, the metal silicide layer 206 may also have an arc-shaped top surface 206a with a center higher than the top surface 175a, and further extends onto the top surface 175a of the spacer 175, forming an arch bridge structure as shown in fig. 12. In this way, the end surfaces on both sides of the metal silicide layer 206 can be also sandwiched between the spacers 175 to have a width W2 greater than the contact 693, so as to increase the contact area between the metal silicide layer 206 and the contact 695 above it, thereby effectively improving the structural stability of the storage node plug 690.

Thus, the semiconductor device 600 of the sixth embodiment of the present invention also has the metal silicide layer 206 additionally disposed, and the metal silicide layer 206 spans over the spacer 175, so that the two side faces can be sandwiched between the spacer 171 and the spacer 175 and simultaneously contact the spacer 171 (the sidewall 171 a) and the spacer 175 (the top surface 175 a). In addition, the arc-shaped top surface 206a of the metal silicide layer 206 may further increase the contact area of the contact 695, reduce the resistance of the storage node plug 690, and obtain a more optimized structure. In this way, the electrical connection between the storage node plug 690 and the transistor element in the substrate 110 can be further improved.

Referring to fig. 13, a cross-sectional view of a semiconductor device 700 according to a seventh embodiment of the invention is shown. The structure of the semiconductor device 700 in this embodiment is substantially the same as that of the semiconductor device 100 in the first embodiment, including the formation of the substrate 110, the word line 120 (not shown in fig. 13), the bit line 160, and the like, and will not be repeated here. The main difference between this embodiment and the first embodiment is that the parameter conditions of the metal silicide manufacturing process are adjusted so that the metal silicide layer 207 can have a step shape.

In detail, in the present embodiment, when etching the spacer 175 and the conductive layer 191, the top surface (not shown) of the etched conductive layer 191 is slightly lower than the top surface 175a of the spacer 175, and the parameters (such as metal silicide rate) of the metal silicide process are controlled so that the metal silicide layer 207 can be uniformly expanded onto the top surface 175a of the spacer 175 during formation. Thus, the step-shaped metal silicide layer 207 may be formed, which includes a first portion 207a located above the contact 793 and a second portion 207b located above the spacer 175, wherein the top surfaces of the first portion 207a and the second portion 207b have a significant height difference, as shown in fig. 13. In this way, the end surface of the second portion 207b of the metal silicide layer 207 may be also sandwiched between the spacers 175, so that the metal silicide layer 207 may have a width W2 greater than the contact 693 as a whole, thereby increasing the contact area between the metal silicide layer 207 and the contact 795 thereabove and effectively improving the structural stability of the storage node plug 790.

Thus, the semiconductor device 700 according to the seventh embodiment of the invention also has an additional metal silicide layer 207, and the metal silicide layer 207 spans over the spacer 175, so that the two side faces can be sandwiched between the spacer 171 and the spacer 175 and simultaneously contact the spacer 171 (the sidewall 171 a) and the spacer 175 (the top surface 175 a). In addition, the contact area of the contact 795 is further increased by the metal silicide layer 207 having a step shape, the resistance of the storage node plug 790 is reduced, and a more optimized structure is obtained. In this way, the electrical connection between the storage node plug 790 and the transistor element within the substrate 110 may be further improved.

In general, the semiconductor device of the present invention is additionally provided with a metal silicide layer between the lower contact and the upper contact through a metal silicide manufacturing process, so that the metal silicide layer can be arranged across the spacer at two sides of the bit line. The two side end surfaces of the metal silicide layer are clamped between the clearance walls and have a width larger than that of the lower contact. Therefore, the metal silicide layer and the upper contact can correspondingly have larger contact area, so that the storage node plug of the semiconductor device can obtain a more stable structure. In addition, the metal silicide layer may include titanium silicide, tungsten silicide, tantalum silicide, molybdenum silicide, cobalt silicide, nickel silicide, etc. to further reduce the resistance of the storage node plug and further improve the electrical connection between the storage node plug and the transistor element. Thus, the semiconductor device of the invention can have more optimized structure and device performance.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of bit lines disposed on the substrate;

a plurality of first contacts disposed on the substrate and spaced apart from the bit lines;

the first gap wall is arranged between each bit line and the first contact, and is arranged on the substrate and extends upwards from the top surface of the substrate to a first height;

the second spacer is arranged between the first spacer and the first contact, is arranged on the substrate and extends upwards from the top surface of the substrate to a second height, and the first height is higher than the second height;

a plurality of second contacts respectively arranged above the first contacts; and

the metal silicide layer is arranged between the first contact and the second contact, wherein the end face of the metal silicide layer is clamped between the second spacer and the first spacer;

the maximum width of the metal silicide layer is larger than that of the first contact;

the metal silicide layer is in direct contact with the side wall of the first spacer and the top surface of the second spacer.

2. The semiconductor device of claim 1, wherein a top surface of the first contact is higher than a top surface of the second spacer, the metal silicide layer directly contacting sidewalls of the first spacer, the top surface of the second spacer, and a portion of the sidewalls of the first contact.

3. The semiconductor device of claim 2, wherein the metal silicide layer has an inverted U-shape.

4. The semiconductor device of claim 1, wherein a top surface of the first contact is lower than the top surface of the second spacer, and wherein the metal silicide layer directly contacts sidewalls of the first spacer and the top and sidewalls of the second spacer.

5. The semiconductor device according to claim 4, wherein the metal silicide layer has a first portion and a second portion having different widths, the first portion being disposed over the second portion and having a larger width.

6. The semiconductor device according to claim 1, wherein the bit line includes a plurality of first bit lines and a plurality of second bit lines, the first bit lines and the second bit lines are alternately arranged with each other, and the second bit lines are in direct contact with the substrate.

7. The semiconductor device of claim 6, wherein the first bit line and the second bit line each comprise a semiconductor layer, a barrier layer, and a conductive layer sequentially stacked.

8. The semiconductor device of claim 6, further comprising a third spacer disposed below the second spacer on both sides of the second bit line, the third spacer extending within the substrate.

9. The semiconductor device of claim 1, further comprising a fourth spacer disposed between the second spacer and the first contact, the fourth spacer directly contacting sidewalls of the first spacer and top and sidewalls of the second spacer, the fourth spacer having a shoulder on a portion of the fourth spacer overlying the top of the second spacer, the end surface of the metal silicide layer being sandwiched between the shoulders.

10. The semiconductor device of claim 9, wherein the fourth spacer has a third height, wherein the third height is greater than the second height and less than or equal to the first height.

11. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a plurality of bit lines on the substrate;

forming a plurality of first contacts on the substrate, wherein the bit lines and the first contacts are alternately arranged;

forming a first spacer on the substrate, wherein the first spacer is positioned between each bit line and the first contact, and is arranged on the substrate and extends upwards from the top surface of the substrate to a first height;

forming a second spacer on the first spacer, between the first spacer and the first contact, wherein the second spacer is disposed on the substrate and extends upwards from the top surface of the substrate to a second height, and the first height is higher than the second height;

forming a plurality of second contacts above the first contacts respectively; and

forming a metal silicide layer on the substrate, wherein the metal silicide layer is positioned between the first contact and the second contact, and the end face of the metal silicide layer is clamped between the second spacer and the first spacer;

the metal silicide layer directly contacts the side wall of the first spacer and the top surface of the second spacer.

12. The method of claim 11, wherein the bit line further comprises, after forming:

forming the first spacer and the third spacer on the side wall of each bit line, wherein the top surface of the first spacer is flush with the top surface of the third spacer;

removing a portion of the third spacer; and

and forming the second spacer on the first spacer, wherein the second spacer is positioned on the third spacer of the rest part.

13. The method of forming a semiconductor device according to claim 11, further comprising:

and forming a fourth spacer on the second spacer, wherein the fourth spacer is positioned between the second spacer and the first contact, the fourth spacer is in direct contact with the side wall of the first spacer and the top surface and the side wall of the second spacer, a shoulder is arranged on the part, covered on the top surface of the second spacer, of the fourth spacer, and the end surface of the metal silicide layer is clamped between the shoulders.

14. The method of claim 11, wherein the metal silicide layer is formed after the bit line and the second spacer are formed.

15. The method of claim 14, wherein the forming the bit line and the second spacer further comprises:

forming a conductive layer between each bit line and the second spacer;

etching the conductive layer; and

and performing a metal silicide manufacturing process to form the metal silicide layer and the first contact.

16. The method of claim 15, wherein a top surface of the first contact is higher than the top surface of the second spacer, the metal silicide layer directly contacting sidewalls of the first spacer, the top surface of the second spacer, and a portion of sidewalls of the first contact.

17. The method of claim 15, wherein a top surface of the first contact is lower than the top surface of the second spacer, and wherein the metal silicide layer directly contacts sidewalls of the first spacer and the top and sidewalls of the second spacer.