CN115863406A - Lateral diffusion metal oxide semiconductor device - Google Patents
Lateral diffusion metal oxide semiconductor device Download PDFInfo
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- CN115863406A CN115863406A CN202310190519.XA CN202310190519A CN115863406A CN 115863406 A CN115863406 A CN 115863406A CN 202310190519 A CN202310190519 A CN 202310190519A CN 115863406 A CN115863406 A CN 115863406A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 12
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 230000005684 electric field Effects 0.000 description 10
- 238000004088 simulation Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
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Abstract
The application provides a lateral diffusion metal oxide semiconductor device which comprises a substrate, a field plate dielectric layer and a field plate electrode, wherein the field plate dielectric layer is arranged on one side of the substrate, and a groove is formed in one surface, far away from the substrate, of the field plate dielectric layer; the field plate electrode is arranged on the field plate dielectric layer and filled in the groove, and the groove is positioned in the middle area of the field plate electrode. Through the design, when the high voltage is applied to the drain terminal electrode, the field plate dielectric field bears the voltage close to the grid electrode and the two ends of the drain terminal electrode, and the extra voltage can be borne at the groove position, so that the device obtains higher breakdown voltage, the voltage resistance of the device is improved, and the original lower on-resistance is maintained.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a lateral diffusion metal oxide semiconductor device.
Background
Laterally Diffused Metal Oxide Semiconductor Field Effect Transistors (LDMOSFETs) are the preferred choice for high voltage switching applications because of their compatibility with CMOS technology. The high-performance LDMOS device has two characteristics: one is low on-loss (Rsp) and the other is high Breakdown Voltage (BVDSS).
However, the two parameters have a certain trade-off relation, and generally, a device with low on-resistance has low breakdown voltage; the on-resistance of the device with high breakdown voltage is also relatively large. The LDMOS device obtains higher breakdown voltage, meanwhile, the low on-resistance is kept unchanged as much as possible, the layout size, the physical appearance and the doping concentration of the device are generally required to be optimally designed, but the breakdown voltage of the device is not well improved due to the improvement of the current design.
Disclosure of Invention
In view of the above, the present application provides a laterally diffused metal oxide semiconductor device to improve the breakdown voltage of the device.
The application provides a lateral diffusion metal oxide semiconductor device, which comprises:
a substrate;
the field plate dielectric layer is arranged on one side of the substrate, and a groove is formed in one surface, far away from the substrate, of the field plate dielectric layer;
and the field plate electrode is arranged on the field plate dielectric layer and is filled in the groove, and the groove is positioned in the middle area of the field plate electrode.
And the groove is positioned in the middle region of the field plate dielectric layer.
And the distance between the groove bottom of the groove and the substrate is smaller than the thickness of the field plate dielectric layer around the groove.
Wherein the groove diameter of the groove is 1/100-99/100 of the length of the field plate electrode.
The vertical section of the groove is in at least one of a concave shape, a W shape or a V shape.
The groove height of the groove is 1/10-9/10 of the field plate dielectric layer.
The field plate dielectric layer is made of at least one of silicon oxide, silicon oxynitride and silicon nitride.
The LDMOS device further comprises a drain terminal electrode which is arranged on the substrate and is in contact with the field plate dielectric layer.
Wherein the drain terminal electrode is not in contact with the field plate electrode.
The application provides a lateral diffusion metal oxide semiconductor device which comprises a substrate, a field plate dielectric layer and a field plate electrode, wherein the field plate dielectric layer is arranged on one side of the substrate, and a groove is formed in one surface, far away from the substrate, of the field plate dielectric layer; the field plate electrode is arranged on the field plate dielectric layer and filled in the groove, and the groove is positioned in the middle area of the field plate electrode. In this application, through set up the recess that is used for holding partial field plate electrode on the field plate dielectric layer, and set up the recess in the middle zone that is located the field plate electrode for the thickness attenuate of the field plate dielectric layer of field plate electrode intermediate position, so that can attract more electric charges to form stronger electric field, and then make the groove position of field plate electrode intermediate zone can disperse more voltages, thereby improve the breakdown voltage of device, and keep lower on-resistance.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic cross-sectional structure diagram of an LDMOS device provided by the present application;
fig. 2 is a simulation calculation chart of the voltage division of the field plate dielectric layer when the LDMOS device provided by the present application and the LDMOS device in the prior art break down.
Reference numerals are as follows:
10. a laterally diffused metal oxide semiconductor device; 100. a substrate, 110, a drift region; 120. a channel region; 200. a field plate dielectric layer; 210. a groove; 300. a field plate electrode; 400. a gate electrode; 500. a gate dielectric layer; 600. a drain terminal electrode; 700. a source electrode.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
The application provides a lateral diffusion metal oxide semiconductor device which comprises a substrate, a field plate dielectric layer and a field plate electrode, wherein the field plate dielectric layer is arranged on one side of the substrate, and a groove is formed in one surface, far away from the substrate, of the field plate dielectric layer; the field plate electrode is arranged on the field plate dielectric layer and filled in the groove, and the groove is positioned in the middle area of the field plate electrode.
In this application, through set up the recess that is used for holding partial field plate electrode on the field plate dielectric layer, and set up the recess in the middle zone that is located the field plate electrode for the thickness attenuate of the field plate dielectric layer of field plate electrode intermediate position, so that can attract more electric charges to form stronger electric field, and then make the groove position of field plate electrode intermediate zone can disperse more voltages, thereby obtain higher voltage resistance, maintain original lower on-resistance simultaneously.
Referring to fig. 1, fig. 1 is a schematic cross-sectional structural diagram of an LDMOS device provided in the present application. The present application provides an LDMOS device, a lateral diffused metal oxide semiconductor device 10 includes a substrate 100, a field plate dielectric layer 200, a field plate electrode 300, a gate 400, a gate dielectric layer 500, and a drain terminal electrode 600, which are described in detail below.
Specifically, the substrate 100 is a silicon substrate 100, the substrate 100 has a drift region 110 and a channel region 120, and the drift region 110 is located on one side of the channel region 120.
The field plate dielectric layer 200 is disposed on one side of the substrate 100, and a groove 210 is formed on a surface of the field plate dielectric layer 200 away from the substrate 100. Specifically, the field plate dielectric layer 200 is disposed on the drift region 110, and a groove 210 is formed on a surface of the field plate dielectric layer 200 away from the semiconductor.
The field plate electrode 300 is arranged on the side of the field plate dielectric layer 200 far away from the substrate 100, the field plate electrode 300 is filled in the groove 210, and the groove 210 is positioned in the middle region of the field plate electrode 300.
In the prior art, the field plate dielectric layer 200 under the field plate electrode 300 is usually a flat film layer, that is, the field plate dielectric layer 200 is usually uniform in thickness, when the field plate electrode 300 generates a voltage division effect, the voltage distributed at each position of the field plate electrode 300 is not uniform, generally, the voltage division at two sides of the edge of the field plate electrode 300 is more, that is, the voltage borne by the field plate dielectric layer 200 near the gate 400 and two ends of the drain electrode 600 is more, and the voltage division at the middle position of the field plate electrode 300 is less, which limits the voltage withstanding performance of the device, in the present application, by arranging the groove 210 for accommodating part of the field plate electrode 300 on the field plate dielectric layer 200 and arranging the groove 210 in the middle region of the field plate electrode 300, the thickness of the field plate dielectric layer 200 at the middle position of the field plate electrode 300 is reduced, so that when the drain electrode 600 applies a high voltage, the field plate dielectric layer 200 bears the voltage near the gate 400 and two ends of the drain electrode 600, and bears an additional voltage at the position of the groove 210, the device obtains a higher breakdown voltage, which improves the voltage withstanding the voltage of the device, and maintains the original low on-resistance.
The drain electrode 600 is located on the drift region 110 and on one side of the field plate dielectric layer 200, the drain electrode 600 contacts the field plate dielectric layer 200, and the drain electrode 600 does not contact the field plate electrode 300. A source terminal electrode 700 is disposed on the channel region 120 and on a side of the gate 400 away from the field plate dielectric layer 200. The gate dielectric layer 500 is disposed on the drift region 110 and the channel region 120, that is, the gate dielectric layer 500 is disposed on a portion of the drift region 110 and a portion of the channel region 120, and the gate dielectric layer 500 is in contact with the field plate dielectric layer 200. The gate 400 is disposed on the gate dielectric layer 500 and contacts the field plate dielectric layer 200.
In an embodiment, the distance between the bottom of the groove 210 and the substrate 100 is less than the thickness of the field plate dielectric layer 200 around the groove 210, that is, the height of the field plate dielectric layer 200 around the groove 210 is higher than the height of the field plate dielectric layer 200 under the groove 210, so as to further attract more charges to form a stronger electric field, and further, the groove 210 in the middle region of the field plate electrode 300 can disperse more voltages, thereby obtaining higher voltage resistance, and maintaining the original lower on-resistance.
In one embodiment, the groove 210 has a groove diameter of 1/100 to 99/100 of the length of the field plate electrode 300. Specifically, the groove diameter of the groove 210 can be 1/100, 2/100, 1/3, 55/100 or 99/100 of the length of the field plate electrode 300, so as to further enable more charges to be attracted to form a stronger electric field, and further enable more voltage to be dispersed at the position of the groove 210 in the middle area of the field plate electrode 300, thereby obtaining higher voltage resistance.
In one embodiment, the vertical cross-sectional shape of the groove 210 is at least one of a concave shape, a W shape or a V shape, so that the groove 210 in the middle region of the field plate electrode 300 can distribute more voltage, thereby obtaining higher voltage resistance while maintaining the original low on-resistance.
In one embodiment, the trench 210 has a trench height of 1/10-9/101/2 of the field plate dielectric layer 200. Specifically, the groove height of the groove 210 is 1/10, 1/2, 7/10 or 9/10 of the field plate dielectric layer 200, so that more charges can be attracted to form a stronger electric field, and further more voltage can be dispersed at the groove 210 position in the middle region of the field plate electrode 300, so that higher voltage resistance can be obtained, and meanwhile, the original lower on-resistance can be maintained.
In one embodiment, the material of the field plate dielectric layer 200 is silicon oxide.
Referring to fig. 2, fig. 2 is a graph illustrating a simulation calculation of the voltage division of the field plate dielectric layer when the LDMOS device provided by the present application and the LDMOS device in the prior art break down.
It should be noted that fig. 2 is a comparison of the lateral electric field distribution of the drift region 110 under the field plate electrode 300 under the Breakdown Voltage (BVD) of the LDMOS of the prior art and the LDMOS of the present application, where the X abscissa of fig. 2 is the size range of the field plate electrode 300 and the Y ordinate is the electric field strength. The field plate dielectric layer 200 of the LDMOS in the prior art mainly bears voltage at two ends of the field plate dielectric layer under the breakdown voltage, but the voltage born by the middle region is less, and the middle region of the field plate dielectric layer 200 in the present application will bear additional voltage due to the thinner middle thickness, so as to obtain higher voltage withstanding performance, that is, after the groove 210 is added to the LDMOS in the present application, an additional electric field peak is formed below the field plate dielectric layer corresponding to the position of the groove 210, and this additional peak electric field is formed by the added portion of voltage withstanding.
Table 1:
| VT（V） | Rsp（mΩ*mm2） | BVD（V） | |
| LDMOS of the prior art | 1.49 | 9.8 | 23.9 |
| LDMOS of the present application | 1.49 | 9.65 | 29.5 |
Table 1 shows a comparison of electrical data of LDMOS simulation models generated using the same process conditions but different field plate dielectric layers 200. In the device of the present application in table 1, the groove diameter of the groove 210 is 1/3 of the length of the field plate electrode 300, the groove height of the groove 210 is 1/10-9/101 of the field plate dielectric layer 200, and the vertical cross-sectional shape of the groove 210 is a concave shape, so that compared with the LDMOS of the prior art, the LDMOS using the field plate dielectric layer 200 of the present application can maintain the on-resistance unchanged, and the breakdown voltage is higher.
Therefore, compared with the field plate dielectric layer 200 in the LDMOS device in the prior art, the field plate electrode 300 in the application has better electrical property and is compatible with most of the existing LDMOS devices.
The application provides an LDMOS device, through set up the recess 210 that is used for holding partial field plate electrode 300 on field plate dielectric layer 200, and set up recess 210 in the middle zone that is located field plate electrode 300, make the thickness attenuate of field plate dielectric layer 200 of field plate electrode 300 intermediate position, so that can attract more electric charges to form stronger electric field, and then make the recess 210 position of field plate electrode 300 middle zone can disperse more voltages, thereby obtain higher voltage endurance, maintain original lower on-resistance simultaneously.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.
Claims (9)
1. A laterally diffused metal oxide semiconductor device, comprising:
a substrate;
the field plate dielectric layer is arranged on one side of the substrate, and a groove is formed in one surface, far away from the substrate, of the field plate dielectric layer;
and the field plate electrode is arranged on the field plate dielectric layer and is filled in the groove, and the groove is positioned in the middle area of the field plate electrode.
2. The LDMOS device of claim 1, wherein the groove is located in an intermediate region of the field plate dielectric layer.
3. The LDMOS device of claim 2, wherein a bottom of the trench is spaced from the substrate by a distance less than a thickness of the field plate dielectric layer around the trench.
4. The LDMOS device of claim 3, wherein a groove diameter of the groove is 1/100-99/100 of a length of the field plate electrode.
5. The LDMOS device of claim 4, wherein a vertical cross-sectional shape of the groove is at least one of a notch, W, or V shape.
6. The LDMOS device of claim 5, wherein the trench has a trench height of 1/10-9/10 of the field plate dielectric layer.
7. The LDMOS device of claim 6, wherein the field plate dielectric layer comprises a material comprising at least one of silicon oxide, silicon oxynitride, and silicon nitride.
8. The ldmos device of claim 7 further including a drain terminal electrode disposed on said substrate and in contact with said field plate dielectric layer.
9. The ldmos device of claim 8, wherein said drain terminal electrode is not in contact with said field plate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310190519.XA CN115863406A (en) | 2023-03-02 | 2023-03-02 | Lateral diffusion metal oxide semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310190519.XA CN115863406A (en) | 2023-03-02 | 2023-03-02 | Lateral diffusion metal oxide semiconductor device |
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| US20220285551A1 (en) * | 2021-03-05 | 2022-09-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate electrode extending into a shallow trench isolation structure in high voltage devices |
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2023
- 2023-03-02 CN CN202310190519.XA patent/CN115863406A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005183633A (en) * | 2003-12-18 | 2005-07-07 | Toyota Central Res & Dev Lab Inc | Semiconductor device and manufacturing method thereof |
| US20080067558A1 (en) * | 2006-09-15 | 2008-03-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
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