CN115842012A - Modularized chip structure and chip system - Google Patents

Abstract

A modular chip structure and a chip system provided by the present invention relate to the technical field of electronic circuits, to optimize the modular chip structure to a certain extent, and avoid further optimization and adjustment required for product iteration, resulting in long development and testing cycles. The modular chip structure provided by the present invention includes a substrate and a platform chip assembly; the platform chip assembly includes at least two main chips, a plurality of first pads are formed on the side of the main chip facing the substrate, and a plurality of first pads are formed on the side of the substrate away from the main chip. There are multiple second pads, and the number of the second pads includes the number of functional pins of the first pads included in at least two main chips.

Description

Modular chip structure and chip system

technical field

The invention relates to the technical field of air conditioners, in particular to a modular chip structure and a chip system.

Background technique

With the continuous development of semiconductor technology, the packaging design of chips is constantly developing towards the direction of integration and miniaturization. However, the technology development and reliability and stability of chips require continuous accumulation and precipitation. Each iteration of terminal products, platform chips with different configurations need to redesign or adjust the corresponding peripheral chips, so that enterprises need to invest a lot of manpower and material resources to research , resulting in a long development cycle and heavy maintenance workload. And if the chip can be iterated at the beginning of the design, it can save the development cycle and investment of the end product.

Therefore, it is urgent to provide a modular chip structure and a chip system to solve the problems existing in the prior art to a certain extent.

Contents of the invention

The purpose of the present invention is to provide a modular chip structure and a chip system to optimize the modular chip structure to a certain extent, avoiding the need for further optimization and adjustment for product iterations, resulting in long development and testing cycles.

A modular chip structure provided by the present invention includes a substrate and a platform chip assembly; the platform chip assembly includes at least two main chips, and a plurality of first pads are formed on the side of the main chip facing the substrate, A plurality of second pads are formed on the side of the substrate away from the main chip, and the number of the second pads includes at least two functional pins of the first pads included in the main chip quantity.

Wherein, both the first pad and the second pad are made of metal material, and the cross section of the second pad is circular.

Specifically, the package sizes of the plurality of main chips are the same, and the sizes of the first pads are the same.

Wherein, the modular chip structure provided by the present invention further includes a memory chip, the memory chip is arranged on the side of the substrate away from the second bonding pad, and the memory chip is arranged close to the main chip, the The memory chip communicates with the main chip.

Specifically, the modular chip structure provided by the present invention further includes a first power management chip and a second power management chip, the first power management chip and the second power management chip are both arranged on the substrate away from the One side of the second pad, and the first power management chip and the second power management chip are arranged around the main chip; the first power management chip is connected to the main chip circuit, and the second The power management chip is connected with the memory chip and the main chip respectively.

Further, at least one main chip is connected to the substrate, and a plurality of decoupling capacitors are formed on the side of the substrate away from the main chip.

Wherein, a plurality of the second pads are distributed in an array or along the circumference of the substrate, or a part of the second pads is distributed in an array, and another part of the second pads surrounds the arrayed pads. The circumferential distribution of the second pads is described above.

Specifically, the diameter of the second pads is 0.6MM, and among the second pads distributed uniformly along the circumference of the substrate, the center-to-center distance between adjacent second pads is 1.27MM , among the second pads distributed in a matrix, the center-to-center spacing between adjacent second pads is 1.8MM, and the second pads that are evenly distributed in the circumferential direction and the adjacent second pads are in a matrix The center-to-center distance between the second pads in the formula distribution is 1.27MM.

Compared with the prior art, the modular chip structure provided by the present invention has the following advantages:

The modular chip structure provided by the present invention includes a substrate and a platform chip assembly; the platform chip assembly includes at least two main chips, a plurality of first pads are formed on the side of the main chip facing the substrate, and a plurality of first pads are formed on the side of the substrate away from the main chip. There are multiple second pads, and the number of the second pads includes the number of functional pins of the first pads included in at least two main chips.

From this analysis, it can be seen that since each first pad on the main chip has a corresponding function, and the platform chip assembly in this application includes at least two main chips, the application makes the substrate away from one of the main chips. A plurality of second pads are formed on the side, and the number of the second pads includes at least the number of the first pad function pin pads included in the two main chips, so that a substrate can have at least two main chips When any main chip is connected to the substrate, it is only necessary to solder the first pad and the second pad of the corresponding function, and connect the second pad to the corresponding functional interface in the chip system through the lead. Connect to implement the corresponding functions of the main chip.

It can be understood that since different types and configurations of main chips have different functions, when replacing the main chip, only the second pads needed to be used can be soldered to complete the functional compatibility of different main chips .

In addition, the present invention also provides a modular chip system, including a base plate, a packaging structure, and the above-mentioned modular chip structure; the packaging structure encapsulates the modular chip structure, and exposes the modular chip structure with one side of the second pad.

Wherein, the packaging structure includes an inner silk screen and an outer silk screen, a notch is formed at one corner of the inner silk screen, and a trapezoidal silk screen is formed on the inner side of the inner silk screen at a position corresponding to the notch, so A triangular silk screen is formed at the positions corresponding to the other three corners inside the silk screen of the inner ring.

The modular chip structure provided by this application is packaged with a packaging structure, and the second pad is exposed, which can realize the connection between the modular chip and the bottom plate, thereby forming an overall chip system. When it is necessary to replace the main chip with different configurations There is no need to change other chips and electrical structures in the chip system, just replace the main chip and solder the second pads with corresponding functions.

Description of drawings

In order to more clearly illustrate the specific implementation of the present invention or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the specific implementation or description of the prior art. Obviously, the accompanying drawings in the following description The drawings show some implementations of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative work.

FIG. 1 is a structural schematic diagram of a first viewing angle of a modular chip structure provided by an embodiment of the present invention;

FIG. 2 is a structural schematic diagram of a second perspective of a modular chip structure provided by an embodiment of the present invention;

3 is an electrical connection diagram of a modular chip structure provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a package structure in a chip system provided by an embodiment of the present invention.

In the figure: 1-substrate; 101-second pad; 102-decoupling capacitor; 2-main chip; 3-memory chip; 4-first power management chip; 5-second power management chip; 6-inner ring Silk screen; 601-notch; 7-outer ring silk screen; 8-trapezoidal screen; 9-triangular screen; 10-avoidance groove.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only It is a part of the embodiments of this application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

In the description of the embodiments of the present application, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner" and "outer" indicate The orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship that is usually placed when the product of the invention is used, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying Any device or element must have a specific orientation, be constructed and operate in a specific orientation and therefore should not be construed as limiting the invention. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions, and should not be construed as indicating or implying relative importance.

Furthermore, the terms "horizontal", "vertical" and the like do not imply that a component is absolutely level or overhanging, but may be slightly inclined. For example, "horizontal" only means that its direction is more horizontal than "vertical", and it does not mean that the structure must be completely horizontal, but can be slightly inclined.

In the description of the embodiments of this application, it should also be noted that, unless otherwise specified and limited, the terms "setting", "installation", "communication", and "connection" should be understood in a broad sense, for example, it can be fixed The connection can also be a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

As used herein, the term "and/or" includes any one and any combination of any two or more of the associated listed items.

For ease of description, spatial terms such as "on," "upper," "below," and "lower" may be used herein to describe the relationship between one element and another as shown in the drawings. Component relationships. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

The terms used herein are only used to describe various examples, and are not used to limit the present disclosure. Unless the context clearly dictates otherwise, singular forms are intended to include plural forms. The terms "comprising", "comprising" and "having" enumerate the presence of stated features, quantities, operations, members, elements and/or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and/or combinations thereof.

Variations in the shapes shown in the figures may occur due to manufacturing techniques and/or tolerances. Accordingly, examples described herein are not limited to the specific shapes shown in the drawings but include changes in shapes that occur during manufacture.

The features of the examples described herein can be combined in various ways that will be apparent after understanding the disclosure of this application. Furthermore, while the examples described herein have a variety of configurations, other configurations are possible, as will be apparent after understanding the disclosure of this application. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the realization of those skilled in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist , nor within the scope of protection required by the present application.

As shown in Figures 1-3, the present invention provides a modular chip structure, including a substrate 1 and a platform chip assembly; the platform chip assembly includes at least two main chips 2, and the side of the main chip 2 facing the substrate 1 is formed with multiple A plurality of second pads 101 are formed on the side of the substrate 1 away from the main chip 2, and the number of the second pads 101 includes at least two functional tubes of the first pads contained in the main chip 2. number of feet.

Compared with the prior art, the modular chip structure provided by the present invention has the following advantages:

In the modular chip structure provided by the present invention, since each first pad on the main chip 2 has a corresponding function, and the platform chip assembly in this application includes at least two main chips 2 of different models, therefore, this According to the application, a plurality of second pads 101 are formed on the side of the substrate 1 away from the main chip 2, and the number of the second pads 101 includes at least two functional pins of the first pads included in the main chip 2. Quantity, so that one substrate 1 can have all the functions of at least two main chips 2, when any one of the main chips 2 is connected to the substrate 1, only the first pad and the second pad 101 of the corresponding function need to be welded , and connect the second bonding pad 101 with the corresponding functional interface in the chip system through wires, so as to realize the implementation of the corresponding function of the main chip 2 .

It can be understood that, since different types and configurations of main chips 2 have different corresponding functions, when replacing the main chip 2, only the second pads 101 to be used need to be soldered to complete the different main chips. 2 are functionally compatible.

Preferably, in the present application, both the first pad and the second pad 101 are made of metal material, and the cross section of the second pad 101 is circular.

In order to ensure that the replaced main chip 2 will not affect other chips and electrical structures arranged on the substrate 1, therefore, in the present application, the package sizes of the multiple main chips 2 are the same, and the first pads have the same size. Correspondingly, the number of pins on the main chip 2 is the same, and the definitions of the pins are compatible with each other, and the iterative upgrade of the product main chip 2 can be realized by reflow soldering during soldering.

As shown in Figure 1, the modular chip structure provided by the present invention also includes a memory chip 3, the memory chip 3 is arranged on the side of the substrate 1 away from the second pad 101, and the memory chip 3 is arranged close to the main chip 2, and the memory chip 3 3 communicates with the main chip 2.

Preferably, the memory chip 3 in this application is an LPDDR4X chip.

As shown in Figure 1, the modular chip structure provided by the present invention also includes a first power management chip 4 and a second power management chip 5, both of which are arranged on the base plate 1 away from One side of the second pad 101, and the first power management chip 4 and the second power management chip 5 are arranged around the main chip 2; the first power management chip 4 is connected to the main chip 2, and the second power management chip 5 is respectively connected to the main chip 2 The memory chip 3 is connected with the main chip 2 .

In this application, the input terminal of the first power management chip 4 and the input terminal of the second power management chip 5 are powered on and output different levels to the main chip 2 and the LPDDR4X chip according to the time sequence. Both the first power management chip 4 and the second power management chip 5 are laid out on the substrate 1 , and the second power management chip 5 outputs different default fixed levels and provides them to the main chip 2 and the memory chip 3 respectively after being powered on.

The first power management chip 4 outputs two circuits of higher current level networks to provide to the main chip 2 . As shown in Figure 3, since the first power management chip 4, the second power management chip 5, the memory chip 3 and the main chip 2 are integrated on the substrate 1 in the present application, the power supply network can be connected to the main chip 2 and the main chip 2. The traces between the memory chips 3 are very short, so that the impedance of the traces can be reduced to a certain extent. However, thinner traces will cause current limitation and cause local heating and voltage drops, which will easily cause system instability, and larger traces will increase impedance. Therefore, as shown in Figure 2, the substrate 1 in this application deviates from One side of the main chip 2 is designed to reserve a plurality of decoupling capacitors 102 .

By selecting different decoupling capacitors 102, the resonant frequency can be improved, the high-frequency impedance can be reduced, and the parasitic inductance loop can be reduced, thereby providing a more stable and reliable power supply quality.

What needs to be added here is that the decoupling capacitor 102 in this application is located on the side of the substrate 1 away from the main chip 2 and is close to the closest position of the power domain pin network of the main chip 2 . Preferably, the plurality of decoupling capacitors 102 in this application at least include decoupling capacitors 102 with capacitance values of 0.1 μF, 10 nF and 100 pF, so as to correspond to different signal frequency bands and filter out high-frequency noise at different frequency ends, so as to improve the power supply network The high-frequency noise in the medium has a better filtering effect and smoothes the fluctuation of the power network voltage. At the same time, these decoupling capacitors 102 have a small ESR/ESL (equivalent resistance, equivalent inductance) to provide a low-impedance loop. Satisfying the dynamic response of the power domain; the capacitance and placement of the decoupling capacitor 102 can improve the integrity of the power signal and optimize the AC target impedance value corresponding to the high frequency in the power network.

In some implementations, it is not necessary to mount the decoupling capacitor 102 on the back of the substrate 1 by optimizing the layout and routing. The AC impedance value corresponding to the high-frequency point can be improved by optimizing the layout and routing. This is in the actual simulation. It can be clearly seen through the simulated AC impedance curve, but the above two methods can meet the target impedance value required by the platform chip.

Optionally, as shown in FIG. 4 , in the present application, a plurality of second pads 101 are distributed in an array or distributed along the circumference of the substrate 1 or a part of the second pads 101 is distributed in an array, and another part of the second pads is distributed in an array. 101 are distributed around the circumference of the arrayed second pads 101 .

Preferably, in the present application, the second pad 101 is a metal pad formed by immersion gold on the back surface of the metal bare copper. The coating of the pad is glossy and smooth, has strong conductivity, high solderability, and the pad is exposed to air oxidation resistance. Well, long life.

The metallized second pad 101 is connected to the first pad of the corresponding functional pin of the main chip 2 by wiring after passing through the hole VIA.

It can be understood that, in order to facilitate routing, therefore, in this application, three rows of second pads 101 uniformly distributed along the circumference of the substrate 1 are formed near the periphery of the substrate 1, and the diameters of the second pads 101 are uniform. is 0.6MM, the center-to-center distance between adjacent second pads 101 uniformly distributed along the circumference of the substrate 1 is 1.27MM, and the second pads 101 distributed inward in a matrix form are arbitrarily adjacent to the second pads The center-to-center distances of the top, bottom, left, and right sides of 101 are both 1.8MM, and the center-to-center distances between the adjacent second pads 101 that are evenly distributed in the circumferential direction and the second pads 101 that are distributed in a matrix are also 1.27MM.

In this embodiment, there is a sufficient distance between the second pads 101 , therefore, the reliability of automatic reflow soldering can be satisfied without the need for a stepped stencil of a special process.

What needs to be added here is that in order to ensure that the functional pins of the main chip 2 can be completely connected, as shown in Figure 3, the corresponding functions of the interface provided by this application include modular power supply pins, GND network , high-speed MIP I-CS I and high-speed MIP I-DS I interface corresponding to video input and output, LVDS interface, high-speed PC I E interface, general serial port UART, SPI interface, EMMC storage interface, PAR-CS I parallel video input interface, JTAG, chip debugging interface, RGM I I gigabit network interface, QSP I interface, I I C interface, CAN-FD interface, TDM interface, I I S interface and general GP I O interface, etc., which meet the interface configuration of most current customer product designs Not only has 4-screen output display and 9-way camera video input, but also has the current smallest chip modular size, which not only reserves a wealth of interfaces for potential product design requirements, but is also more suitable for meeting the needs of miniaturized structural design of complete machine products .

In addition, the present invention also provides a modular chip system, including a base plate, a packaging structure, and the above-mentioned modular chip structure; the packaging structure encapsulates the modular chip structure, and exposes the modular chip structure with the second pad 101 side.

The modular chip structure provided by the present application is packaged with a packaging structure, and the second pad 101 is exposed, which can realize the connection between the modular chip and the bottom plate, thereby forming an overall chip system. When it is necessary to replace the main chip with different configurations 2, there is no need to change other chips and electrical structures in the chip system, only the main chip 2 is replaced, and the second pads 101 with corresponding functions are soldered.

Preferably, as shown in FIG. 4 , the packaging structure in this application includes an inner ring silk screen 6 and an outer ring silk screen 7 , one corner of the inner ring silk screen 6 is formed with a notch 601 , and the inner side of the inner ring silk screen 6 corresponds to the notch. A trapezoidal silkscreen 8 is formed at the position of 601, and a triangular silkscreen 9 is formed at positions corresponding to the other three corners inside the inner ring silkscreen 6 .

It can be understood that, as shown in Figure 4, the inner ring silk screen 6 and the outer ring silk screen 7 in this application are arranged at intervals. Other components can be arranged arbitrarily without affecting the modular chip structure in this application. In order to avoid errors in the installation direction between the modular chip and the base plate, in this application, a notch 601 is formed at a corner of the inner ring silk screen 6, and a trapezoidal silk screen 8 is formed on the inner side of the inner ring silk screen 6 corresponding to the notch 601. Therefore, it can be clearly distinguished from the triangular silk screen 9 at the other three corners, so that the polarity can be quickly known, and the problem of wrong installation direction can be avoided.

What needs to be supplemented here is that since the decoupling capacitor 102 is also formed on the substrate 1 in the above scheme, in order to avoid the decoupling capacitor 102 from affecting the connection and installation between the substrate 1 and the base plate, corresponding decoupling capacitors 102 can also be placed on the base plate. The region of the coupling capacitor 102 forms an avoidance groove 10. When the substrate 1 has the decoupling capacitor 102, interference between the region of the decoupling capacitor 102 and the base plate can be avoided, so that the connection between the modular chip structure and the base plate can be smoother.

What needs to be further supplemented here is that since in some implementations there is no need to set the decoupling capacitor 102, the decoupling capacitor 102 in this application adopts a chip structure. When the decoupling capacitor 102 is not needed, the corresponding position on the bottom plate There is no need to form the avoidance groove 10 described above, so wiring can be facilitated.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (10)

1. A modular chip structure is characterized by comprising a substrate and a platform chip assembly;

the platform chip assembly comprises at least two main chips, wherein the main chips face one side of the substrate is provided with a plurality of first bonding pads, the substrate deviates from one side of the main chips is provided with a plurality of second bonding pads, and the number of the second bonding pads comprises at least two functional pins of the first bonding pads, which are contained in the main chips.

2. The modular chip structure of claim 1, wherein the first and second pads are made of a metal material, and the second pad has a circular cross-section.

3. The modular chip architecture of claim 1, wherein the packages of the plurality of main chips are the same size and the first pads are the same size.

4. The modular chip structure of claim 1, further comprising a memory chip, wherein the memory chip is disposed on a side of the substrate away from the second bonding pad, and the memory chip is disposed close to the main chip, and the memory chip and the main chip are interconnected.

5. The modular chip structure of claim 4, further comprising a first power management chip and a second power management chip, wherein the first power management chip and the second power management chip are both disposed on a side of the substrate away from the second pad, and the first power management chip and the second power management chip are disposed around the main chip;

the first power management chip is connected with the main chip through a circuit, and the second power management chip is respectively connected with the memory chip and the main chip.

6. The modular chip structure according to claim 1, wherein at least one of the main chips is connected to the substrate, and a plurality of decoupling capacitors are formed on a side of the substrate facing away from the main chip.

7. The modular chip structure of claim 2, wherein the second pads are arranged in an array or along a circumference of the substrate or a portion of the second pads are arranged in an array and another portion of the second pads are arranged around the circumference of the second pads in an array.

8. The modular chip structure according to claim 7, wherein the second pads have a diameter of 0.6MM, and the second pads uniformly distributed along the circumferential direction of the substrate have a center-to-center distance of 1.27MM between adjacent second pads, and the second pads distributed in a matrix form have a center-to-center distance of 1.8MM between adjacent second pads, and the second pads uniformly distributed in the circumferential direction have a center-to-center distance of 1.27MM between adjacent second pads distributed in a matrix form.

9. A chip system comprising a backplane, a package structure, and the modular chip structure of any of claims 1-8 above;

the packaging structure packages the modular chip structure inside, and exposes one side of the modular chip structure, which is provided with the second bonding pad.

10. The chip system according to claim 9, wherein the package structure includes an inner ring screen printing and an outer ring screen printing, a notch portion is formed at one corner of the inner ring screen printing, a trapezoidal screen printing is formed on an inner side of the inner ring screen printing and at a position corresponding to the notch portion, and a triangular screen printing is formed at positions corresponding to the other three corners of the inner ring screen printing.

Images